Storage device and electronic device

Abstract

The present disclosure provides a storage device and an electronic device. The storage device comprises N storage units, N is an integer greater than 1; each storage unit receives a clock signal, and the clock signals of the N storage units share the same wire; the clock period of the clock signal is greater than 2 times the pulse width of the clock signal; the first storage unit of the N storage units further receives an initial enable signal, and is used to generate an output enable signal of the first storage unit based on the initial enable signal and the clock signal; the i-th storage unit of the N storage units further receives an output enable signal of the (i-1)-th storage unit, and is used to generate an output enable signal of the i-th storage unit based on the output enable signal of the (i-1)-th storage unit and the clock signal, i is an integer greater than 1 and less than or equal to N, so that the first to N-th storage units enter the power-on establishment state in turn.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a storage device and an electronic device. Background Art

[0002] With the rapid development of big data technology, the demand for integrated storage and computing chips is growing rapidly. Storage chips are composed of many small storage units, each of which can read and write data independently. A single external power supply is used to generate several high-voltage power supplies or low-voltage power supplies on the chip for reading, erasing, and writing operations of the storage units.

[0003] During the voltage establishment process, the memory cell will generate a large peak power consumption; if too many memory cells are powered on to establish the voltage at the same time, it will cause a huge power supply current, which may lead to the risk of power-on failure in severe cases.

[0004] In the related art, each memory cell has an independent enable signal for independently controlling the circuit in the memory cell; however, each memory cell is configured with a separate enable signal, which occupies a large amount of wiring channel resources.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The present disclosure provides a storage device and an electronic device. The storage device can realize sequential power-on of the first to Nth storage units, ensuring that fewer storage units are in the power-on establishment state at the same time, avoiding the generation of huge power supply current, and reducing the peak power consumption during the power-on process of the storage device. At the same time, the clock signals of the N storage units share the same wiring, and the input enable signal of the storage unit is generated by the previous storage unit. There is no need to configure an enable signal for each storage unit separately, which can save wiring channel resources.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] An embodiment of the present disclosure provides a storage device, comprising: N is an integer greater than 1; each storage unit receives a clock signal, and the clock signals of the N storage units share the same routing; the clock period of the clock signal is greater than twice the pulse width of the clock signal; the first storage unit among the N storage units also receives an initial enable signal, which is used to generate an output enable signal of the first storage unit based on the initial enable signal and the clock signal; the i-th storage unit among the N storage units also receives an output enable signal of the (i-1)-th storage unit, which is used to generate an output enable signal of the i-th storage unit based on the output enable signal of the (i-1)-th storage unit and the clock signal, where i is an integer greater than 1 and less than or equal to N, so that the 1st to N-th storage units enter the power-on establishment state in sequence.

[0009] In some exemplary embodiments of the present disclosure, the initial enable signal and the output enable signals of the N memory cells share a same wiring.

[0010] In some exemplary embodiments of the present disclosure, in each clock cycle of the clock signal, k storage units enter the power-on setup state, where k is a positive integer and k+i<N.

[0011] In some exemplary embodiments of the present disclosure, the clock period is greater than the time each memory cell is in the power-up setup state.

[0012] In some exemplary embodiments of the present disclosure, each storage unit includes a first input port, a second input port, a first output port, and a second output port; the first output port of the (i-1)th storage unit is connected to the first input port of the i-th storage unit for transmitting the clock signal; the second output port of the (i-1)th storage unit is connected to the second input port of the i-th storage unit for transmitting the output enable signal of the (i-1)th storage unit.

[0013] In some exemplary embodiments of the present disclosure, each memory cell includes an even number of inverters, the output ends of the even number of inverters of the (i-1)th memory cell serve as the first output port of the (i-1)th memory cell, and the input ends of the even number of inverters of the i-th memory cell serve as the first input port of the i-th memory cell for transmitting the clock signal.

[0014] In some exemplary embodiments of the present disclosure, the clock cycle includes 1 pulse, and the time difference between powering on the (i-1)th storage unit and the i-th storage unit is the clock cycle, wherein the clock cycle is greater than 2 times the pulse width of the 1 pulse.

[0015] In some exemplary embodiments of the present disclosure, each clock cycle includes k pulses, the clock cycle is greater than twice the sum of the pulse widths of the k pulses, the time difference between the power-on of the 1st storage unit and the (1+k)th storage unit is the clock cycle, the time difference between the power-on of the i-th storage unit and the (i+k)-th storage unit is the clock cycle, k is an integer greater than 1, and k+i<N.

[0016] In some exemplary embodiments of the present disclosure, each storage unit includes a trigger; the trigger of the first storage unit is used to latch the initial enable signal as the output enable signal of the first storage unit at the first rising edge or the first falling edge of the clock signal when the initial enable signal is at the first level; the trigger of the i-th storage unit is used to latch the output enable signal of the (i-1)th storage unit as the output enable signal of the i-th storage unit at the i-th rising edge or the i-th falling edge of the clock signal when the output enable signal of the (i-1)th storage unit is at the first level.

[0017] In some exemplary embodiments of the present disclosure, each memory cell further includes a voltage conversion module and a memory array; the voltage conversion module in each memory cell is used to receive the respective output enable signal of each memory cell, and generate the output voltage of the voltage conversion module according to the respective output enable signal of each memory cell and the power supply voltage, and the output voltage of the voltage conversion module is used to power the memory array, so that when the respective output enable signal of each memory cell is generated, the memory cell enters the power-on establishment state.

[0018] An embodiment of the present disclosure provides an electronic device, comprising any of the above-mentioned storage devices.

[0019] In a storage device provided by an embodiment of the present disclosure, the first storage unit among N storage units receives an initial enable signal and a clock signal, and generates an output enable signal of the first storage unit based on the initial enable signal and the clock signal; the i-th storage unit receives the output enable signal and the clock signal of the (i-1)-th storage unit, and generates an output enable signal of the i-th storage unit based on the output enable signal and the clock signal of the (i-1)-th storage unit. This can enable the first to N-th storage units to enter the power-on establishment state in sequence, ensuring that fewer storage units are in the power-on establishment state at the same time, avoiding the generation of huge power supply current, and reducing the peak power consumption during the power-on process of the storage device; at the same time, the clock signals of the N storage units share the same routing, and the input enable signal of the storage unit is generated by the previous storage unit. There is no need to configure an enable signal for each storage unit separately, which can save wiring channel resources.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0022] Figure 1 is a schematic diagram of a storage device in the related art.

[0023] Figure 2 is a schematic diagram of a storage device in an exemplary embodiment of the present disclosure.

[0024] Figure 3 yes Figure 2 Schematic diagram of the internal structure of one of the storage units in the storage device shown.

[0025] Figure 4 yes Figure 2 A power-on timing diagram corresponding to the storage device shown.

[0026] Figure 5 yes Figure 2 Another power-on timing diagram corresponding to the storage device shown.

[0027] Figure 6 It is a structural diagram of the PUMP in an exemplary embodiment of the present disclosure.

[0028] Figure 7 FIG. 4 is a schematic structural diagram of an LDO in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0030] The features, structures or characteristics described in the present disclosure may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0031] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in at least one hardware module or integrated circuit, or in different networks and / or processor devices and / or microcontroller devices.

[0032] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all content and steps, nor must they be executed in the order described. For example, some steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0033] In addition, in the description of the present disclosure, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of at least one element or component; the terms "comprising", "including" and "having" are used to express open-ended inclusion and mean that additional elements or components may exist in addition to the listed elements or components; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0034] Figure 1 is a schematic diagram of a storage device in the related art.

[0035] refer to Figure 1 In the related art, a storage device 100 includes multiple storage units. Taking four storage units (storage unit 101, storage unit 102, storage unit 103, and storage unit 104) as an example, in order to reduce the peak current power consumption when the storage unit is powered on, each storage unit has an independent enable signal for independently controlling the circuit in the storage unit; wherein, the enable signal EN1 is used to control the storage unit 101, the enable signal EN2 is used to control the storage unit 102, the enable signal EN3 is used to control the storage unit 103, and the enable signal EN4 is used to control the storage unit 104.

[0036] When the storage device 100 is powered on, the enable signals EN1 , EN2 , EN3 and EN4 need to be activated in sequence to ensure that only one storage unit is working in the same time period.

[0037] However, a large-capacity storage device generally has a large number of storage units, and each storage unit is configured with a separate enable signal, which occupies a large amount of wiring channel resources.

[0038] For example, suppose a storage device with a capacity of 8GB consists of 32 storage units with a capacity of 256MB; each time a storage unit is powered on, 32 enable signal lines are required. These enable signals are all globally wired, occupying a large amount of layout wiring resources.

[0039] Moreover, the number of enable signal lines increases with the number of storage units. If the capacity of the storage device changes from 8GB to 32GB, 128 storage units with a capacity of 256MB are required, that is, 128 enable signal lines are required. The larger the capacity of the storage device, the more wiring resources are occupied.

[0040] In response to the technical problems existing in the above-mentioned related technologies, the embodiments of the present disclosure provide a storage device for solving at least one or all of the above-mentioned technical problems.

[0041] An embodiment of the present disclosure provides a storage device, which includes N storage units, where N is an integer greater than 1; each storage unit receives a clock signal, and the first storage unit among the N storage units also receives an initial enable signal, which is used to generate an output enable signal of the first storage unit based on the initial enable signal and the clock signal; the i-th storage unit among the N storage units also receives the output enable signal of the (i-1)-th storage unit, which is used to generate an output enable signal of the i-th storage unit based on the output enable signal of the (i-1)-th storage unit and the clock signal, where i is an integer greater than 1 and less than or equal to N, so that the 1st to Nth storage units enter the power-on establishment state in sequence.

[0042] The storage device in the embodiments of the present disclosure may be any device having a storage function, for example, a storage chip, and the present disclosure does not limit this.

[0043] Specifically, refer to Figure 2 The storage device 200 may include storage unit 1, storage unit 2, storage unit 3, storage unit 4, ..., storage unit N-3, storage unit N-2, storage unit N-1 and storage unit N; the capacity of each storage unit may be the same or different.

[0044] Specifically, each storage unit has two input signals (ENi-1 and CLKi-1) and two output signals (ENi and CLKi), EN0 represents an initial enable signal, CLK0 represents an initial clock signal, ENi-1 represents an input enable signal of the (i-1)th storage unit, CLKi-1 represents an input clock signal of the (i-1)th storage unit, ENi represents an output enable signal of the ith storage unit, and CLKi represents an output clock signal of the ith storage unit.

[0045] In the exemplary embodiment, the clock signals of the N storage units share the same wire, and the initial enable signal and the output enable signals of the N storage units can also share the same wire.

[0046] Specifically, the signals between adjacent storage units are sequentially connected, and the output enable signal and the output clock signal of the previous storage unit are respectively used as the input enable signal and the input clock signal of the next storage unit, so that only two wiring channel resources are required to control whether all the storage units work.

[0047] In the embodiment of the present disclosure, the initial clock signal CLK0 and the output clock signal CLKi of each storage unit can be the same clock signal.

[0048] It should be noted that, in the embodiment of the present disclosure, Figure 2 In the storage device 200 shown, the number N of storage units is an integer greater than 15, which is merely illustrative; in actual applications, the number of storage units can be set according to actual conditions, and the present disclosure does not limit this.

[0049] Specifically, the storage unit 1 (i.e., the first storage unit) receives the initial enable signal EN0 and the initial clock signal CLK0, and generates the output enable signal EN1 of the storage unit 1 according to the initial enable signal EN0 and the initial clock signal CLK0; the storage unit 2 receives the output enable signal EN1 of the storage unit 1 and the output clock signal CLK1, and generates the output enable signal EN2 of the storage unit 2 according to the output enable signal EN1 of the storage unit 1 and the output clock signal CLK1; the storage unit 3 receives the output enable signal EN2 of the storage unit 2 and the output clock signal CLK2, and generates the output enable signal EN3 of the storage unit 3 according to the output enable signal EN2 of the storage unit 2 and the output clock signal CLK2;..., the storage unit N receives the output enable signal ENn-1 of the storage unit N-1 and the output clock signal CLKn-1, and generates the output enable signal ENn of the storage unit N according to the output enable signal ENn-1 of the storage unit N-1 and the output clock signal CLKn-1.

[0050] Among them, the output enable signal EN1 of storage unit 1 is used to enable storage unit 1 to enter the power-on establishment state, the output enable signal EN2 of storage unit 2 is used to enable storage unit 2 to enter the power-on establishment state,..., the output enable signal ENn of storage unit N is used to enable storage unit N to enter the power-on establishment state, thereby realizing the sequential entry of the 1st to Nth storage units into the power-on establishment state.

[0051] In an exemplary embodiment, a clock period of the clock signal is greater than twice a pulse width of the clock signal.

[0052] In some embodiments, in each clock cycle of the clock signal, k storage units enter the power-on setup state, k is a positive integer, and k+i<N; that is, in each clock cycle of the clock signal, one or more storage units enter the power-on setup state.

[0053] In some embodiments, the clock period is greater than the time each memory cell is in the power-up setup state to ensure that each memory cell enters the power-up setup state in sequence.

[0054] Specifically, the clock period of the clock signal is much larger than the pulse width of the clock signal. For example, the clock period of the clock signal is at the US (microsecond) level or longer, and the pulse width of the clock signal is at the NS (nanosecond) level.

[0055] In a storage device provided by an embodiment of the present disclosure, the first storage unit among N storage units receives an initial enable signal and a clock signal, and generates an output enable signal of the first storage unit based on the initial enable signal and the clock signal; the i-th storage unit receives the output enable signal and the clock signal of the (i-1)-th storage unit, and generates an output enable signal of the i-th storage unit based on the output enable signal and the clock signal of the (i-1)-th storage unit. This can enable the first to N-th storage units to enter the power-on establishment state in sequence, ensuring that fewer storage units are in the power-on establishment state at the same time, avoiding the generation of huge power supply current, and reducing the peak power consumption during the power-on process of the storage device; at the same time, the clock signals of the N storage units share the same routing, and the input enable signal of the storage unit is generated by the previous storage unit. There is no need to configure an enable signal for each storage unit separately, which can save wiring channel resources.

[0056] In some embodiments, the clock signals of N storage units share the same routing, and the enable signals of N storage units also share the same routing. Therefore, only two wiring channel resources are needed to control whether all the storage units are working. Compared with the related art that requires N wiring channel resources, this greatly saves wiring channel resources. At the same time, the storage device provided by the embodiment of the present disclosure, when it has a large number of storage units, only two wiring channel resources are needed to control whether all the storage units are working. That is, the channel wiring resources required to be used in the storage device provided by the embodiment of the present disclosure are independent of the number of storage units, and can be applied to storage devices with larger capacity.

[0057] In an exemplary embodiment, each storage unit includes a first input port, a second input port, a first output port, and a second output port; the first output port of the (i-1)th storage unit is connected to the first input port of the i-th storage unit for transmitting a clock signal; the second output port of the (i-1)th storage unit is connected to the second input port of the i-th storage unit for transmitting an output enable signal of the (i-1)th storage unit.

[0058] For example, Figure 3 yes Figure 2 The schematic diagram of the internal structure of one of the storage units in the storage device shown is a schematic diagram. Taking the i-th storage unit as an example, the i-th storage unit may include a first input port 301, a second input port 302, a first output port 303, and a second output port 304, wherein the first input port 301 is used to receive the output clock signal CLKi-1 of the (i-1)-th storage unit, the second input port 302 is used to receive the output enable signal ENi-1 of the (i-1)-th storage unit, the first output port 303 is used to output the output enable signal CLKi of the i-th storage unit, and the second output port is used to output the output enable signal ENi of the i-th storage unit.

[0059] In an exemplary embodiment, each memory cell may include an even number of inverters, the output ends of the even number of inverters of the (i-1)th memory cell serve as the first output port of the (i-1)th memory cell, and the input ends of the even number of inverters of the i-th memory cell serve as the first input port of the i-th memory cell for transmitting a clock signal.

[0060] Continue to refer Figure 3Each storage unit can include an even number of inverters, for example, 2 inverters 305; the outputs of the 2 inverters of the (i-1)th storage unit serve as the first output of the (i-1)th storage unit, and the inputs of the 2 inverters 305 of the ith storage unit serve as the first input port 301 of the ith storage unit to transmit the clock signal CLKi-1; similarly, the outputs of the 2 inverters 305 of the ith storage unit serve as the first output 303 of the ith storage unit, and the inputs of the 2 inverters of the (i+1)th storage unit serve as the first input port of the (i+1)th storage unit to transmit the clock signal CLKi.

[0061] In the embodiments of the present disclosure, the inclusion of an even number of inverters in each storage unit can provide long line driving capability for each storage unit.

[0062] In exemplary embodiments, each storage unit can include a flip-flop; the flip-flop of the 1st storage unit is configured to latch the initial enable signal as the output enable signal of the 1st storage unit at the first rising or falling edge of the clock signal when the initial enable signal is at a first level (e.g., high level); the flip-flop of the ith storage unit is configured to latch the output enable signal of the (i-1)th storage unit as the output enable signal of the ith storage unit at the ith rising or falling edge of the clock signal when the output enable signal of the (i-1)th storage unit is at the first level.

[0063] In the embodiments of the present disclosure, the flip-flop can be a D flip-flop (DFF), or can be another type of flip-flop. In the following examples, a D flip-flop is used as an example.

[0064] Continuing to refer to Figure 3 , still taking the ith storage unit as an example, the D flip-flop 306 in the ith storage unit receives the output clock signal CLKi-1 and the output enable signal ENi-1 of the (i-1)th storage unit, and latches the output enable signal ENi-1 of the (i-1)th storage unit as the output enable signal ENi of the ith storage unit at the ith rising or falling edge of the clock signal when the output enable signal CLKi-1 of the (i-1)th storage unit is at a high level.

[0065] Exemplarily, Figure 4 is Figure 2 a power-on timing diagram corresponding to the storage device shown in FIG. 4, referring to Figure 4, CLK0 represents the clock signal, the clock period of the clock signal is represented by T2, one clock period T2 of the clock signal includes one pulse, the clock period is greater than twice the pulse width of the one pulse, and each pulse signal is used to start one storage unit; the clock period T2 of the clock signal is much greater than the pulse width TH of the clock signal, and the width of the pulse width TH can ensure that the trigger is latched normally; the clock period T2 of the clock signal is greater than the time each storage unit is in the power-on establishment state, which can ensure that each storage unit enters the power-on establishment state in turn; and the clock period T2 of the clock signal is equal to the time difference between the power-on of the (i-1)th storage unit and the i-th storage unit.

[0066] refer to Figure 4 Specifically, when the initial enable signal EN0 is at a low level, the enable signals EN1, EN2, ..., ENn that control all storage units are all at a low level, and all storage units do not work; after the EN0 initial enable signal becomes a high level, taking the triggers in each storage unit as rising-edge latched triggers as an example, the trigger in the first storage unit latches the initial enable signal EN0 as the output enable signal EN1 of the first storage unit at the first rising edge of the clock signal CLK0, EN1 is used to start the first storage unit, EN1 becomes a high level after a short trigger delay, and the first storage unit starts to start.

[0067] Specifically, the output enable signal EN1 of the first storage unit is input to the second storage unit. The trigger in the second storage unit latches EN1 as the output enable signal EN2 of the second storage unit at the second rising edge of the clock signal CLK0. EN2 is used to start the second storage unit. After a short trigger delay, EN2 becomes a high level, and the second storage unit starts to start. At this time, the two storage units are already in the started state.

[0068] Similarly, after the nth rising edge of the clock signal CLK0, the output enable signal ENn of the Nth storage unit becomes high. At this time, all enable signals become high, and all storage units (i.e., N storage units) are in the startup state. The startup time between adjacent storage units differs by an interval time T2.

[0069] In the embodiment of the present disclosure, the size of the clock period T2 of the clock signal can be adjusted so that each storage unit can establish a voltage within the T2 time, thereby ensuring that the number of storage units that are simultaneously in the power-on establishment state remains basically at one; since the maintenance voltage power consumption of each storage unit is usually significantly lower than the power consumption during the establishment process, the number of storage units that are simultaneously in the power-on establishment state remains basically at one, which can greatly reduce the peak current of the storage device.

[0070] Continue to refer Figure 4 After the initial enable signal EN0 becomes low, the trigger in the first storage unit is reset, and the output enable signal EN1 of the first storage unit becomes low; after EN1 becomes low, the trigger in the second storage unit is reset, and the output enable signal EN2 of the second storage unit becomes low, and so on. The initial enable signal EN0 becoming low will quickly reset the enable signal of each storage unit in sequence, and all enable signals will be forced to become low, and all storage units will not work.

[0071] In an exemplary embodiment, each clock cycle may include k pulses, where k is an integer greater than 1 and k+i<N; the clock cycle is greater than twice the sum of the pulse widths of the k pulses; specifically, the clock cycle may be much greater than the pulse width to ensure that each storage unit enters the power-on setup state in sequence.

[0072] In an exemplary embodiment, the time difference between the power-on of the 1st storage unit and the (1+k)th storage unit is a clock cycle, and the time difference between the power-on of the i-th storage unit and the (i+k)-th storage unit is a clock cycle, that is, k adjacent storage units are a group, and k storage units enter the power-on establishment state in turn in each clock cycle.

[0073] The following description is made by taking an example where two pulses are included in each clock cycle, but the present disclosure is not limited thereto.

[0074] For example, Figure 5 yes Figure 2 Another power-on timing diagram corresponding to the storage device shown is shown in FIG. Figure 5 , the clock signal CLK0 includes two pulses within one clock cycle T2, each pulse is used to activate one memory cell, that is, two pulses within one clock cycle form a group, and each group of pulses activates two memory cells. The clock signal CLK0 has two adjacent pulse signals within each clock cycle T2, where the pulse period T1 of the pulse signal is relatively short, which can be on the order of tens of nanoseconds.

[0075] Specifically, when the initial enable signal EN0 is at a low level, the enable signals EN1, EN2, ..., ENn controlling all storage units are all at a low level, and all storage units do not work; after the EN0 initial enable signal becomes a high level, taking the triggers in each storage unit as rising-edge latched triggers as an example, in the first clock cycle, the trigger in the first storage unit latches the initial enable signal EN0 as the output enable signal EN1 of the first storage unit at the first rising edge of the clock signal CLK0, and the trigger in the second storage unit latches the initial enable signal EN1 as the output enable signal EN2 of the second storage unit at the second rising edge of the clock signal CLK0, and EN2 becomes a high level after a T1 time period after EN1 becomes a high level. EN1 is used to start the first storage unit, and EN2 is used to start For the second storage unit, since the T1 time is relatively short, the first storage unit and the second storage unit are basically in the power-on setup state at the same time; in the second clock cycle, similarly, EN2 is latched as EN3 at the third rising edge of the clock signal CLK0, and EN3 is latched as EN4 at the fourth rising edge of CLK0. EN4 becomes high after a period of T1 after EN3 becomes high. EN3 is used to start the third storage unit, and EN4 is used to start the fourth storage unit. Since the T1 time is relatively short, the third storage unit and the fourth storage unit are basically in the power-on setup state at the same time; and so on, until the last clock cycle, ENn-1 and ENn are started; this is equivalent to starting the power-on operation of two storage units every longer T2 period, thereby shortening the overall power-on startup time of the storage device.

[0076] In the embodiment of the present disclosure, the number of pulses in the clock cycle of the clock signal can be set according to the power supply capacity in the same time period, so as to flexibly control the number of storage units entering the power-on establishment state in the same time period, thereby better balancing the startup time and power consumption indicators.

[0077] In an exemplary embodiment, each memory cell may further include a voltage conversion module and a memory array; wherein the voltage conversion module in each memory cell is used to receive the respective output enable signal of each memory cell, and generate the output voltage of the voltage conversion module according to the respective output enable signal of each memory cell and the power supply voltage, and the output voltage of the voltage conversion module is used to power the memory array, so that when the respective output enable signal of each memory cell is generated, the memory cell enters a power-on establishment state.

[0078] refer to Figure 3For example, still taking the i-th memory unit as an example, the i-th memory unit can include a voltage conversion module 307 and a memory array 308; wherein the voltage conversion module 307 can be a PUMP (charge pump) and / or a LDO (Low Dropout Regulator, low dropout linear regulator), configured to receive an output enable signal ENi of the i-th memory unit, generate an output voltage (VCC and / or VPMP) according to the output enable signal ENi and a power supply voltage VDD, and supply power to the memory array 308.

[0079] Specifically, referring to Figure 6 For example, still taking the i-th memory unit as an example, the PUMP in the i-th memory unit can include an oscillator 601, a driving unit 602, and a charge pump 603; wherein the oscillator 602 is configured to receive an enable signal ENi, and generate a clock signal OSC according to the enable signal ENi, and output the clock signal OSC to the driving unit 602 to generate two opposite phase clock signals CLK and CLKB, which are used to drive the charge pump 603 to raise the power supply voltage VCC to an output voltage VPMP.

[0080] Specifically, referring to Figure 7 For example, still taking the i-th memory unit as an example, the LDO power module in the i-th memory unit receives a reference voltage VREF and an enable signal ENi, and lowers the power supply voltage VCC to an output voltage VDD according to the reference voltage VREF and the enable signal ENi, and has a large load capacity.

[0081] The embodiments of the present disclosure further provide an electronic device including the memory device according to any of the above embodiments. The electronic device can be any terminal device and / or server, and the terminal device can be any one or more of a mobile phone, a tablet computer, a desktop computer, a notebook computer, a game console, a television, a vehicle-mounted terminal, a wearable smart device, etc.

[0082] It should be noted that the above figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present disclosure, and are not for limiting purposes. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of the processes. In addition, it is also easy to understand that the processes can be executed synchronously or asynchronously, for example, in multiple modules.

[0083] It should be understood that the number of any elements in the figures of the present disclosure is for illustration only and not for limiting purposes, and any naming is only for differentiation and does not have any limiting meaning.

[0084] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0085] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A storage device, characterized in that: include: N storage units, where N is an integer greater than 1; Each storage unit receives a clock signal, and the clock signals of the N storage units share a same wiring; a clock period of the clock signal is greater than twice a pulse width of the clock signal; The first storage unit among the N storage units further receives an initial enable signal, and is configured to generate an output enable signal of the first storage unit based on the initial enable signal and the clock signal; The i-th storage unit among the N storage units further receives an output enable signal of the (i-1)-th storage unit, and is configured to generate an output enable signal of the i-th storage unit based on the output enable signal of the (i-1)-th storage unit and the clock signal, where i is an integer greater than 1 and less than or equal to N, so that the 1st to Nth storage units enter a power-on setup state in sequence; Wherein, each clock cycle includes k pulses, the clock cycle is greater than twice the sum of the pulse widths of the k pulses, the time difference between the power-on of the 1st storage unit and the (1+k)th storage unit is the clock cycle, the time difference between the power-on of the i-th storage unit and the (i+k)-th storage unit is the clock cycle, k is an integer greater than 1, and k+i<N.

2. The storage device according to claim 1, wherein The initial enable signal and the output enable signals of the N storage units share a same wiring.

3. The storage device according to claim 1, wherein The clock cycle is greater than the time each storage unit is in the power-on setup state.

4. The storage device according to claim 1, wherein Each storage unit includes a first input port, a second input port, a first output port, and a second output port; The first output port of the (i-1)th storage unit is connected to the first input port of the i-th storage unit for transmitting the clock signal; The second output port of the (i-1)th storage unit is connected to the second input port of the i-th storage unit for transmitting an output enable signal of the (i-1)th storage unit.

5. The storage device according to claim 4, wherein: Each storage unit includes an even number of inverters, the output ends of the even number of inverters of the (i-1)th storage unit serve as the first output port of the (i-1)th storage unit, and the input ends of the even number of inverters of the i-th storage unit serve as the first input port of the i-th storage unit for transmitting the clock signal. The storage device according to claim 1 , wherein: The clock cycle includes one pulse, and the time difference between powering on the (i-1)th storage unit and the i-th storage unit is the clock cycle, wherein the clock cycle is greater than twice the pulse width of the one pulse.

7. The storage device according to claim 1, wherein: Each storage unit includes a flip-flop; The trigger of the first storage unit is used to latch the initial enable signal as the output enable signal of the first storage unit at the first rising edge or the first falling edge of the clock signal when the initial enable signal is at the first level; The trigger of the i-th storage unit is used to latch the output enable signal of the (i-1)th storage unit as the output enable signal of the i-th storage unit at the i-th rising edge or the i-th falling edge of the clock signal when the output enable signal of the (i-1)th storage unit is at the first level.

8. The storage device according to claim 1, wherein: Each storage unit also includes a voltage conversion module and a storage array; The voltage conversion module in each storage unit is used to receive the output enable signal of each storage unit and generate the output voltage of the voltage conversion module according to the output enable signal of each storage unit and the power supply voltage. The output voltage of the voltage conversion module is used to power the storage array, so that when the output enable signal of each storage unit is generated, the storage unit enters the power-on establishment state.

9. An electronic device, characterized in that: Comprising the storage device according to any one of claims 1 to 8.

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