Signal TDM distribution method, electronic device and medium based on FPGA

Abstract

The present invention relates to the field of computer technology, and in particular to a signal TDM distribution method based on FPGA, an electronic device and a medium. The method comprises step S1, obtaining a signal set between a first FPGA and a second FPGA; step S2, obtaining E s The optimal TDR value TDR(s,f1) corresponding to the case where there are f1 cables and s signals between the first FPGA and the second FPGA; Step S3, obtain E w The optimal TDR value TDR(w,f2) corresponding to the case where there are f2 cables and w signals between the first FPGA and the second FPGA; Step S4, if TDR(W,F) exists, the signal TDM allocation between the first FPGA and the second FPGA is determined based on all TDR(s,f1) and TDR(w,f2). The present invention improves the operation efficiency of the user design.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a signal TDM distribution method, electronic equipment and medium based on FPGA. Background Art

[0002] In the prototype verification and hardware simulation system, multiple field programmable gate arrays (FPGAs) are connected to each other through cables. Different parts of the chip design will be placed on each FPGA, and signals are connected between each part, resulting in some signals needing to be transmitted across the FPGA. For cross-FPGA signals, it is necessary to find the best path to reduce the transmission delay of the signal from the starting point through multiple FPGAs to the end point. At the same time, since the number of physical communication cables between FPGAs is limited, when the number of signals is greater than the number of cables, it is necessary to use time division multiplexing (TDM) technology to allow multiple signals to share a physical cable, thereby achieving correct signal transmission. Since time division multiplexing technology will significantly increase the transmission delay of a single signal, a larger time division multiplexing ratio (TDR) will result in a greater delay. At the same time, since there are different delay requirements between signals, different multiplexing ratios need to be given to different signals, so as to achieve a smaller overall transmission delay to meet the overall operating speed requirements of the system. It can be seen from this that how to achieve the optimal TDM allocation and improve the operating efficiency requirements of user designs have become technical problems that need to be solved urgently. Summary of the invention

[0003] The purpose of the present invention is to provide a signal TDM distribution method, electronic equipment and medium based on FPGA, so as to improve the operation efficiency of user design.

[0004] According to a first aspect of the present invention, there is provided a signal TDM distribution method based on FPGA, comprising:

[0005] Step S1: Obtain a signal set {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}, where E s is the sth signal between the first FPGA and the second FPGA, the value range of s is 1 to S, and S is the number of positive signals between the first FPGA and the second FPGA; E wis the wth signal between the first FPGA and the second FPGA, the value range of w is S+1 to W, and W is the sum of the number of forward signals and reverse signals between the first FPGA and the second FPGA; E s The upper limit of the delay between the first FPGA and the second FPGA is D s , D1>D2,...,>D s ,...,>D S ; E w The upper limit of the delay between the first FPGA and the second FPGA is D w , D S+1 >D S+2 >,...,>D w ,...,>D W ;

[0006] Step S2: Obtain E s The optimal TDR value TDR(s,f1) corresponding to the case where there are f1 cables and s signals between the first FPGA and the second FPGA, where the value range of f1 is 1 to F, and F is the total number of cables between the first FPGA and the second FPGA;

[0007] Step S3, obtain E in sequence w The optimal TDR value TDR(w,f2) corresponding to the case where there are f2 cables and w signals between the first FPGA and the second FPGA, where the value range of f2 is 2 to F, and the same cable can only transmit signals in the same direction;

[0008] Step S4: If TDR (W, F) exists, determine the signal TDM allocation between the first FPGA and the second FPGA based on all TDR (s, f1) and TDR (w, f2).

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the FPGA-based signal TDM distribution method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The present invention can obtain the optimal TDM allocation result when the upper limit of the delay of all signals between two FPGAs and the number of cables between the two FPGAs are known, thereby improving the operation efficiency of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a signal TDM distribution method based on FPGA provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a signal TDM distribution method based on FPGA, such as Figure 1 As shown, including:

[0017] Step S1: Obtain a signal set {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}, where E s is the sth signal between the first FPGA and the second FPGA, the value range of s is 1 to S, and S is the number of positive signals between the first FPGA and the second FPGA; E w is the wth signal between the first FPGA and the second FPGA, the value range of w is S+1 to W, and W is the sum of the number of forward signals and reverse signals between the first FPGA and the second FPGA; E s The upper limit of the delay between the first FPGA and the second FPGA is D s , D1>D2,...,>D s ,...,>D S ; Ew The upper limit of the delay between the first FPGA and the second FPGA is D w , D S+1 >D S+2 >,...,>D w ,...,>D W .

[0018] Among them, the first FPGA and the second FPGA can be any two FPGAs in the FPGA system that are interconnected by cables and have signal transmission. The signal between the first FPGA and the second FPGA refers to the signal transmitted through the cable between the first FPGA and the second FPGA. It should be noted that the forward signal refers to the signal transmitted from the first FPGA to the second FPGA, and the reverse signal refers to the signal transmitted from the second FPGA to the first FPGA. There may be both forward signals and reverse signals between the first FPGA and the second FPGA, or there may be only forward signals, that is, there are bidirectional signals. The existence of only forward signals is equivalent to a special case of the existence of bidirectional signals, and is also applicable to the method described in the embodiment of the present invention. The delay upper limit refers to the maximum delay of the signal passing through the first FPGA and the second FPGA. Through D1>D2,...,>D s ,...,>D S and D S+1 >D S+2 >,...,>D w ,...,>D W It can be seen that E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W The forward signal and the reverse signal are sorted in descending order according to the upper delay limit, and the forward signal is overall arranged before the reverse signal. The FPGA system can be a prototype verification system or a hardware simulation system of multiple FPGAs, the signal can be a signal in the user design, and the user design can be a chip design.

[0019] Step S2: Obtain E s The optimal TDR value corresponding to the case where there are f1 cables and s signals between the first FPGA and the second FPGA is TDR(s,f1), where the value range of f1 is 1 to F, and F is the total number of cables between the first FPGA and the second FPGA.

[0020] It should be noted that, by obtaining the optimal TDR value corresponding to each combination of f1 and s in step S2, it can be understood that TDR (s, f1) may exist or may not exist.

[0021] Step S3, obtain E in sequence w The optimal TDR value corresponding to the situation where there are f2 cables and w signals between the first FPGA and the second FPGA is TDR(w,f2), where the value range of f2 is 2 to F, and the same cable can only transmit signals in the same direction.

[0022] It should be noted that, by obtaining the optimal TDR value corresponding to each combination of f2 and w in step S3, it can be understood that TDR (w, f2) may exist or may not exist.

[0023] Step S4: If TDR (W, F) exists, determine the signal TDM allocation between the first FPGA and the second FPGA based on all TDR (s, f1) and TDR (w, f2).

[0024] It should be noted that if TDR(W,F) exists, it means that the W signals between the first FPGA and the second FPGA can be successfully TDM distributed on F cables. If it does not exist, it means that the W signals between the first FPGA and the second FPGA cannot be successfully TDM distributed on F cables. In this case, a corresponding prompt message can be generated, and the design can be adjusted and TDM distribution can be performed again using the method described in the embodiment of the present invention.

[0025] As an embodiment, the step S1 includes:

[0026] Step S11, obtaining initial winding information in the FPGA system.

[0027] Step S12: Generate a time margin (Slack) for each signal based on the initial winding information.

[0028] Step S13, obtaining the delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA, and determining the sum of the delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA and the time margin corresponding to the signal as the delay upper limit of the signal.

[0029] Step S14: Sort the signals between the first FPGA and the second FPGA according to the direction of each signal passing between the first FPGA and the second FPGA and the upper limit of the delay of each signal, and generate {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}.

[0030] It is understandable that by D1>D2,...,>D s ,...,>D S and D S+1 >D S+2 >,...,>D w ,...,>D W sorting, generating {E1,E2,...,E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}.

[0031] As an embodiment, the initial winding information in step S11 may be any initial winding information. Preferably, step S11 includes:

[0032] Step S111: Acquire the connection relationship between FPGAs in the FPGA system.

[0033] Among them, in step S111, it is specifically necessary to obtain the cable connection information between all FPGAs in the FPGA system.

[0034] Step S112: Determine the shortest routing path for each signal based on the connection relationship between the FPGAs.

[0035] Step S113: Based on the shortest path routing of all signals, perform average TDM distribution on the signals between every two interconnected FPGAs, and generate the initial routing information in the FPGA system.

[0036] It can be understood that average TDM distribution refers to evenly distributing the signals between two interconnected FPGAs to the cables between the two FPGAs. When it is impossible to divide them completely, more signals can be distributed to a smaller number of cables or less signals can be distributed to a smaller number of cables, so that the signals are distributed as evenly as possible on the cables between the two FPGAs.

[0037] As an embodiment, the step S12 includes:

[0038] Step S121 : acquiring an initial delay DA of each signal based on the initial wiring information of the FPGA system.

[0039] It should be noted that after all the signals are routed, the delay corresponding to each signal can be directly obtained through the timing tool, which will not be repeated here.

[0040] Step S122: Generate a time margin DS for each signal based on the initial delay DA of each signal and the preset delay DB of each signal:

[0041] DS=DB-DA.

[0042] It should be noted that the preset delay DB refers to the delay that the signal is expected to reach.

[0043] As an embodiment, the step S2 includes:

[0044] Step S21, set s=1, f1=1, and execute step S22.

[0045] Step S22: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. s If so, TDR(s,f1) is set to the value of the current TDR, and step S23 is executed. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, TDR(s,f1) is set to empty, and step S24 is executed.

[0046] It should be noted that step S22 determines the situation where there is only one cable for allocation. The delay corresponding to the TDR value allocated to the signal must be less than or equal to the upper limit of the signal delay in order to successfully allocate. The smaller the TDR value, the smaller the delay. Therefore, when there is only one cable, the first available TDR value obtained in the order of TDR values ​​from small to large is the optimal TDR value.

[0047] Step S23, determine whether s is less than S, if so, set s=s+1, return to execute step S22, otherwise, execute step S24.

[0048] Step S24, determine whether f1 is less than F, if so, set s=1, f1=f1+1, and execute step S25, otherwise, execute step S3.

[0049] Step S25: Based on the preset time division multiplexing mapping table, determine whether the corresponding delay is less than or equal to D according to the order of TDR values ​​from small to large. s If so, determine whether TDR(s-TDR0,f1-1) is empty, TDR0 is the value of the currently determined TDR, if it is not empty, set TDR(s,f1) to the value of the currently determined TDR, and execute step S23, otherwise, set TDR(s,f1) to empty, and execute step S24.

[0050] It should be noted that step S25 obtains the TDR value of two or more cables. In this case, it is also necessary to satisfy that the number of allocated cables cannot exceed the current maximum number of cables. Therefore, it is necessary to simultaneously satisfy that TDR(s-TDR0, f1-1) is not empty, that is, s-TDR0 signals can be successfully allocated on f1-1 cables.

[0051] It should be noted that when there is only a forward signal between the first FPGA and the second FPGA, all possible TDR values ​​can be obtained through steps S21-S25. When there is a reverse signal between the first FPGA and the second FPGA, it is necessary to further perform step S3 to obtain all possible TDR values ​​corresponding to the reverse signal. When TDR (s, f1) does not have a TDR value that meets the conditions, the corresponding setting is empty.

[0052] As an embodiment, step S3 includes:

[0053] Step S31, set w=S+1, f2=2, and execute step S32.

[0054] It should be noted that the same cable can only transmit signals in one direction. Therefore, when there is a bidirectional signal between the first FPGA and the second FPGA, the forward signal needs to occupy at least one cable. Therefore, the value of f2 should start from 2.

[0055] Step S32: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w If so, TDR(w,f2) is set to the value of the current judgment TDR, and step S33 is executed. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, TDR(w,f2) is set to empty and step S34 is executed.

[0056] It should be noted that step S32 determines the situation where there is only one cable for allocation. The delay corresponding to the TDR value allocated to the signal must be less than or equal to the upper limit of the signal delay in order to successfully allocate. The smaller the TDR value, the smaller the delay. Therefore, when there is only one cable, the first available TDR value obtained in the order of TDR values ​​from small to large is the optimal TDR value.

[0057] Step S33, determine whether w is less than W, if so, set w=w+1, return to execute step S32, otherwise, execute step S34.

[0058] Step S34, determine whether f2 is less than F, if so, set w=S+1, f2=f2+1, and execute step S35, otherwise, execute step S4.

[0059] Step S35: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w If so, execute step S36, otherwise, execute step S34.

[0060] Step S36: Determine whether (w - TDR0) ≥ S + 1 is satisfied. If so, execute Step S37; otherwise, execute Step S38.

[0061] Step S37: Determine whether TDR(w - TDR0, f2 - 1) is empty. TDR0 is the value of the currently judged TDR. If it is not empty, set TDR(w, f2) to the value of the currently judged TDR, and execute Step S33; otherwise, set TDR(w, f2) to be empty and execute Step S34.

[0062] Step S38: Determine whether TDR(S, f2 - 1) is empty. If it is not empty, set TDR(w, f2) to the value of the currently judged TDR, and execute Step S33; otherwise, set TDR(w, f2) to be empty and execute Step S34.

[0063] It should be noted that if (w - TDR0) ≥ S + 1, it means that the (w - TDR0)th signal is also a reverse signal; otherwise, it is a forward signal. Since only one signal can be transmitted on the same cable, the forward signal and the reverse signal cannot be allocated on the same cable. Therefore, when (w - TDR0) < S + 1, the boundary value adjacent to the reverse signal, that is, the Sth signal, should be taken for judgment instead of the (w - TDR0)th signal. When there is no TDR value that meets the conditions in TDR(w, f2), it is correspondingly set to be empty.

[0064] As an embodiment, Step S4 includes:

[0065] Step S41: If TDR(W, F) is not empty, set the cable number XL to be allocated as F, and the termination number ZL of the signal to be allocated as W.

[0066] It should be noted that if TDR(W, F) is not empty, it means that the W signals between the first FPGA and the second FPGA can be allocated on F cables.

[0067] Step S42: Set the TDR value of the XLth cable between the first FPGA and the second FPGA to TDR(ZL, XL).

[0068] Among them, the optimal TDR value of the XLth cable between the first FPGA and the second FPGA is TDR(ZL, XL). Therefore, directly set the TDR value of the XLth cable between the first FPGA and the second FPGA to TDR(ZL, XL). It shows that at this time, the XLth cable can accommodate at most TDR(ZL, XL) signals.

[0069] Step S43: Determine whether ZL - TDR(ZL, XL) is greater than or equal to S. If so, execute Step S45; otherwise, execute Step S44.

[0070] It should be noted that when ZL-TDR(ZL,XL) is greater than or equal to S, it indicates that all the signals to be allocated at this time are reverse signals. Therefore, directly execute step S45. When ZL-TDR(ZL,XL) is less than S, it is possible that the starting signal to be allocated is a forward signal and the ending signal to be allocated is a reverse signal. However, since only signals in one direction can be allocated to the same cable, further judgment is required and step S44 is executed.

[0071] Step S44: If ZL > S, then execute step S46; otherwise, execute step S45.

[0072] It should be noted that when the situation of ZL > S and ZL-TDR(ZL,XL) < S occurs, it indicates that the starting signal to be allocated is a forward signal and the ending signal to be allocated is a reverse signal. Therefore, through step S46, the starting signal to be allocated is set to the (S + 1)-th signal to ensure that only signals in the same direction are allocated to the same cable.

[0073] Step S45: Set the starting signal number YL to be allocated as YL = ZL-TDR(ZL,XL) + 1, and allocate signals E YL to E ZL on the XL-th cable, and execute step S47.

[0074] Step S46: Set YL = S + 1, and allocate signals E YL to E ZL on the XL-th cable, and execute step S47.

[0075] Step S47: If YL - 1 = 1, then end the process; otherwise, set XL = XL - 1, ZL = YL - 1, and return to execute step S42.

[0076] It should be noted that through steps S41 - S47, the TDR values corresponding to all signals and the cable numbers to which they are allocated can be determined. It can be understood that in the embodiments of the present invention, the cables are numbered in the order of 1, 2, 3..., F. In addition, after the TDM allocation is completed, all the cables in the first FPGA and the second FPGA may be occupied, or there may be remaining unoccupied cables.

[0077] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but there can also be additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0078] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0079] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0080] The embodiment of the present invention can obtain the optimal TDM allocation result when the upper limit of the delay of all signals between two FPGAs and the number of cables between the two FPGAs are known, thereby improving the operation efficiency of the design.

[0081] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A signal TDM distribution method based on FPGA, characterized in that: include: Step S1: Obtain a signal set {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W }, where E s is the sth signal between the first FPGA and the second FPGA, the value range of s is 1 to S, and S is the number of positive signals between the first FPGA and the second FPGA; E w is the wth signal between the first FPGA and the second FPGA, the value range of w is S+1 to W, and W is the sum of the number of forward signals and reverse signals between the first FPGA and the second FPGA; E s The upper limit of the delay between the first FPGA and the second FPGA is D s , D1>D2,...,>D s ,...,>D S ; E w The upper limit of the delay between the first FPGA and the second FPGA is D w , D S+1 >D S+2 >,...,>D w ,...,>D W ; Step S2: Obtain E s The optimal TDR value TDR(s,f1) corresponding to the case where there are f1 cables and s signals between the first FPGA and the second FPGA, where the value range of f1 is 1 to F, and F is the total number of cables between the first FPGA and the second FPGA; Step S3, obtain E in sequence w The optimal TDR value TDR(w,f2) corresponding to the case where there are f2 cables and w signals between the first FPGA and the second FPGA, where the value range of f2 is 2 to F, and the same cable can only transmit signals in the same direction; Step S4: if TDR(W,F) exists, determine the signal TDM allocation between the first FPGA and the second FPGA based on all TDR(s,f1) and TDR(w,f2); The step S4 comprises: Step S41, if TDR (W, F) is not empty, set the cable number to be allocated XL = F, and the signal termination number to be allocated ZL = W; Step S42, setting the TDR value of the XLth cable between the first FPGA and the second FPGA to TDR (ZL, XL); Step S43, determine whether ZL-TDR (ZL, XL) is greater than or equal to S, if so, execute step S45, otherwise, execute step S44; Step S44: If ZL>S, execute step S46; otherwise, execute step S45; Step S45, set the starting signal number to be allocated YL = ZL-TDR (ZL, XL) + 1, and YL To E ZL Allocate to the XLth cable and execute step S47; Step S46, set YL=S+1, and convert signal E YL To E ZL Allocate to the XLth cable and execute step S47; Step S47: If YL-1=1, end the process; otherwise, set XL=XL-1, ZL=YL-1, and return to step S42.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11, obtaining initial winding information in the FPGA system; Step S12, generating a time margin for each signal based on the initial winding information; Step S13, obtaining a delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA, and determining the sum of the delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA and the time margin corresponding to the signal as the upper limit of the signal delay; Step S14: Sort the signals between the first FPGA and the second FPGA according to the direction of each signal passing between the first FPGA and the second FPGA and the upper limit of the delay of each signal, and generate {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W }.

3. The method according to claim 2, characterized in that The step S11 comprises: Step S111, obtaining the connection relationship between FPGAs in the FPGA system; Step S112: Determine the shortest path routing for each signal based on the connection relationship between the FPGAs; Step S113: Based on the shortest path routing of all signals, perform average TDM distribution on the signals between every two interconnected FPGAs, and generate the initial routing information in the FPGA system.

4. The method according to claim 1, characterized in that The step S2 comprises: Step S21, set s=1, f1=1, and execute step S22; Step S22: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. s If so, TDR(s,f1) is set to the value of the current judgment TDR, and step S23 is executed. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, TDR(s,f1) is set to empty, and step S24 is executed; Step S23, determine whether s is less than S, if so, set s=s+1, return to step S22, otherwise, execute step S24; Step S24, determine whether f1 is less than F, if so, set s=1, f1=f1+1, and execute step S25, otherwise, execute step S3; Step S25: Based on the preset time division multiplexing mapping table, determine whether the corresponding delay is less than or equal to D according to the order of TDR values ​​from small to large. s If so, determine whether TDR(s-TDR0,f1-1) is empty, TDR0 is the value of the currently determined TDR, if it is not empty, set TDR(s,f1) to the value of the currently determined TDR, and execute step S23, otherwise, set TDR(s,f1) to empty, and execute step S24.

5. The method according to claim 1 or 4, characterized in that: The step S3 comprises: Step S31, set w=S+1, f2=2, and execute step S32; Step S32: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w If so, TDR(w,f2) is set to the value of the current judgment TDR, and step S33 is executed. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, TDR(w,f2) is set to empty, and step S34 is executed; Step S33, determine whether w is less than W, if so, set w=w+1, return to step S32, otherwise, execute step S34; Step S34, determine whether f2 is less than F, if so, set w=S+1, f2=f2+1, and execute step S35, otherwise, execute step S4; Step S35: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w , if yes, execute step S36, otherwise, execute step S34; Step S36, determine whether (w-TDR0)≥S+1 is satisfied, if so, execute step S37, otherwise, execute step S38; Step S37, determine whether TDR (w-TDR0, f2-1) is empty, TDR0 is the value of the currently determined TDR, if it is not empty, set TDR (w, f2) to the value of the currently determined TDR, and execute step S33, otherwise, set TDR (w, f2) to empty, and execute step S34; Step S38, determine whether TDR (S, f2-1) is empty. If not, set TDR (w, f2) to the value of the current judgment TDR and execute step S33. Otherwise, set TDR (w, f2) to empty and execute step S34.

6. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-5.

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