Data access request sending method, device and equipment for multi-core processor

Abstract

The present disclosure proposes a data access request sending method, device and equipment for a multi-core processor. The method is executed by a master node of the multi-core processor, including: determining a first number of data access requests that a management queue of the master node can process at a first time, and when the first number is less than a first number threshold, or the first number is equal to a second number threshold, determining a target request node that sends a first data access request to a routing node of the multi-core processor after the first time, the first number threshold being the maximum number of data access requests that the master node can receive at the first time, and the second number threshold being zero, and sending a first signal to the target request node, so as to timely determine the timing when the management queue of the master node can no longer process data access requests, and avoid continuing to send data access requests to the target request node, causing the data access request to wait in the on-chip network and causing congestion of the on-chip network, thereby improving the performance of the multi-core processor.

Description

Technical Field

[0001] The present disclosure relates to the field of processor technology, and in particular to a method, device, electronic device and storage medium for sending a data access request for a multi-core processor. Background Art

[0002] The rapid development of semiconductor technology has made the speed and integration of microprocessors higher and higher. The number and types of transistor resources that processor designers can use to implement chips are constantly increasing. Single-chip multiprocessors (Chip Multiprocessors, CMP), also known as multi-core processors, have gradually become the mainstream of high-performance general-purpose processors. In CMP, the goal of the on-chip network data transmission strategy is to meet the processor core's needs for data access and cache coherence maintenance with high bandwidth at the cost of relatively low communication overhead, power consumption, response delay, etc., and reduce on-chip network congestion.

[0003] In the related art, data access requests that cannot be processed in time by the master node in the CMP will wait in the on-chip network, occupying the buffer resources of each routing node (Router) of the on-chip network, resulting in congestion of the on-chip network. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the purpose of the present disclosure is to propose a method, device, electronic device and storage medium for sending data access requests for a multi-core processor, so as to timely determine the time when the main node management queue cannot continue to process data access requests, thereby avoiding continuing to send data access requests to the target request node based on the first signal, causing congestion in the on-chip network caused by the data access requests waiting in the on-chip network, thereby improving the performance of the multi-core processor.

[0006] A method for sending data access requests for a multi-core processor proposed in an embodiment of the first aspect of the present disclosure is executed by a master node of the multi-core processor, and the method includes: determining a first number of data access requests that a management queue of the master node can process at a first time, and when the first number is less than a first number threshold, or the first number is equal to a second number threshold, determining a target request node that sends a first data access request to a routing node of the multi-core processor after the first time, the first number threshold being the maximum number of data access requests that the master node can receive at the first time, and the second number threshold being zero, and sending a first signal to the target request node, wherein the first signal is used to instruct the target request node to suspend sending the first data access request.

[0007] A method for sending a data access request for a multi-core processor proposed in an embodiment of the second aspect of the present disclosure is executed by a target request node of the multi-core processor. The method includes: receiving a first signal sent by a master node of the multi-core processor, and suspending sending a first data access request based on the first signal.

[0008] A data access request sending device for a multi-core processor proposed in an embodiment of the third aspect of the present disclosure is executed by a master node of the multi-core processor, and the device includes: a first determination module, used to determine a first number of data access requests that a management queue of the master node can process at a first time; a second determination module, used to determine a target request node that sends a first data access request to a routing node of the multi-core processor after a first time when the first number is less than a first number threshold, or the first number is equal to a second number threshold, wherein the first number threshold is the maximum number of data access requests that the master node can receive at the first time, and the second number threshold is zero; a sending module, used to send a first signal to the target request node, wherein the first signal is used to instruct the target request node to suspend sending the first data access request.

[0009] The data access request sending device for a multi-core processor proposed in the fourth aspect of the embodiment of the present disclosure is executed by the target request node of the multi-core processor. The device includes: a receiving module, which is used to receive a first signal sent by the master node of the multi-core processor and suspend sending a first data access request based on the first signal.

[0010] The fifth aspect embodiment of the present disclosure proposes an electronic device, including a memory, a storage device, and a computer program stored in the storage device and executable on the storage device. When the storage device executes the program, the data access request sending method for a multi-core processor proposed in the first aspect embodiment of the present disclosure is implemented, or the data access request sending method for a multi-core processor proposed in the second aspect embodiment of the present disclosure is implemented.

[0011] The sixth aspect embodiment of the present disclosure proposes a non-temporary computer-readable storage medium, on which a computer program is stored. When the program is executed by the memory, it implements the data access request sending method for a multi-core processor as proposed in the first aspect embodiment of the present disclosure, or implements the data access request sending method for a multi-core processor as proposed in the second aspect embodiment of the present disclosure.

[0012] The seventh aspect embodiment of the present disclosure proposes a computer program product. When the instruction memory in the computer program product is executed, it executes the data access request sending method for a multi-core processor proposed in the first aspect embodiment of the present disclosure, or implements the data access request sending method for a multi-core processor proposed in the second aspect embodiment of the present disclosure.

[0013] The data access request sending method, device, electronic device and storage medium for a multi-core processor provided by the present disclosure have at least the following beneficial effects: determining a first number of data access requests that a management queue of a master node can process at a first time, and when the first number is less than a first number threshold, or the first number is equal to a second number threshold, determining a target request node that sends a first data access request to a routing node of the multi-core processor after the first time, the first number threshold being the maximum number of data access requests that the master node can receive at the first time, the second number threshold being zero, and sending a first signal to the target request node, so as to timely determine the timing when the management queue of the master node cannot continue to process data access requests, so as to avoid, based on the first signal, continuing to send data access requests to the target request node, causing congestion of the on-chip network caused by the data access requests waiting in the on-chip network, thereby improving the performance of the multi-core processor.

[0014] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0016] Figure 1 It is a flowchart of a method for sending a data access request for a multi-core processor proposed in an embodiment of the present disclosure;

[0017] Figure 2 is a schematic diagram of the architecture of a multi-core processor proposed in an embodiment of the present disclosure;

[0018] Figure 3 is a flowchart of a method for sending a data access request for a multi-core processor proposed in another embodiment of the present disclosure;

[0019] Figure 4 is a flowchart of a method for sending a data access request for a multi-core processor proposed in another embodiment of the present disclosure;

[0020] Figure 5 It is a structural diagram of a data access request sending device for a multi-core processor proposed in an embodiment of the present disclosure;

[0021] Figure 6 It is a structural diagram of a data access request sending device for a multi-core processor proposed in an embodiment of the present disclosure;

[0022] Figure 7 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present disclosure, and are not to be construed as limitations of the present disclosure. On the contrary, the embodiments of the present disclosure include all changes, modifications, and equivalents that fall within the spirit and connotation of the appended claims.

[0024] Figure 1 It is a flowchart of a method for sending a data access request for a multi-core processor proposed in an embodiment of the present disclosure.

[0025] It should be noted that the executor of the data access request sending method for a multi-core processor in this embodiment is a data access request sending device for a multi-core processor, which can be implemented by software and / or hardware, and can be configured in an electronic device, which may include but is not limited to a terminal, a server, etc.

[0026] like Figure 1 As shown, the data access request sending method for a multi-core processor includes:

[0027] S101: Determine a first number of data access requests that a management queue of a master node can process at a first time.

[0028] The data access request sending method for a multi-core processor described in the embodiment of the present disclosure is executed by a master node of the multi-core processor.

[0029] Among them, multi-core processors are also called chip multiprocessors (CMP). The number of processor cores integrated on the chip reaches 32 cores, 64 cores, 128 cores, or even more cores. The cores are interconnected using an on-chip network (Network on Chip, NoC). Considering the scalability, the on-chip network of multi-core processors mostly adopts a Mesh (mesh) topology, or a topology such as Torus (3D cube) expanded from the Mesh.

[0030] Among them, under the multi-level cache hierarchy and on-chip network architecture, the system-level cache is shared by all processor cores, uniformly addressed, and cache consistency is maintained between multiple cores in the multi-core processor chip. In the case of shared last-level cache, each cache block has a fixed master node (Home node) as a level for consistency maintenance. The memory address distribution is consistent with the address distribution of the last-level cache. Each Home node maintains a directory to record which processor cores' cache nodes each cache block in the processor core has, as well as the status in the processor core cache.

[0031] In the embodiments of the present disclosure, see Figure 2 , Figure 2 It is an architectural diagram of a multi-core processor proposed in an embodiment of the present disclosure. The processor core includes a processor core execution unit and a multi-level cache hierarchy. The on-chip network routing node is responsible for transmitting requests from the processor core to the Home node. The Home node includes a management queue, a record queue, a threshold judgment unit, a system-level cache (System Cache) and a directory (Directory).

[0032] Each Home node has a management queue (Manage Queue) to uniformly process the access requests to the system-level cache sent by the processing core to the corresponding Home node and the consistency requests sent to the directory, and return data. The management queue is the control core between the processor core (CPU Core), directory (Directory), system-level cache (System Cache) and memory controller (Memory Controller). The management queue is responsible for receiving and sending cache miss access requests from the processor core to the directory and system-level cache, sending system-level cache miss access memory requests to the memory controller, returning failed access responses to the processor core, sending consistency maintenance-related operations to the processor core, receiving responses from the processor core, receiving responses from the memory controller, etc.

[0033] The first time may be the current time, and there is no limitation on this.

[0034] Among them, the data access request can be, for example, information sent directly by a processor core related to the main node to the main node for requesting access to the main node data, or it can be information sent by other processor cores to the main node via a request node related to the main node for requesting access to the main node data, and there is no restriction on this.

[0035] Among them, the management queue of the master node has a corresponding first number threshold of data access requests when processing data access requests. Therefore, the first number of data access requests that the management queue can process at the first time can be the difference between the processing data threshold and the number of data access requests that the management queue is processing at the first time.

[0036] That is to say, in the embodiment of the present disclosure, determining the first number of data access requests that the management queue of the master node can process at the first time can be by determining a first number threshold of data access requests corresponding to the management queue, and determining the number of data access requests that the management queue is processing at the first time, and then taking the difference between the first number threshold and the number of data access requests that the management queue is processing at the first time as the first number.

[0037] S102: When the first number is less than a first number threshold, or the first number is equal to a second number threshold, determine a target request node that sends a first data access request to a routing node of the multi-core processor after a first time.

[0038] The first quantity threshold is the maximum number of data access requests that the master node can receive at the first time, or the second quantity threshold refers to the management queue being full, that is, the second quantity threshold is zero.

[0039] It is understandable that when the number of data access requests being processed in the management queue is less than the first number threshold, or the first number is equal to the second number threshold, the Home node will no longer be able to continue to receive data access requests from the on-chip network, so that the data access request sent by the requesting node will wait in the on-chip network because the Home node cannot receive it, occupying the buffer resources of each routing node (Router) in the on-chip network, and causing the on-chip network to be blocked.

[0040] The first data access request refers to a data access request to be sent by a requesting node that communicates with the master node after the first time.

[0041] Therefore, the embodiment of the present disclosure is precisely to solve the above-mentioned technical problems, thereby determining the first number of data access requests that the management queue of the master node can process at the first time, and then combining the first number threshold and the second number threshold to promptly determine the time when the management queue can no longer continue to process data access requests, thereby taking corresponding measures to avoid the occurrence of the above-mentioned problems.

[0042] Optionally, in some embodiments, the first quantity threshold is determined based on: determining a third number of initial request nodes communicating with the master node; determining a fourth number of data access requests that each initial request node can send in parallel, and determining a fifth number of data access requests that local processor cores associated with the master node can send in parallel, determining the product between the third number and the fourth number; and taking the sum of the product and the fifth number as the first quantity threshold.

[0043] That is to say, in the embodiments of the present disclosure, see the above Figure 2 , the requests of the multi-core processor Home node will come from the third number (four directions of east, west, south and north) of the initial request nodes, plus the direction of the local processor core. Assuming that the third number (4) of initial request nodes can send a maximum of a fourth number (M) of data access requests in parallel in each direction, and the local processor core can issue a maximum of a fifth number (N) of requests in parallel, it can be determined that the first number threshold of the management queue is 4*M+N.

[0044] For example, when the four directions of east, west, south, and north and the local processor core can only send one request in parallel at most, the first quantity threshold of the management queue is 5. When the four directions of east, west, south, and north can only send one request in parallel at most, and the local processor core can issue multiple requests to access the Home node in parallel, the threshold of the management queue is set to the maximum number of requests from the four directions of east, west, south, and north plus the local maximum number of requests to access the Home node in parallel. For example, the four directions of east, west, south, and north can only send one data access request to access the Home node, and the local processor core can issue at most 2 data access requests to access the Home node in parallel. The first quantity threshold of the management queue is 4+2=6, and there is no limit on this.

[0045] Optionally, in some embodiments, the threshold of the second quantity is determined based on the following method: if the management queue of the Home node is full, when all items in the management queue are occupied and there are no available empty items, it is determined that the first number of data access requests that the management queue of the main node can process at the first time is equal to 0, that is, the second quantity threshold is set to 0.

[0046] It should be noted that the above method of determining the quantity threshold is only an example, and the quantity threshold of the management queue can also be dynamically adjusted according to the analysis of the congestion situation of the on-chip network, and there is no limitation on this.

[0047] Optionally, in some embodiments, when the first number is less than a first number threshold, or the first number is equal to a second number threshold, the node identification information and request priority corresponding to each first data access request are obtained, and then the node identification information and request priority are stored in the record queue of the master node.

[0048] Among them, the request priority corresponding to the first data access request refers to the request priority of the processor core corresponding to the first data access request. The priorities can be divided into different levels, such as 4 levels, and different priorities can be assigned to different request requirements or service qualities (QoS) of the corresponding processor cores. Alternatively, the request priority corresponding to each first data access request can also be determined based on information such as the delay or bandwidth required by the processor core corresponding to the first data access request, and there is no restriction on this.

[0049] In the disclosed embodiment, the node identification information corresponding to the first data access request may be, for example, the number of the target request node to which the first data access request is directly sent, or may be, for example, the number of the processor core corresponding to the first data access request. The number of digits of the processor core number is determined according to the number of processor cores. For example, if the number of processor cores is 128, the processor core number is 7 digits; if the number of processor cores is 256, the processor core number is 8 digits. There is no limitation on this.

[0050] The number of items in the record queue may be set to the sum of the maximum number of requests that can be issued by all processor cores, thereby ensuring that the record queue will not be full.

[0051] Optionally, in some embodiments, when the first number is less than a first number threshold, or the first number is equal to a second number threshold, determining the target request node that sends the first data access request to the routing node of the on-chip network after the first time may be, when the first number is less than the first number threshold, or the first number is equal to the second number threshold, determining the node identification information from the record queue, and then determining the target request node from multiple initial request nodes of the multi-core processor based on the node identification information.

[0052] That is to say, in the embodiment of the present disclosure, when the first number is less than the first number threshold, or the first number is equal to the second number threshold, the node identification information can be determined from the record queue, and then the initial request node corresponding to the node identification information can be used as the target node.

[0053] S103: Send a first signal to the target requesting node.

[0054] In an embodiment of the present disclosure, when the first number is less than a first number threshold, or the first number is equal to a second number threshold, after determining the target request node for sending a first data access request to a routing node of a multi-core processor after a first time, a first signal can be sent to the target request node, thereby avoiding, based on the first signal, continuing to send data access requests to the target request node, causing congestion in the on-chip network caused by the data access requests waiting in the on-chip network, thereby effectively improving the performance of the multi-core processor.

[0055] In this embodiment, by determining a first number of data access requests that the management queue of the master node can process at the first time, when the first number is less than a first number threshold, or the first number is equal to a second number threshold, a target request node that sends a first data access request to the routing node of the multi-core processor after the first time is determined, and then a first signal is sent to the target request node, wherein the first number threshold is the maximum number of data access requests that the master node can receive at the first time, thereby timely determining the timing when the management queue of the master node cannot continue to process the data access request, thereby avoiding, based on the first signal, continuing to send data access requests to the target request node, causing the data access request to wait in the on-chip network and causing congestion in the on-chip network, thereby improving the performance of the multi-core processor.

[0056] Figure 3 It is a flowchart of a method for sending a data access request for a multi-core processor proposed in another embodiment of the present disclosure.

[0057] like Figure 3 As shown, the data access request sending method for a multi-core processor includes:

[0058] S301: Determine a first number of data access requests that a management queue of a master node can process at a first time.

[0059] S302: When the first number is less than a first number threshold, or the first number is equal to a second number threshold, determine a target request node that sends a first data access request to a routing node of the multi-core processor after a first time.

[0060] The specific description of S301 - S302 can be found in the above embodiment, which will not be repeated here.

[0061] S303: When the first number is greater than or equal to a first number threshold, send a third signal to the initial requesting node, wherein the third signal is used to instruct the initial requesting node to continue sending a second data access request to the master node.

[0062] The second data access request is a data access request that the initial requesting node continues to send to the master node when the first quantity is greater than or equal to the first quantity threshold, and the first data access request and the second data access request are different.

[0063] That is to say, in the embodiments of the present disclosure, when it is determined that the first number is greater than or equal to the first number threshold, it is determined that the number of data access requests that the management queue can currently process has not reached the first number threshold, that is, the management queue can continue to process the data access request at this time. Therefore, the target node can send a third signal to the initial request node to instruct the initial request node to continue to send the second data access request to the master node, thereby avoiding wasting resources of the management queue and not delaying the processing timing of the data access request.

[0064] S304: Determine a second number of data access requests that the management queue can process at a second time.

[0065] Among them, the second time is after the first time.

[0066] That is to say, in the embodiment of the present disclosure, determining the second number of data access requests that the management queue of the master node can process at the second time may be by determining a second number threshold of data access requests corresponding to the management queue, and determining the number of data access requests being processed by the management queue at the second time, and then using the difference between the second number threshold and the number of data access requests being processed by the management queue at the second time as the second number.

[0067] S305: When the second number is greater than or equal to the first number threshold, send a second signal to the target requesting node, wherein the second signal is used to instruct the target requesting node to resend the first data access request to the master node.

[0068] When determining that the second number is greater than or equal to the first number threshold, the disclosed embodiment can determine that the number of data access requests that the management queue can process at the second time reaches the first number threshold, that is, the management queue can continue to process the data access requests at this time. As a result, the master node can send a second signal to the target request node at the second time to instruct the second signal to resend the first data access request to the master node, thereby avoiding on-chip network congestion at the first time and promoting the target request node to resend the first data access request at the second time, thereby avoiding omission of data access requests, thereby effectively ensuring the data access effect of the processor core.

[0069] Optionally, in some embodiments, sending the second signal to the target request node may be performed by sorting multiple request priorities in the record queue from low to high to obtain a sorting result, and then sending the second signal to the multiple target request nodes in turn according to the sorting result.

[0070] That is to say, in the embodiment of the present disclosure, when the second number is greater than or equal to the first number threshold, multiple request priorities in the record queue may be sorted from low to high to obtain a sorting result, and then the second signal may be sent to the target request node corresponding to the request priority with a higher priority according to the sorting result.

[0071] In the disclosed embodiment, after sending the second signal to the target request node, an item may be reserved in the management queue for the local processor core associated with the master node to ensure that the first data access request resent by the local processor core can be processed by the management queue.

[0072] In the embodiment of the present disclosure, by determining the first number of data access requests that the management queue of the master node can process at the first time, and then determining the target request node that sends the first data access request to the routing node of the multi-core processor after the first time when the first number is less than the first number threshold or the first number is equal to the second number threshold, and then sending a third signal to the initial request node when the first number is greater than or equal to the first number threshold, the target node can send the third signal to the initial request node to instruct the initial request node to continue to send the second data access request to the master node, thereby avoiding waste of resources of the management queue and not delaying the processing timing of the data access request, and then determining the second number of data access requests that the management queue can process at the second time, and then sending a second signal to the target request node when the second number is greater than or equal to the first number threshold, thereby avoiding, based on the first signal, continuing to send data access requests to the target request node, causing the data access request to wait in the on-chip network and causing congestion in the on-chip network, and at the same time, promoting the target request node to resend the first data access request at the second time, thereby avoiding omission of the data access request, thereby effectively ensuring the data access effect of the processor core.

[0073] Figure 4 It is a flowchart of a method for sending a data access request for a multi-core processor proposed in an embodiment of the present disclosure.

[0074] It should be noted that the executor of the data access request sending method for a multi-core processor in this embodiment is a data access request sending device for a multi-core processor, which can be implemented by software and / or hardware, and can be configured in an electronic device, which may include but is not limited to a terminal, a server, etc.

[0075] like Figure 4 As shown, the data access request sending method for a multi-core processor includes:

[0076] S401: Receive a first signal sent by a master node of a multi-core processor.

[0077] In the embodiments of the present disclosure, the explanations of the same terms in the above embodiments can be found in the above embodiments and will not be repeated here.

[0078] In the embodiment of the present disclosure, the target request node may receive a first signal sent by a master node of the multi-core processor.

[0079] S402: According to the first signal, suspend sending the first data access request.

[0080] In the disclosed embodiment, after receiving the first signal, the target request node may suspend sending the first data access request to the master node, thereby preventing the data access request from being processed in a timely manner, causing the data access request to wait in the on-chip network and cause congestion in the on-chip network, and the target request node will send an indication message to the processor core corresponding to the first data access request, and the indication message is used to instruct the processor core to retain the request and wait for future retransmission.

[0081] Optionally, in some embodiments, the target requesting node may also receive a second signal sent by the master node, and then resend the first data access request to the master node based on the second signal.

[0082] Specifically, after receiving the second signal, the target request node can determine that the master node management queue can continue to process the data access request at this time, so the target request node can resend the first data access request to the master node.

[0083] In the disclosed embodiment, the target request node of the multi-core processor receives the first signal sent by the master node of the multi-core processor, and can suspend sending the first data access request to the target request node based on the first signal, thereby avoiding the data access request from being processed in time, causing the data access request to wait in the on-chip network and causing congestion in the on-chip network, thereby improving the overall performance of the multi-core processor.

[0084] Figure 5 It is a structural diagram of a data access request sending device for a multi-core processor proposed in an embodiment of the present disclosure.

[0085] like Figure 5 As shown, the data access request sending device 50 for a multi-core processor is characterized in that it is executed by a master node of the multi-core processor, and the device includes:

[0086] A first determination module 501, configured to determine a first number of data access requests that a management queue of a master node can process at a first time;

[0087] A second determination module 502 is used to determine a target request node that sends a first data access request to a routing node of the multi-core processor after a first time when the first number is less than a first number threshold or the first number is equal to a second number threshold, wherein the first number threshold is a maximum number of data access requests that the master node can receive at the first time, and the second number threshold is zero;

[0088] The sending module 503 is used to send a first signal to the target requesting node, wherein the first signal is used to instruct the target requesting node to suspend sending the first data access request.

[0089] In some embodiments of the present disclosure, the data access request sending device 50 for a multi-core processor further includes:

[0090] an acquisition module, configured to acquire node identification information and a request priority corresponding to each first data access request when the first number is less than a first number threshold or the first number is equal to a second number threshold;

[0091] The storage module is used to store the node identification information and the request priority in the record queue of the master node.

[0092] In some embodiments of the present disclosure, the second determining module 502 is further configured to:

[0093] When the first number is less than the first number threshold, or the first number is equal to the second number threshold, determining the node identification information from the record queue;

[0094] A target requesting node is determined from a plurality of initial requesting nodes of the multi-core processor according to the node identification information.

[0095] In some embodiments of the present disclosure, the data access request sending device 50 for a multi-core processor further includes:

[0096] A third determination module, configured to determine a second number of data access requests that the management queue can process at a second time, wherein the second time is after the first time;

[0097] The first sending module is used to send a second signal to the target request node when the second number is greater than or equal to the first number threshold, wherein the second signal is used to instruct the target request node to re-send the first data access request to the main node.

[0098] In some embodiments of the present disclosure, the first sending module is further configured to:

[0099] Sort multiple request priorities in the record queue from low to high to obtain a sorting result;

[0100] The second signal is sent to the multiple target request nodes in sequence according to the sorting result.

[0101] In some embodiments of the present disclosure, the first quantity threshold is determined based on the following method:

[0102] determining a third number of initial requesting nodes in communication with the master node;

[0103] Determining a fourth number of data access requests that each initial requesting node can send in parallel, and determining a fifth number of data access requests that a local processor core associated with the master node can send in parallel;

[0104] determining a product between the third quantity and the fourth quantity;

[0105] A sum value between the product and the fifth quantity is used as the first quantity threshold.

[0106] In some embodiments of the present disclosure, the data access request sending device 50 for a multi-core processor further includes:

[0107] The second sending module is used to send a third signal to the initial requesting node when the first number is greater than or equal to the first number threshold, wherein the third signal is used to instruct the initial requesting node to continue sending the second data access request to the master node.

[0108] With the above Figures 1 to 3 Corresponding to the method for sending data access request for a multi-core processor provided in the embodiment, the present disclosure also provides a device for sending data access request for a multi-core processor. Figures 1 to 3 The data access request sending method for a multi-core processor provided in the embodiment corresponds to the method, so the implementation of the data access request sending method for a multi-core processor is also applicable to the data access request sending device for a multi-core processor provided in the embodiment of the present disclosure, and will not be described in detail in the embodiment of the present disclosure.

[0109] In this embodiment, the master node of the multi-core processor determines a target request node to send a first data access request to the routing node of the multi-core processor after the first time by determining a first number of data access requests that the management queue of the master node can process at a first time, and when the first number is less than a first number threshold, or the first number is equal to a second number threshold, the first number threshold is the maximum number of data access requests that the master node can receive at the first time, and the second number threshold is zero, and a first signal is sent to the target request node, so as to timely determine the timing when the management queue of the master node can no longer process data access requests, thereby avoiding continued sending of data access requests to the target request node, causing congestion in the on-chip network due to the data access requests waiting in the on-chip network, thereby improving the performance of the multi-core processor.

[0110] Figure 6 It is a structural diagram of a data access request sending device for a multi-core processor proposed in an embodiment of the present disclosure.

[0111] like Figure 6 As shown, the data access request sending device 60 for a multi-core processor is executed by a target request node of the multi-core processor, and the device includes:

[0112] The receiving module 601 is used to receive a first signal sent by the master node of the multi-core processor, and suspend sending the first data access request according to the first signal.

[0113] In some embodiments of the present disclosure, the receiving module 601 is further configured to:

[0114] receiving a second signal sent by the master node;

[0115] According to the second signal, the first data access request is resent to the master node.

[0116] With the above Figure 4 Corresponding to the method for sending data access request for a multi-core processor provided in the embodiment, the present disclosure also provides a device for sending data access request for a multi-core processor. Figure 4 The data access request sending method for a multi-core processor provided in the embodiment corresponds to the method, so the implementation of the data access request sending method for a multi-core processor is also applicable to the data access request sending device for a multi-core processor provided in the embodiment of the present disclosure, and will not be described in detail in the embodiment of the present disclosure.

[0117] In the disclosed embodiment, the target request node of the multi-core processor receives the first signal sent by the master node of the multi-core processor, and can suspend sending the first data access request to the target request node based on the first signal, thereby avoiding the data access request from being processed in time, causing the data access request to wait in the on-chip network and causing congestion in the on-chip network, thereby improving the overall performance of the multi-core processor.

[0118] In order to implement the above embodiments, the present disclosure also proposes an electronic device, including: a memory, a storage, and a computer program stored in the storage and executable on the storage. When the storage executes the program, the data access request sending method for a multi-core processor proposed in the above embodiments of the present disclosure is implemented.

[0119] In order to implement the above embodiments, the present disclosure also proposes a non-temporary computer-readable storage medium on which a computer program is stored. When the program is executed by the memory, the method for sending data access requests for a multi-core processor proposed in the above embodiments of the present disclosure is implemented.

[0120] In order to implement the above embodiments, the present disclosure further proposes a computer program product. When the instruction memory in the computer program product is executed, the method for sending data access requests for a multi-core processor proposed in the above embodiments of the present disclosure is executed.

[0121] Figure 7 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Figure 7 The electronic device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0122] like Figure 7 As shown, the electronic device 12 is in the form of a general purpose computing device. Components of the electronic device 12 may include, but are not limited to: one or more memories or processing units 16, a system memory 28, and a bus 18 that connects various system components (including the system memory 28 and the processing unit 16).

[0123] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a memory or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

[0124] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0125] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Figure 7 Not shown, often called a "hard drive").

[0126] although Figure 7 Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a compact disc read only memory (hereinafter referred to as: CD-ROM), a digital versatile disc read only memory (hereinafter referred to as: DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0127] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0128] The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 12, and / or communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 22. In addition, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 through a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0129] The processing unit 16 executes various functional applications and data processing by running the programs stored in the system memory 28, such as implementing the data access request sending method for a multi-core processor mentioned in the above embodiment.

[0130] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0131] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0132] It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

[0133] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0134] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0135] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0136] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0137] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0138] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0139] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A method for sending a data access request for a multi-core processor, characterized in that: The method is executed by a master node of a multi-core processor, and includes: Determining a first number of data access requests that a management queue of the master node can process at a first time; When the first number is less than a first number threshold, or the first number is equal to a second number threshold, determining a target requesting node that sends a first data access request to a routing node of the multi-core processor after the first time, wherein the second number threshold is zero; Sending a first signal to the target requesting node, wherein the first signal is used to instruct the target requesting node to suspend sending the first data access request; Wherein, the method further comprises: determining a third number of initial requesting nodes in communication with the master node; Determine a fourth number of data access requests that each of the initial requesting nodes can send in parallel, and determine a fifth number of data access requests that a local processor core associated with the master node can send in parallel; determining a product between the third amount and the fourth amount; The sum of the product and the fifth quantity is taken as the first quantity threshold.

2. The method according to claim 1, characterized in that The method further comprises: When the first number is less than the first number threshold, or the first number is equal to the second number threshold, acquiring node identification information and request priority corresponding to each of the first data access requests; The node identification information and the request priority are stored in a record queue of the master node.

3. The method according to claim 2, characterized in that The step of determining a target requesting node that sends a first data access request to a routing node of the multi-core processor after the first time when the first number is less than a first number threshold or the first number is equal to a second number threshold comprises: When the first number is less than the first number threshold, or the first number is equal to the second number threshold, determining the node identification information from the record queue; The target requesting node is determined from a plurality of initial requesting nodes of the multi-core processor according to the node identification information.

4. The method according to claim 2 or 3, characterized in that The method further comprises: determining a second number of data access requests that the management queue can process at a second time, wherein the second time is after the first time; In a case where the second number is greater than or equal to the first number threshold, a second signal is sent to the target requesting node, wherein the second signal is used to instruct the target requesting node to resend the first data access request to the master node.

5. The method according to claim 4, characterized in that The sending a second signal to the target requesting node comprises: Sorting the plurality of request priorities in the record queue from low to high to obtain a sorting result; The second signal is sent to the plurality of target request nodes in sequence according to the sorting result.

6. The method according to claim 1, characterized in that The method further comprises: In a case where the first number is greater than or equal to the first number threshold, a third signal is sent to the initial requesting node, wherein the third signal is used to instruct the initial requesting node to continue sending a second data access request to the master node.

7. A method for sending a data access request for a multi-core processor, characterized in that: The method is performed by a target requesting node of a multi-core processor, wherein the target requesting node is a requesting node that sends a first data access request to a routing node of the multi-core processor after a first time, and the method comprises: Receiving a first signal sent by a master node of the multi-core processor; According to the first signal, suspend sending the first data access request; Among them, the first number of data access requests that the management queue of the master node can process at the first time is less than a first number threshold, or the first number is equal to zero, and the first number threshold is determined by: determining the third number of initial request nodes communicating with the master node; determining the fourth number of data access requests that each of the initial request nodes can send in parallel, and determining the fifth number of data access requests that the local processor cores associated with the master node can send in parallel; determining the product between the third number and the fourth number; and taking the sum of the product and the fifth number as the first number threshold.

8. The method according to claim 7, characterized in that The method further comprises: receiving a second signal sent by the master node; Resend the first data access request to the master node according to the second signal.

9. A data access request sending device for a multi-core processor, characterized in that: The device is executed by a master node of a multi-core processor, and the device comprises: A first determining module, configured to determine a first number of data access requests that the management queue of the master node can process at a first time; A second determination module is used to determine a target requesting node that sends a first data access request to a routing node of the multi-core processor after the first time when the first number is less than a first number threshold or the first number is equal to a second number threshold, wherein the second number threshold is zero; A sending module, configured to send a first signal to the target requesting node, wherein the first signal is used to instruct the target requesting node to suspend sending the first data access request; Wherein, the device is also used for: determining a third number of initial requesting nodes in communication with the master node; Determine a fourth number of data access requests that each of the initial requesting nodes can send in parallel, and determine a fifth number of data access requests that a local processor core associated with the master node can send in parallel; determining a product between the third amount and the fourth amount; The sum of the product and the fifth quantity is taken as the first quantity threshold.

10. A data access request sending device for a multi-core processor, characterized in that: The method is executed by a target requesting node of a multi-core processor, wherein the target requesting node sends a requesting node of a first data access request to a routing node of the multi-core processor after a first time, and the apparatus comprises: A receiving module, configured to receive a first signal sent by a master node of the multi-core processor, and suspend sending the first data access request according to the first signal; Among them, the first number of data access requests that the management queue of the master node can process at the first time is less than a first number threshold, or the first number is equal to zero, and the first number threshold is determined by: determining the third number of initial request nodes communicating with the master node; determining the fourth number of data access requests that each of the initial request nodes can send in parallel, and determining the fifth number of data access requests that the local processor cores associated with the master node can send in parallel; determining the product between the third number and the fourth number; and taking the sum of the product and the fifth number as the first number threshold.

11. An electronic device, comprising: at least one memory; as well as a memory communicatively connected to the at least one memory; wherein, The memory stores instructions that can be executed by the at least one memory, and the instructions are executed by the at least one memory so that the at least one memory can perform the method according to any one of claims 1 to 8.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

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