Method, device and storage medium for simulation logic system design

Abstract

The present application provides a method for simulating a logic system design. The method comprises: determining a plurality of basic logic units of the logic system design according to a description of the logic system design; merging the plurality of basic logic units into a plurality of task nodes, each of the plurality of task nodes comprising one or more sub-nodes; determining a simulation arrangement of the plurality of task nodes in an event-driven simulation manner, the plurality of task nodes comprising a first task node; and simulating one or more sub-nodes of the first task node in a clock cycle-based simulation manner in response to arranging the simulation of the first task node.

Description

Technical Field

[0001] The present application relates to the field of computer software technology, and in particular to a method, device and storage medium for simulating logic system design. Background Art

[0002] In the field of integrated circuit verification, simulation can refer to compiling a logical system design and then running it using simulation tools to simulate and test various functions of the design. The design can be, for example, an application-specific integrated circuit (ASIC) or a system-on-chip (SOC). Therefore, the design tested or verified in simulation can also be called the design under test (DUT). Summary of the invention

[0003] A first aspect of the present application provides a method for simulating a logic system design, the method comprising: determining a plurality of basic logic units of the logic system design according to a description of the logic system design; merging the plurality of basic logic units into a plurality of task nodes, each of the plurality of task nodes comprising one or more sub-nodes; determining a simulation schedule of the plurality of task nodes in an event-driven simulation manner, the plurality of task nodes comprising a first task node; and simulating one or more sub-nodes of the first task node in a clock cycle-based simulation manner in response to arranging the simulation of the first task node.

[0004] A second aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method as described in the first aspect.

[0005] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and when the set of instructions is executed, causes the computer to perform the method as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1A schematic structural diagram of an exemplary electronic device according to an embodiment of the present application is shown.

[0008] Figure 2 A schematic diagram of an exemplary simulation system according to an embodiment of the present application is shown.

[0009] Figure 3 A schematic diagram of an exemplary compiler according to an embodiment of the present application is shown.

[0010] Figure 4 A schematic diagram of a task node according to an embodiment of the present application is shown.

[0011] Figure 5 A schematic diagram showing the structure of a logic system design including multiple task nodes according to an embodiment of the present application

[0012] Figure 6 A schematic diagram showing the arrangement of multiple task nodes for simulation according to an embodiment of the present application is shown.

[0013] Figure 7 A schematic diagram showing another arrangement of simulating multiple task nodes according to an embodiment of the present application

[0014] Figure 8 A flow chart of a method for simulating logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0016] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0017] Figure 1 FIG. 1 is a schematic diagram showing the structure of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may be an electronic device for running a simulation system. Figure 1As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in the electronic device.

[0018] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0019] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method of emulation logic system design of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0020] The network interface 106 can be configured to provide the electronic device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0021] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0022] The bus 110 may be configured to transmit information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0023] It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above electronic device architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0024] Figure 2 FIG. 2 is a schematic diagram of an exemplary simulation tool 200 according to an embodiment of the present disclosure. The simulation tool 200 may be a computer program running on the electronic device 100 .

[0025] In the field of chip design, a design can usually be simulated using a simulation tool, such as the GalaxSim simulation tool produced by Xinhuazhang Technology Co., Ltd. Figure 2 The exemplary simulation tool 200 shown may include a compiler 210 and a simulator 220. The compiler 210 may receive source code 204 (e.g., a hardware description language such as VHDL, Verilog, SystemVerilog, etc.) and compile it into an executable code 206 (e.g., machine code, assembly code, software code, etc.). It is understood that the description of the logic system design may be described in a hardware description language (HDL), a register transfer level (RTL) language, binary code, assembly code, or machine code, etc. The simulator 220 may perform simulation according to the executable code 206 and output the simulation result 208. For example, the simulation tool 200 may output the simulation result 208 via Figure 1 The peripheral interface 108 outputs the data to an output device (for example, displayed on a display). The logic system design may be a chip design.

[0026] Figure 3FIG. 2 is a schematic diagram of an exemplary compiler 210 according to an embodiment of the present application. Figure 3 As shown, compiler 210 may include a front end 212 , a middle end 214 , and a back end 216 .

[0027] The front end 212 may be used to analyze the lexical, grammatical, and semantic aspects of the source code according to a specific source language.

[0028] After the lexical, grammatical and semantic analysis of the source code is completed, the middle end 214 can convert the source code into an intermediate representation (or intermediate code) and can optimize the intermediate representation. The intermediate language (intermediate code) is a syntax-oriented, equivalent internal representation code of the source code that is easy to translate into the target program. Its comprehensibility and the degree of easy generation of execution code are between the source code and the execution code. Commonly used intermediate codes include reverse Polish notation, quadruple, ternary and tree representation. For example, the middle end 214 can remove useless code, remove inaccessible code, clear unused variables, etc. Optimization can include machine-related optimization and machine-independent optimization. Among them, machine-related optimization, for example, can be the optimization of the test platform (Testbench, TB), and some test platform characteristics can be used to help optimize. Machine-independent optimization, for example, can be the optimization of the design under test (Design Under Test, DUT). The optimized intermediate representation can be passed to the back end 126 for further processing.

[0029] The back end 216 can be configured based on the target processor (e.g., Figure 1 The intermediate representation is further optimized according to the architecture of the processor 102, and an execution code is generated. Usually, the execution code is a machine code.

[0030] It is understood that the structure of the compiler is not limited to Figure 3 For example, front end 212 and middle end 214 may be collectively referred to as a front end of a compiler.

[0031] The compiler 210 can generate an execution code based on the computer code to be compiled. The computer code to be compiled can also be called source code, such as a written logic system design. Usually, the source language for writing the source code is a high-level programming language. The high-level programming language can be the above-mentioned software programming language or hardware programming language. The execution code can be, for example, assembly code, machine code, etc. Usually, the compiler 210 can be stored in Figure 1 The compiler 210 is stored in the memory 104 shown in the figure and is executed by the processor 102 to compile the logic system design into execution code. The compiler 210 can convert the description of the logic system design from a high-level language description (e.g., HDL language) into a lower-level description (e.g., RTL language or binary code) so that the underlying hardware can run the logic system design.

[0032] There are two general types of digital simulation for logic system design: event-driven simulation and cycle-based simulation. Event-driven simulation performs calculations for each event (e.g., the rising edge of a signal) and uses the calculation results as the input for the next state. Cycle-based simulation only calculates the values ​​of the signals of the simulated module at the beginning and end of each clock cycle, while ignoring the processes occurring within the clock cycle.

[0033] Therefore, when a module has frequent events, event-driven simulation is not as efficient as clock-cycle-based simulation. When a module has few events, clock-cycle-based simulation is not as efficient as event-driven simulation.

[0034] At the same time, since event-driven simulation needs to consider the dependencies between signals, its parallelism is poor. On the contrary, clock cycle-based simulation has good parallelism and can usually simulate the target design in parallel.

[0035] As the logic system design becomes increasingly large, the time required for simple event-driven simulation has increased dramatically to an unbearable level. However, clock cycle-based simulation lacks universality. For circuit simulations with fewer activation signals, many unnecessary calculations will be performed, resulting in poor stability, and the current simulation performance has reached a bottleneck.

[0036] How to fully utilize the advantages of event-driven simulation and clock cycle-based simulation to accelerate the simulation of logic system design is a technical problem that needs to be solved urgently.

[0037] Figure 4 A schematic diagram of a task node according to an embodiment of the present application is shown.

[0038] like Figure 4 As shown, the logic system design 400 may include a plurality of basic logic units (eg, addition, subtraction, various logic gates, etc.). Figure 4 These basic logic units are shown in circles (e.g., 4011, 4013, 4031, 4033, 4035, 4051, 4071, etc.), and an ordered diagram is presented due to the data dependency between the basic logic units. It can be understood that the logic system design 400 can be a complete chip design or a part of a complete chip design.

[0039] These basic logical units can be combined into Mtask (macro task) nodes, for example, Figure 4In the embodiment of the present invention, multiple task nodes 401, 403, 405 and 407 are shown. For example, for a graphics processing chip, each graphics processing unit is relatively independent and can be used as a task node.

[0040] Each task node can include multiple basic logic units and still ensure the original simulation order. Usually, a logic system design 400 can be converted into hundreds of nodes. Figure 4 This is for exemplary purposes only.

[0041] In some embodiments, the simulation tool 200 may perform an ordered graph merge of basic logic units based on maximum fanout freecones (MFCC) to obtain task nodes. Figure 4 In FIG. 4 , basic logic units 4011 , 4013 and A are combined into MFCC A, and this MFCC A can be a task node 401. Similarly, the logic system design 400 can also generate task nodes 403 , 405 and 407.

[0042] Depending on the number of basic logic units included in an MFCC, the logic system design 400 may have different numbers of task nodes. For example, task nodes 401 and 403 may be further merged into task node 409.

[0043] In some embodiments, the simulation tool 200 may obtain a number limit of task nodes and merge multiple basic logic units of the logic system design 400 into multiple task nodes according to the number limit.

[0044] Generally speaking, the simulation tool 200 can merge basic logic units with more data dependencies into one MFCC (i.e., one task node), thereby reducing the dependencies between task nodes. In this way, when simulating these task nodes in parallel, since there are fewer data dependencies between them, the performance overhead of synchronization during the simulation process can be reduced, thereby improving the simulation performance.

[0045] At the same time, basic logic units with more data dependencies are more likely to be triggered or not triggered at the same time. Therefore, merging basic logic units with more data dependencies into one MFCC (i.e., one task node) can reduce the possibility of triggering task nodes. For task nodes that are not triggered, the simulation tool 200 can skip their simulation to further improve simulation performance. In the present application, triggering means that an input signal can cause a task node (e.g., one or more basic logic units) that receives the input signal to produce a change in state (e.g., an output signal).

[0046] Figure 5A schematic diagram of a structure 500 of a logic system design including multiple task nodes according to an embodiment of the present application is shown.

[0047] As described above, if a task node is not triggered, the simulation tool 200 may skip its simulation. Therefore, the simulation tool 200 may receive an input signal of a task node and determine whether the input signal causes the task node to be triggered.

[0048] A signal that can cause a task node to be triggered may be referred to as a trigger signal.

[0049] In some embodiments, the simulation tool 200 can determine one or more trigger signals of a task node according to the description of the logic system design. For example, the simulation tool 200 can determine the trigger signal of the combinational circuit according to the characteristics of the combinational circuit of the logic gate. Since this is a technical solution familiar in the art, it will not be repeated here. Therefore, for a task node, the simulation tool 200 can determine the trigger signal of the task node.

[0050] The simulation tool 200 can determine whether a task node will be triggered in an iteration according to the above determined trigger signal and the received input signal.

[0051] In some embodiments, the above-mentioned process of determining the trigger is part of the simulation tool 200 performing the simulation. Figure 5 As shown, the above trigger determination process can be solidified as a part of the logic system design. Figure 5 In the embodiment, the trigger determination units 501, 503, 505 are provided to the task nodes 405, 407, 409 respectively, for respectively determining whether the input signals received by the task nodes 405, 407, 409 trigger the task nodes 405, 407, 409.

[0052] It is understandable that how to implement the above-mentioned trigger determination process can be adjusted according to the needs of the application and is not necessarily limited to the embodiments or Figure 5 .

[0053] by Figure 5 To continue the description by taking an example, the trigger determination unit 501 receives the input signal before the task node 405 corresponding thereto, and determines whether the task node 405 is triggered. In response to determining that the task node 405 is triggered, the input signal may be provided to the task node 405 for simulating the task node 405. In response to determining that the task node 405 is not triggered, the simulation tool 200 may maintain the previous state of the task node 405, that is, the output signal of the task node 405 remains unchanged.

[0054] The operation of the task nodes 407, 409 and the trigger determination units 503, 505 is similar to that of the above-mentioned task node 405 and the trigger determination unit 501, and will not be described again.

[0055] In order to quickly determine whether a task node is triggered, the simulation tool 200 can store the trigger signal of the task node in a continuous memory space of the memory of the electronic device 100 running the simulation tool 200. It is understandable that the continuous memory space means that the trigger signal of the task node is stored in a continuous memory address. In this way, when a new simulation cycle (for example, a new iteration or a new clock cycle) arrives, the simulation tool 200 can compare whether the value stored in the continuous memory space changes to determine whether the trigger signal has changed. It is understandable that once the trigger signal of the task node changes, it can usually be considered that the task node is triggered. For example, the simulation tool 200 can save the value of the continuous memory space at a first time point (for example, the starting point of the first simulation cycle) and the value of the second time point (for example, the starting point of the second simulation cycle), and compare whether there is a difference between the two values. Once it is determined that the memory space is different at the first time point and the second time point, the simulation tool 200 determines that the task node is triggered at the second time point.

[0056] Figure 6 A schematic diagram of an arrangement 600 for simulating multiple task nodes according to an embodiment of the present application is shown.

[0057] As described above, multiple task nodes can be obtained by merging the basic logic units of the logic system design. The simulation tool 200 can determine the arrangement of simulating the multiple task nodes according to the event-driven simulation method. For example, Figure 6 As shown, arrangement 600 includes simulating task nodes 601 and 603 first, simulating task node 605 second, and simulating task node 607 last. It is understandable that task nodes that do not have data dependency on each other can be simulated in parallel. Each task node may include one or more child nodes. It is understandable that the child node may include one or more basic logic units. That is to say, in some embodiments, the child node may be a smaller task node, and in other embodiments, the child node may be a basic logic unit.

[0058] Although the arrangement of simulating the multiple task nodes is determined by using an event-driven simulation method at the task node level, when simulating each task node, the subnodes included in the task node are simulated in a clock cycle-based simulation method. For example, when simulating task node 603, subnodes 6031, 6033, and 6035 are simulated in a clock cycle-based simulation method.

[0059] In this way, event-driven simulation is used at the task node level and clock cycle-based simulation is used at the sub-node level, thereby realizing hybrid simulation and accelerating the simulation of logic system design.

[0060] Figure 7 A schematic diagram of another arrangement 700 for simulating multiple task nodes according to an embodiment of the present application is shown.

[0061] Since there are many possibilities for merging basic logic units, there are many possibilities for merging multiple basic logic units of a logic system design to generate multiple task nodes (for example, Figure 4 and 5 ). Generally, a user may provide a constraint of a maximum number of task nodes (eg, 500) to the simulation tool 200, and then the simulation tool 200 merges basic logic units within the maximum number.

[0062] Since there is a possibility of further merging and splitting of task nodes, the simulation tool 200 can dynamically adjust the merging and splitting of any nodes according to the operation of the logic system design, thereby improving the simulation efficiency.

[0063] In some embodiments, simulation tool 200 can simulate logic system design in a first time period according to a first group of multiple task nodes. For example, simulation tool 200 can simulate logic system design according to arrangement 600 in a time period of 10 cycles. The cycle here can be an iteration or a clock cycle. Simulation tool 200 can obtain and analyze the triggering situation of these 10 cycles through an analysis (profile) tool. The triggering situation can include the triggering situation of task nodes 601-607 in 10 cycles. For example, simulation tool 200 can find that task nodes 601 and 603 are all triggered and not triggered in the same cycle in these 10 cycles.

[0064] According to the triggering conditions of the above-mentioned task nodes 601-607 within the time period of the 10 cycles, the simulation tool 200 can merge the plurality of task nodes 601-607 to form a second group of a plurality of task nodes, such as Figure 7 Arrangement 700 is shown. Figure 7 As shown, since task nodes 601 and 603 are triggered and not triggered in the same cycle in these 10 cycles, task nodes 601 and 603 can be merged into a new task node 701 to reduce the computational burden of the simulation.

[0065] Understandably, Figure 7Only task nodes 601 and 603 are shown to be merged during the operation of the simulation of the logic system design, but the task node can also be split (for example, multiple sub-nodes in a task node are split into two independent task nodes). At the same time, the merging and splitting of sub-nodes within the task node is also possible, which will not be repeated here.

[0066] By implementing event-driven simulation and clock cycle-based simulation at different stages of the simulation logic system design, the embodiment of the present application provides a hybrid architecture simulation method, which makes full use of two completely different simulation methods to accelerate the simulation of the logic system design, and maximizes the advantages and minimizes the disadvantages. At the same time, by dynamically adjusting the merging and splitting of task nodes during the runtime of the simulation logic system design, the simulation of the logic system design can be further dynamically optimized.

[0067] The embodiment of the present application also provides a method for designing a simulation logic system.

[0068] Figure 8 FIG. 8 is a flow chart showing a method 800 for designing a simulation logic system according to an embodiment of the present application. The method 800 may be Figure 1 The electronic device 100 shown is implemented, more specifically, by the simulation tool 200 running on the electronic device 100. The method 800 may include the following steps.

[0069] In step 802, the simulation tool 200 may be configured based on the logic system design (e.g., Figure 4 The description of the logic system design 400 ) determines a plurality of basic logic units (eg, basic logic unit 4011 , etc.) of the logic system design.

[0070] In step 804, the simulation tool 200 may merge the multiple basic logic units into multiple task nodes (eg, Figure 4 Task node 401 or Figure 6 Each of the plurality of task nodes includes one or more child nodes (eg, child nodes 6011 and 6013 of task node 601).

[0071] In step 806, the simulation tool 200 may determine the simulation schedule of the plurality of task nodes in an event-driven simulation manner (eg, Figure 6 Arrangement 600 or Figure 7 Arrangement 700), the multiple task nodes include a first task node.

[0072] At step 808 , in response to scheduling the first task node simulation, one or more sub-nodes of the first task node are simulated in a clock cycle-based simulation manner.

[0073] In some embodiments, the method 800 further includes: determining whether each of the plurality of task nodes is triggered. Figure 5 The description of determining the simulation arrangement of the plurality of task nodes in an event-driven simulation manner further includes: responding to a target task node (eg, Figure 5 The target task node 405 is not triggered at a time point, and the simulation of the target task node is skipped (for example, the output of the previous state is maintained); in response to the target task node being triggered at the time point, the simulation of the target task node is scheduled.

[0074] In some embodiments, determining whether each of the multiple task nodes is triggered further includes: setting multiple trigger signals of the target task node in a continuous memory space; determining whether there is a difference between the memory space at a first time point and a second time point; in response to the difference between the memory space at the first time point and the second time point, determining that the target task node is triggered at the second time point.

[0075] In some embodiments, merging the plurality of basic logic units into a plurality of task nodes further comprises: merging the plurality of basic logic units into a first plurality of task nodes (eg, Figure 6 The number of the plurality of task nodes in the first group is specified by a user, for example, input to the simulation tool 200 by the user.

[0076] In some embodiments, the simulation tool can dynamically split and merge task nodes. Merging the multiple basic logic units into multiple task nodes further includes: simulating the logic system design in a first time period according to the first group of multiple task nodes; further merging or splitting the multiple task nodes to form a second group of multiple task nodes (for example, Figure 7 It can be understood that merging the plurality of task nodes to form a second group of plurality of task nodes may be a part of merging or splitting the plurality of task nodes of the first group.

[0077] By implementing event-driven simulation and clock cycle-based simulation at different stages of the simulation logic system design, the embodiment of the present application provides a hybrid architecture simulation method, which makes full use of two completely different simulation methods to accelerate the simulation of the logic system design, and maximizes the advantages and minimizes the disadvantages. At the same time, by dynamically adjusting the merging and splitting of task nodes during the runtime of the simulation logic system design, the simulation of the logic system design can be further dynamically optimized.

[0078] The present application also provides an electronic device. The electronic device may be Figure 1 The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method 800.

[0079] The embodiment of the present application further provides a non-transitory computer-readable storage medium, which stores a set of computer instructions, and the set of instructions is used to make the computer perform method 800 when executed.

[0080] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0081] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0082] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0083] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for designing a simulation logic system, comprising: Determine a plurality of basic logic units of the logic system design according to the description of the logic system design; Merging the multiple basic logic units into multiple task nodes, each of the multiple task nodes includes one or more sub-nodes; Determining a simulation arrangement of the plurality of task nodes in an event-driven simulation manner, the plurality of task nodes including a first task node; as well as In response to scheduling the first task node simulation, simulating one or more subnodes of the first task node in a clock cycle-based simulation manner; Wherein, determining the simulation arrangement of the plurality of task nodes in an event-driven simulation manner further comprises: In response to a target task node not being triggered at a time point, skipping the simulation of the target task node; In response to the target task node being triggered at the time point, arranging simulation of the target task node.

2. The method of claim 1, further comprising: It is determined whether each of the plurality of task nodes is triggered.

3. The method of claim 1, wherein: Determining whether each of the plurality of task nodes is triggered further comprises: Setting multiple trigger signals of the target task node in a continuous memory space; Determine whether there is a difference between the memory space at the first time point and the second time point; In response to a difference between the memory space at the first time point and the second time point, it is determined that the target task node is triggered at the second time point.

4. The method of claim 1, wherein: Merging the multiple basic logic units into multiple task nodes further includes: The multiple basic logic units are merged into a first group of multiple task nodes based on the data dependency relationship between the multiple basic logic units, wherein the number of the multiple task nodes in the first group is specified by a user.

5. The method of claim 4, wherein: Merging the multiple basic logic units into multiple task nodes further includes: simulating the logic system design within a first time period according to the first plurality of task nodes; According to the triggering conditions of the first group of multiple task nodes within the first time period, the multiple task nodes are further merged or split to form a second group of multiple task nodes.

6. An electronic device comprising: A memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions so that the electronic device performs the method according to any one of claims 1 to 5.

7. A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method according to any one of claims 1 to 5 when executed.

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