High-K Metal-Insulator-Metal (MIM) Capacitor Networks for Hysteresis Mitigation

Abstract

The present disclosure relates to a high-k metal-insulator-metal (MIM) capacitor network for hysteresis mitigation. A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor switch pairs are coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor switch pairs includes a lateral overflow integrator capacitor (LOFIC) and a switching transistor coupled to the LOFIC.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to evolve rapidly. For example, the demand for higher resolution and lower power consumption has driven the further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and photogenerate image charge upon absorption. The photogenerated image charge by the pixels can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of photogenerated image charge is proportional to the intensity of the image light, which is read out from the column bit lines as an analog signal and converted into a digital value to produce a digital image representing the external scene (i.e., image data).

[0004] Standard image sensors have a limited dynamic range of approximately 60 to 70 dB. However, the real-world dynamic range of brightness is much greater. For example, natural scenes often span a range of 90 dB or more. To capture details in both bright highlights and dark shadows, high dynamic range (HDR) technology has been used in image sensors to increase the captured dynamic range. Summary of the Invention

[0005] In one aspect, the present disclosure relates to a pixel circuit comprising: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion; a reset transistor coupled between a reset voltage and the floating diffusion; and a plurality of capacitor switch pairs coupled between the reset transistor and a bias voltage source, wherein each of the plurality of capacitor switch pairs comprises: a lateral overflow integrator capacitor (LOFIC); and a switch transistor coupled in series between the reset transistor and the LOFIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 An example of an imaging system including a pixel array according to the teachings of the present disclosure is described.

[0008] Figure 2 A schematic diagram illustrating one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and a photodiode according to the teachings of the present disclosure.

[0009] Figure 3A 、 3B and 3C illustrate timing diagrams for different frame periods of example signal values in an example pixel circuit including a LOFIC network and a photodiode during idle, precharge, integration, and readout periods according to the teachings of the present disclosure.

[0010] Figure 4 Illustrated is a cross-section of a pixel circuit including a LOFIC network and a photodiode on a substrate according to the teachings of the present disclosure.

[0011] Figure 5 Illustrated is a cross-section of a LOFIC on a substrate according to the teachings of the present disclosure.

[0012] Figure 6 A first wafer including a pixel array is illustrated stacked with a second wafer including a LOFIC network array in accordance with the teachings of the present disclosure.

[0013] Figure 7 A schematic diagram illustrating one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and two photodiodes according to the teachings of the present disclosure.

[0014] Figure 8A 、8B and 8C illustrate timing diagrams for different frame periods of example signal values in an example pixel circuit including a LOFIC network and two photodiodes during pre-charge, integration, and readout periods according to the teachings of the present disclosure.

[0015] Figure 9 The illustration shows a diagram showing a top-down view of a pixel circuit including a LOFIC network and two photodiodes on a substrate according to the teachings of the present disclosure.

[0016] Figure 10 Illustrated is a cross-section of a pixel circuit including a LOFIC network on a substrate and two photodiodes in accordance with the teachings of the present disclosure.

[0017] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. Additionally, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted to facilitate a more unobstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] This document describes examples of imaging systems having a pixel array including pixel circuits, each of which has a LOFIC network that provides reduced image lag. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein can be practiced without employing one or more of these specific details or with other methods, components, materials, and the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0019] Reference throughout this specification to "one example" or "one embodiment" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrases "in one example" or "one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0020] For ease of description, spatially relative terms such as "below," "below," "above," "below," "above," "up," "top," "bottom," "left," "right," "center," "middle," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as being "below," "beneath," or "beneath" another element or feature would be oriented "above" the other element or feature. Thus, the exemplary terms "below" or "beneath" may encompass both above and below orientations. The device may be oriented in other ways (rotated ninety degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, it should be understood that when an element is referred to as being "between" two other elements, it may be the only element between the other two elements, or one or more intervening elements may also be present.

[0021] Throughout this specification, several technical terms are used. These terms have their ordinary meaning in the fields from which they originate, unless explicitly defined herein or the context of their use clearly indicates otherwise. It should be noted that component names and symbols may be used interchangeably throughout this document (e.g., Si versus silicon); however, both have the same meaning.

[0022] As will be discussed, various examples of imaging systems are disclosed that include a pixel array having pixel circuits, each pixel circuit having a LOFIC network configured to provide reduced image lag. It will be appreciated that a LOFIC can be included in a pixel circuit to increase the full well capacity of the pixel circuit and thereby increase the high dynamic range capability of a corresponding image sensor. The LOFIC capacitance is positively correlated to the full well capacity. Thus, as the capacitance of the LOFIC employed in a pixel circuit increases, the full well capacity of the pixel circuit also increases. To this end, a higher LOFIC capacitance is typically required. However, due to the significant RC load created as the capacitance of the LOFIC increases, the time required for the row driver of the imaging system to charge and / or reset the LOFIC also increases. Thus, as the capacitance of the LOFIC in the pixel circuit increases, image lag increases, which results in a slower frame rate.

[0023] It should be understood that image lag caused by LOFIC can be associated with high dielectric constant or high-k materials included in the insulating material of metal-insulator-metal (MIM) LOFICs due to the hysteresis characteristics and slow relaxation behavior of high-k materials that require long discharge times (e.g., hundreds of milliseconds). The relaxation behavior of high-k materials can lead to image degradation, such as image lag due to a number of mechanisms including trap-to-trap tunneling, structural relaxation, coupling with phonon energy, and so on.

[0024] As will be shown in various examples below, an example pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. In one example, a reset transistor is coupled between a bias voltage source and the floating diffusion. In another example, a reset transistor is coupled between a reset voltage source and the floating diffusion. The reset transistor is configured to switch in response to a reset control signal.

[0025] In various examples, the pixel circuit further includes a LOFIC network that provides additional storage capacity configured to store overflow image charge for high dynamic range (HDR) image acquisition. In various examples, the LOFIC network includes two or more capacitor switch pairs, each capacitor switch pair including a LOFIC and a switching transistor. In various examples, each capacitor switch is coupled in parallel with each other. In various examples, each LOFIC is a metal-insulator-metal (MIM) storage capacitor that includes a high-k insulating region disposed between a first metal electrode and a second metal electrode. In various examples, the first metal electrode of each LOFIC is coupled to a bias voltage source, and the second metal electrode of each LOFIC is coupled to a switching transistor of the corresponding capacitor switch pair, which is locally coupled to a reset transistor through one or more circuit elements of the pixel circuit including a floating diffusion of the pixel circuit. In various examples, the LOFIC can be disposed in a location separate from the anti-blooming path of the pixel circuit's photodiode so that there is no charging stress on the LOFIC during idle periods.

[0026] Image lag is caused by the slow discharge of residual charge in the LOFIC, which can cause the pixel circuit to be unable to keep up with the required image sensor frame rate. If the residual charge from the previous frame is not fully discharged, it will appear in the next frame, resulting in undesirable image lag. A LOFIC network according to the teachings of the present disclosure is able to fully discharge the residual charge in the LOFIC by alternately coupling the LOFIC to the rest of the pixel circuit on a frame-by-frame basis. In one example, during each frame cycle of the image sensor, only a single switch in the capacitor switch pair of the LOFIC network is turned on. When the image sensor moves to the next frame, the previously turned-on switching transistor is turned off, and the other switching transistor is turned on. In other words, in one example, multiple switching transistors are alternately turned on, with only one switching transistor turned on in a given frame, so that the LOFIC coupled to the turned-off switching transistor can discharge the residual charge before the frame in which its corresponding switching transistor will turn on. As a result, the LOFIC storing charge from its active frame cycle has sufficient idle periods to fully relax and fully discharge before the integration period in its next active frame. The number of capacitor switch pairs may depend on the desired frame rate and the time required for the LOFIC to fully discharge (e.g., greater than 10 ms, greater than 100 ms). For example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 30 frames per second (fps) is desired (each frame lasting approximately 33 ms), then the LOFIC network should have at least two capacitor switch pairs. As another example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 60 frames per second (fps) is desired (each frame lasting approximately 17 ms), then the LOFIC network should have at least three capacitor switch pairs.

[0027] To illustrate, Figure 1 One example of an imaging system 100 having a pixel array with pixel circuits each including a LOFIC network that provides reduced image lag according to the teachings of the present disclosure is shown. Specifically, Figure 1 The example depicted in illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array that includes a plurality of pixel circuits 104 (e.g., P1, P2, . . . , Pn) arranged in rows (e.g., R1 through Ry) and columns (e.g., C1 through Cx) to obtain image data of a person, location, object, etc., which can then be used to render an image of the person, location, object, etc.

[0028] In various examples, each pixel circuit 104 may include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in the one or more photodiodes is transferred to a floating diffusion included in each pixel circuit 104, where it can be converted into an image signal that is then read out from each pixel circuit 104 via column bit lines 112 by readout circuitry 106. As will be discussed, in various examples, pixel circuits 104 may also be configured to provide HDR image signals. In such cases, the image charge generated by the one or more photodiodes under bright lighting conditions may also be transferred to a LOFIC network and / or additional floating diffusions in each pixel circuit 104 to store the image charge. For example, each pixel circuit 104 may include a LOFIC network configured to store one or more excess image charges overflowing from the coupled one or more photodiodes during an integration period. In various examples, readout circuitry 106 may be configured to read out the image signal via column bit lines 112. In various examples, readout circuitry 106 may include a current source, routing circuitry, and a comparator, which may be included in an analog-to-digital converter or other converter.

[0029] In the example, the digital image data values produced by the analog-to-digital converter in readout circuitry 106 may then be received by function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other).

[0030] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect, such as a flash.

[0031] In one example, the imaging system 100 may be included in an imaging device for a digital camera, a cellular phone, a laptop computer, an endoscope, a security camera, or an automobile, or the like. Additionally, the imaging system 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting / flashlights, electrical inputs (keyboard, touch display, trackpad, mouse, microphone, etc.), and / or a display. The other hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate image data supplied by the imaging system 100.

[0032] Figure 2Schematic diagram illustrating one example of a pixel circuit including a LOFIC network and a photodiode according to the teachings of the present disclosure. It should be understood that Figure 2 The pixel array circuit 204 may be Figure 1 An example of one of the pixel circuits 104 included in the pixel array 102 is shown in FIG. 1 , and similarly named and numbered elements described above may be similarly coupled and function below.

[0033] As shown in the depicted example, pixel circuit 204 includes a photodiode 214 configured to photogenerate image charge in response to incident light. In the depicted example, pixel circuit 204 also includes a first floating diffusion FD1 218 coupled to receive image charge from photodiode 214 via a transfer transistor 216. In the depicted example, transfer transistor 216 is coupled to be controlled in response to a transfer control signal TX 246 to transfer image charge from photodiode 214 to first floating diffusion FD1 218, for example, during a readout cycle associated with pixel circuit 204. A source-follower transistor 220 has a gate coupled to first floating diffusion FD1 218, and a row select transistor 222 is coupled to source-follower transistor 220 such that source-follower transistor 220 and row select transistor 222 are coupled between power supply line AVDD and bit line 212 to output an image signal from pixel circuit 204 in response to a row select control signal RS 248 and the amount of charge at the gate of source-follower transistor 220.

[0034] exist Figure 2 In the illustrated example, a dual floating diffusion transistor 224 is coupled between a first floating diffusion FD1 218 and a second floating diffusion FD2 226. The second floating diffusion FD2 226 is coupled to a capacitor configured to receive excess image charge overflow from the photodiode 214 through the transfer transistor 216 and the dual floating diffusion transistor 224. The second floating diffusion FD2 226 is further coupled to the source of the LOFIC transistor 228. A third floating diffusion FD3 230 is coupled between the LOFIC transistor 228 and the reset transistor 232. The drain of the reset transistor 232 is coupled to the reset voltage source PIXVDD, and the source of the reset transistor 232 is coupled to the third floating diffusion FD3 230. Double floating diffusion transistor 224 is coupled to be controlled in response to double floating diffusion control signal DFD 244 , LOFIC transistor 228 is coupled to be controlled in response to LOFIC transistor control signal LOF 242 , and reset transistor 232 is coupled to be controlled in response to reset control signal RST 240 .

[0035] As shown in the depicted example, pixel circuit 204 also includes a LOFIC network 250 coupled between bias voltage source VCAP 238 and third floating diffusion FD3 230. Thus, it should be appreciated that LOFIC network 250 is selectively coupled to first floating diffusion FD1 218 through LOFIC transistor 228 and dual floating diffusion transistor 224. LOFIC network 250 is configured to receive excess image charge overflow from photodiode 214 (e.g., under bright light conditions, such as IR or LED light).

[0036] In the example, the LOFIC network 250 includes two or more capacitor-switch pairs coupled in parallel. Each capacitor-switch pair includes a corresponding LOFIC 254-n and a switching transistor 256-n. The switching transistor 256-n is coupled in series to the corresponding LOFIC 254-n between the bias voltage source VCAP 238 and the third floating diffusion FD3 230. The switching transistors are coupled to be controlled in response to switch control signals SW-1...SW-n 234-1...234-n. As will be discussed in various examples, the inactive LOFICs 254-1...254-n in the LOFIC network 250 are given sufficient time to relax and fully discharge any residual charge. By alternately coupling and decoupling the LOFICs 254-1...254-n from the rest of the pixel circuitry on a frame-by-frame basis via the switching transistors 256-1...256-n, the residual charge does not affect the next captured frame during operation. For example, during each frame period of the image sensor, only a single switch (e.g., 256-1) of the capacitor switch pair of the LOFIC network 250 is turned on. When the image sensor moves to the next frame, a different switch transistor (e.g., 256-2) is turned on, and all other switch transistors, including the switch transistors that were turned on during the previous frame (e.g., 256-1, 256-3, ..., 256-n), are turned off. The LOFICs 254-1 ... 254-n coupled to the corresponding switched transistors 256-1 ... 256-n that were turned off can discharge residual charge before the frame in which their corresponding switched transistors were turned on. As a result, the LOFIC 254-n, which stored charge from its active frame period, has sufficient idle period to fully relax and discharge before its integration period in the next active frame, thereby reducing any undesirable image lag (e.g., visible artifacts on the captured frame).

[0037] In various examples, the number of capacitor switch pairs can depend on the desired frame rate and the time required for the LOFIC to fully discharge (e.g., greater than 10 ms, greater than 100 ms). For example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 30 frames per second (fps) is desired (each frame lasting approximately 33 ms), then the LOFIC network should have at least two capacitor switch pairs. As another example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 60 frames per second (fps) is desired (each frame lasting approximately 17 ms), then the LOFIC network should have at least three capacitor switch pairs. Having more capacitor switch pairs can increase the reduction in image lag, but this should be balanced against the larger size of the semiconductor substrate required to accommodate all elements of the pixel circuit 204.

[0038] In the example, LOFIC 254-n is implemented as a metal-insulator-metal (MIM) capacitor comprising a high-dielectric, or high-k, insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first and second metal electrodes of LOFIC 254-n may be formed from a single layer of high-k material or a stack of multiple layers of high-k material. The exact composition and total thickness of the high-k material may depend on the desired capacitance of the LOFIC. In various examples, the high-k material may include one of aluminum oxide (AhO3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or a combination thereof. LOFICs 254-1…254-n may have substantially the same size, dielectric composition, and / or dielectric thickness.

[0039] In operation, bias voltage source VCAP 238 is configured to provide a bias voltage to LOFIC network 250 during precharge and readout cycles. In one example, bias voltage source VCAP 238 may have a value between 0V and 3.5V. It should be appreciated that, in various examples, the voltage level of bias voltage source VCAP 238 may be determined taking into account the stability range of high-k materials. In the example, during an idle period, reset control signal RST 240 may have a value sufficient to turn on reset transistor 232 (e.g., between 2.5V and 4V), double floating diffusion control signal DFD 244 may have a high voltage value ranging between 2.5V and 4V, LOFIC transistor control signal LOF 242 may have a value between 0V and 4V, and transfer control signal TX 246 may have a value between 0V and 3V.

[0040] Figure 3A 、 3B 3C and 3C respectively illustrate timing diagrams of the first, second, and nth frame periods of example signal values in an example pixel circuit including a LOFIC network and a photodiode. According to the teachings of the present disclosure, each frame (i.e., Figure 3A、 3B and each of the 3C) operates in idle, precharge, integration and readout cycles. It should be understood that Figure 3A 、 3B And the signal described in 3C can be Figure 2 Examples of signals for controlling the operation of an example pixel circuit, such as pixel circuit 204, are depicted in , and similarly named and numbered elements described above may be similarly coupled and function below.

[0041] Referring now to the described examples, Figure 3A 、 3B 3C illustrates a reset control signal RST 340, a bias voltage VCAP 338, a double floating diffusion control signal DFD 344, a LOFIC control signal LOF 342, a transfer control signal TX 346, a row select control signal RS 348, a first switch control signal SW-1 334-1, a second switch control signal SW-2 334-2, and an nth switch control signal SW-n 334-n, which are configured to control the above-mentioned Figure 2 Various circuit elements are discussed in detail in .

[0042] like Figure 3A 、 3B As shown during the idle period of each frame depicted in 3C , reset control signal RST 340 turns on reset transistor 232. Bias voltage VCAP 338, double floating diffusion control signal DFD 344, LOFIC control signal LOF 342, transfer control signal TX 346, row select control signal RS 348, first switch control signal SW-1 334-1, second switch control signal SW-2 334-2, and nth switch control signal SW-n 334-n are all configured to have low values (e.g., 0 volts) during the idle period. In various examples, LOFIC network 250 shortens the idle period because residual charge in the LOFIC can be discharged during one or more complete frame periods, not just the idle period.

[0043] At time t1, the idle period ends, the reset control signal RST 340 drops back to a low value (e.g., 0 volts), and the precharge period begins. For each frame, one of the switch control signals SW-1...SW-n 334-1...334-n turns on the corresponding switch transistor 256-1...256-n (e.g., at Figure 3A , the first switch control signal SW-1 334-1 is turned on), while the remaining switch control signals SW-1 ... SW-n 334-1 ... 334-n are simultaneously turned off (e.g., Figure 3A334-n are turned off). Next, row select control signal RS 348 turns on row select transistor 222. LOFIC control signal LOF 342 then turns on LOFIC transistor 228, and then dual floating diffusion control signal DFD 344 turns on dual floating diffusion transistor 224, and then bias voltage source VCAP 338 turns on, and then reset control signal RST 340 turns on reset transistor 232, and then transfer control signal TX 346 turns on transfer transistor 216. At this point during the precharge cycle, photodiode 214, first, second, and third floating diffusions FD1-3 218, 226, 230 are all reset by reset transistor 232. The control signals are then switched to low values (e.g., 0 volts) in the reverse order so that transfer control signal TX 346 turns off transfer transistor 216 first and row select control signal RS 348 turns off row select transistor 222 last. Figure 3A 、 3B 3C , the switch control signal SW-n 334 - n turned on at time t1 remains on until the readout period of the frame period ends.

[0044] At time t2, the precharge period ends and the integration period begins. All control signals are low except for switch control signal SW-n, which is coupled to active LOFIC 254-n and corresponds to the frame in which it remains on, as described above. During the integration period, photodiode 214 photogenerates image charge in response to incident light. Pixel circuit 204 is configured so that excess photogenerated charge can overflow from photodiode 214 into LOFIC network 250 through dual floating diffusion transistor 224 and LOFIC transistor 228 for storage in bright or intense light conditions (e.g., LED light or IR light).

[0045] In one example, during the integration period, photogenerated excess image charge is configured to overflow from photodiode 214 to second floating diffusion FD2 226 through dual floating diffusion transistor 224 and to LOFIC network 250 through dual floating diffusion transistor 224 and LOFIC transistor 228 .

[0046] At time t3, the integration period ends and the readout period begins. Row select control signal RS 348 turns on row select transistor 222, LOFIC control signal LOF 342 then pulses LOFIC transistor 228, and dual floating diffusion control signal DFD 344 then turns on dual floating diffusion transistor 224, and bias voltage source VCAP 338 then turns on or couples to apply a bias voltage to LOFIC network 250 for charge readout.

[0047] Next, a correlated double sampling (CDS) readout of the photodiode 214 occurs, during which a medium conversion gain (MCG) readout occurs from the reset value (R) of the photodiode 214. Next, the dual floating diffusion control signal DFD 344 turns off the dual floating diffusion transistor 224, and then a high conversion gain (HCG) readout occurs from the reset value (R) of the photodiode 214. Next, the transfer control signal TX 346 pulses the transfer transistor 216, and then an HCG readout of the signal value (S) occurs based on the charge transferred to the first floating diffusion FD1 218. Next, the dual floating diffusion control signal DFD 344 turns on the dual floating diffusion transistor 224, and then the transfer control signal TX 346 pulses the transfer transistor 216 again, after which an MCG readout of the signal value (S) occurs based on the charge in the first floating diffusion FD1 218 and the second floating diffusion FD2 218.

[0048] Next, LOFIC control signal LOF 342 turns on LOFIC transistor 228, and then transfer control signal TX 346 turns on transfer transistor 216. Next, LOFIC readout of photodiode 214 occurs, during which a low conversion gain (LCG) readout of the signal value (S) occurs based on the charge in first floating diffusion FD1 218, second floating diffusion FD2 218, and corresponding LOFIC 254-n. Next, reset control signal RST 340 pulses reset transistor 232, and then an LCG readout of the reset value (R) of photodiode 214 occurs. In various examples, a CDS MCG readout can be determined by finding the difference between the MCG signal value (S) and the MCG reset value (R), a CDS HCG readout can be determined by finding the difference between the HCG signal value (S) and the HCG reset value (R), and a CDS LCG readout can be determined by finding the difference between the LCG signal value (S) and the LCG reset value (R).

[0049] Afterwards, the reset control signal RST 340 turns on the reset transistor 232 at time t4, and all other signals, including the switch control signal SW-n 334-n turned on at time t1, turn off their corresponding transistors. At time t4, for the next frame, the readout period ends and the idle period begins again. Figure 3A 、 3B As shown in FIG3C , the difference between frames is which switch control signal SW-n 334-n is turned on. If there are two capacitor switch pairs in the LOFIC network 250, the timing diagram will be Figure 3A and 3B If there are five capacitor switch pairs in the LOFIC network 250, then for the sixth frame, the timing diagram will return to Figure 3A .

[0050] Figure 4 4 illustrates a cross-section of one example of a pixel circuit 404 including a LOFIC network 450 and a photodiode 414 on a substrate 462 in accordance with the teachings of the present disclosure. Figure 4 The pixel circuit 404 may be Figure 1 The pixel circuit 104 or the pixel circuit 104 included in the pixel array 102 shown in FIG. Figure 2 4. A pixel circuit 204 of FIG. 4 is shown in FIG. 4, and similarly named and numbered elements described above may be similarly coupled and function below. As shown in the depicted example, above the photodiode 414 and substrate 462 are a gate layer 405 and a plurality of metal layers, including a first metal layer 415, a second metal layer 425, a third metal layer 435, a fourth metal layer 445, and a fifth metal layer 455. In the depicted example, the LOFICs of the LOFIC network 450 (each LOFIC including a plurality of LOFICs 454) are disposed in the fourth metal layer 445. In some examples, the LOFIC network 450 may be disposed within an allocated pixel area of the pixel circuit 404.

[0051] exist Figure 4 In the depicted example, pixel circuitry 404 may include two different interlayer materials: an intermetal dielectric (IMD) 465 and an interlayer dielectric (ILD) 467. In various examples, the IMD and ILD have different dielectric constants. Typically, the IMD is used for copper interconnects and includes a high-k material film (e.g., hafnium oxide), while the ILD is used to encapsulate transistor gates and includes an oxide material film with a lower dielectric constant.

[0052] Figure 5 The illustration shows a cross section of increased detail of one example of a LOFIC 554 in an intermetal dielectric (IMD) 565 according to the teachings of the present disclosure. It should be understood that Figure 5 The LOFIC 554 may be an example of one of the LOFICs 254-n, and the switch transistor 556 may be Figure 2 One or more of the switching transistors 256-n included in the pixel circuit 204 shown Figure 4 4 and 5. In the depicted example, the LOFIC 554 is disposed in the IMD 565 near the semiconductor substrate (e.g., Figure 44. The LOFIC 554 includes a capacitor bottom metal (CBM) electrode 557, a high-k insulating material 558, and a capacitor top metal (CTM) electrode 559. In the illustrated example, the CTM electrode 559 surrounds the insulating material 558 and the CBM electrode 557 in the center of the LOFIC 554. However, in other embodiments, the CTM and CBM electrodes 559 and 557 can be arranged according to a conventional capacitor structure, such as with parallel plates. The CTM electrode 559 is coupled to a bias voltage source, VCAP 538, and the CBM electrode 557 is coupled to a corresponding switch transistor 556, which is further coupled to a floating diffusion node (e.g., Figure 2 The third floating diffusion FD3 230) or the reset transistor (eg, Figure 2 The LOFIC 554 is insulated from other circuit elements using an IMD layer 565, such as Figure 4 Each LOFIC 554 can have substantially the same size, dielectric composition, and / or dielectric thickness.

[0053] Figure 6 An imaging system 600 is illustrated having a first wafer 670 stacked with and coupled to a second wafer 672 in accordance with the teachings of the present disclosure. It should be understood that Figure 6 The imaging system 600 may be Figure 1 , and similarly named and numbered elements described above may be similarly coupled and function below. The first and second wafers 670 and 672 may be semiconductor wafers and may be stacked and interconnected by bonding (e.g., hybrid bonding, oxide bonding) or one or more through-substrate vias (TSVs). The second wafer 672 may be an application-specific integrated circuit (ASIC) wafer. The first wafer 670 includes a pixel array 602, control circuitry 610, and peripheral circuitry 674. The second wafer 672 includes a MIM capacitor (e.g., LOFIC) array 603, column readout circuitry 606, a signal processor 676, and peripheral circuitry 674. In some embodiments, associated switching transistors may also be included on the second wafer 672. The peripheral circuitry 674 may include one or more filter circuits for noise reduction, such as a decoupling capacitor array. Placing the imaging system 600 on two separate wafers allows for LOFIC network expansion and layout flexibility.

[0054] Figure 7 Schematic diagram illustrating one example of a pixel circuit 704 including a lateral overflow integration capacitor (LOFIC) network 750 and a plurality of photodiodes including photodiodes 714 and 764 in accordance with the teachings of the present disclosure. It should be appreciated that Figure 7 The pixel array circuit 704 may be Figure 1An example of one of the pixel circuits 104 included in the pixel array 102 is shown in FIG. 1 , and similarly named and numbered elements described above may be similarly coupled and function below.

[0055] As shown in the depicted example, pixel circuit 704 includes a first photodiode 714 (e.g., a large photodiode LPD) configured to photogenerate image charge in response to incident light. As shown in the depicted example, pixel circuit 704 includes an anti-blooming transistor 768 coupled to first photodiode 714. Pixel circuit 704 also includes a first floating diffusion FD1 718 coupled to receive image charge from first photodiode 714 via a first transfer transistor 716 (e.g., a transfer transistor for large photodiode LPD). In the depicted example, first transfer transistor 716 is coupled to be controlled in response to a first transfer control signal LTX 746 (e.g., a transfer control signal LTX associated with large photodiode LPD) to transfer image charge from first photodiode 714 to first floating diffusion FD1 718, for example, during a readout cycle associated with pixel circuit 704. The source follower transistor 720 has a gate coupled to the first floating diffusion FD1718, and the row select transistor 722 is coupled to the source follower transistor 720, so that the source follower transistor 720 and the row select transistor 722 are coupled between the power supply line AVDD_PIX and the bit line 712 to output an image signal from the pixel circuit 704 in response to the row select control signal RS 748 and the amount of charge at the gate of the source follower transistor 720.

[0056] exist Figure 7In the illustrated example, a dual floating diffusion transistor 724 is coupled between a first floating diffusion FD1 718 and a second floating diffusion FD2 726. In one example, the second floating diffusion FD2 726 can be coupled to one or more capacitors configured to receive excess image charge overflow from the first photodiode 714 via the first transfer transistor 716 and the dual floating diffusion transistor 724. In one example, a reset transistor 732 is coupled between a reset voltage source AVDD_PIX and the second floating diffusion FD2 726. The second floating diffusion FD2 726 is further coupled to a LOFIC transistor 728, which is coupled between the second floating diffusion FD2 726 and a third floating diffusion FD3 730. The third floating diffusion FD3 730 is coupled between the LOFIC transistor 728 and the LOFIC network 750. Dual floating diffusion transistor 724 is coupled to be controlled in response to dual floating diffusion control signal DFD 744 , LOFIC transistor 728 is coupled to be controlled in response to LOFIC transistor control signal LOF 742 , and reset transistor 732 is coupled to be controlled in response to reset control signal RST 740 .

[0057] Pixel circuit 704 further includes a second photodiode 764 (e.g., a small photodiode SPD) configured to photogenerate image charge in response to incident light. A second transfer transistor 766 (e.g., a transfer transistor for small photodiode SPD) is coupled to be controlled in response to a second transfer control signal STX 736 (e.g., a transfer control signal associated with small photodiode SPD) to transfer image charge from second photodiode 764 to second floating diffusion FD2 726, for example, during a readout period associated with pixel circuit 704. The first photodiode 714 and the second photodiode 764 may have different light-sensing characteristics, such as different full well capacities or different light sensitivities, to enable high dynamic range imaging. For example, the first photodiode 714 may have greater sensitivity than the second photodiode 764. In some embodiments, the first photodiode 714 is configured to sense low light, and the second photodiode 764 is configured to sense bright light. In some embodiments, the first photodiode 714 may have a larger photosensing area than the second photodiode 764.

[0058] As shown in the depicted example, pixel circuit 704 also includes a LOFIC network 750 coupled between bias voltage source VCAP 738 and third floating diffusion FD3 730. Thus, it should be appreciated that LOFIC network 750 is selectively coupled to first floating diffusion FD1 718 via LOFIC transistor 728 and dual floating diffusion transistor 724. LOFIC network 750 is configured to receive excess image charge (e.g., under bright light conditions, such as IR or LED light) via overflow gate transistor 760. Overflow gate transistor 760 is coupled to be controlled in response to overflow gate control signal OFG 752 to transfer overflow image charge from second photodiode 764 to LOFIC network 750.

[0059] In the example, LOFIC network 750 includes two or more capacitor switch pairs coupled in parallel. Each capacitor switch pair includes a corresponding LOFIC 754-n and a switching transistor 756-n. Switching transistor 756-n is connected in series to the corresponding LOFIC 754-n between bias voltage source VCAP 738 and third floating diffusion FD3 730. The switching transistors are coupled to be controlled in response to switching control signals SW-1…SW-n 734-1…734-n for controlling the operation of the corresponding LOFIC 754-n. LOFIC network 750 is capable of fully discharging residual charge in LOFICs 754-1…754-n by alternately coupling LOFICs 754-1…754-n to the rest of the pixel circuitry on a frame-by-frame basis via switching transistors 756-1…756-n. In one example, during each frame period of the image sensor, only a single switching transistor (e.g., 756-1) in a capacitor switch pair of LOFIC network 750 is turned on at a time, while all other switching transistors (e.g., 756-2 ... 756-n) are simultaneously turned off. When the image sensor moves to the next frame, a different switching transistor (e.g., 756-2) is turned on, and all other switching transistors, including the switching transistors that were turned on during the previous frame (e.g., 756-1, 756-3 ... 756-n), are simultaneously turned off. LOFICs 754-1 ... 754-n are coupled to the turned-off switching transistors 756-1 ... 756-n, so that the inactive LOFICs (e.g., 754-1 ... 754-n) in LOFIC network 750 are given sufficient time to relax and fully discharge any residual charge before the frame in which their corresponding switching transistors are turned on. Thus, a LOFIC 754-n storing charge from its active frame period has sufficient idle periods to fully relax and discharge before its integration period in the next active frame, thereby reducing any undesirable image lag (eg, visible artifacts on a captured frame).

[0060] In various examples, the number of capacitor switch pairs can depend on the desired frame rate and the time required for the LOFIC to fully discharge (e.g., greater than 10 ms, greater than 100 ms). For example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 30 frames per second (fps) is desired (each frame lasting approximately 33 ms), then the LOFIC network 750 should have at least two capacitor switch pairs. As another example, if the LOFIC takes 30 ms to fully discharge and a frame rate of 60 frames per second (fps) is desired (each frame lasting approximately 17 ms), then the LOFIC network 750 should have at least three capacitor switch pairs. Having more capacitor switch pairs can increase the reduction in image lag, but this should be balanced against the larger size of the semiconductor substrate required to accommodate all elements of the pixel circuit 704.

[0061] In the example, LOFIC 754-n is implemented as a metal-insulator-metal (MIM) capacitor comprising a high-dielectric, or high-k, insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first and second metal electrodes of LOFIC 754-n can be formed from a single layer of high-k material or a stack of multiple layers of high-k material. The exact composition and total thickness of the high-k material can depend on the desired capacitance of the LOFIC. In various examples, the high-k material can include one of aluminum oxide (AhO3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or a combination thereof. LOFICs 754-1…754-n can have substantially the same size, dielectric composition, and / or dielectric thickness.

[0062] In operation, bias voltage source VCAP 738 is configured to provide a bias voltage to LOFIC network 750 during precharge and readout cycles. In one example, bias voltage source VCAP 738 may have a value between 0V and 3.5V. It should be appreciated that, in various examples, the voltage level of bias voltage source VCAP 738 may be determined taking into account the stability range of high-k materials. In this example, during an idle period, reset control signal RST 740 may have a value sufficient to turn on reset transistor 732 (e.g., between 2.5V and 4V), double floating diffusion control signal DFD 744 may have a high voltage value ranging from 2.5V to 4V, LOFIC transistor control signal LOF 742 may have a value of 0V to 4V, and first and second transfer control signals LTX 746 and STX 736 may each have a value of 0V to 3V.

[0063] Figure 8A 、 8B8C and 8C respectively illustrate timing diagrams of the first, second, and nth frame periods of example signal values in an example pixel circuit including a LOFIC network and two photodiodes. According to the teachings of the present disclosure, each frame (i.e., Figure 8A 、 8B and 8C) operate in precharge, integration and readout cycles. It should be understood that Figure 8A 、 8B and the signal depicted in 8C may be Figure 7 Examples of signals for controlling the operation of an example pixel circuit, such as pixel circuit 704, are depicted in , and similarly named and numbered elements described above may be similarly coupled and function below.

[0064] Referring now to the described examples, Figure 8A 、 8B 8C illustrates a row select control signal RS 848, a reset control signal RST 840, a double floating diffusion control signal DFD 844, a LOFIC control signal LOF 842, a first transfer control signal LTX 846, a second transfer control signal STX 836, an overflow gate control signal OFG 852, a bias voltage CAP 838, a first switch control signal SW-1 834-1, a second switch control signal SW-2 834-2, and an nth switch control signal SW-n 834-n, which are configured to control the above-described Figure 7 The corresponding circuit elements are discussed in detail in .

[0065] At time t1, the precharge cycle begins. The reset control signal RST 840 continues to turn on the reset transistor 732, and the dual floating diffusion control signal DFD 844 also continues to turn on the dual floating diffusion transistor 724 from the previous frame. For each frame, one of the switch control signals SW-1...SW-n 834-1...834-n turns on the corresponding switch transistor 756-1...756-n (e.g., Figure 8A , the first switch control signal SW-1 834-1 is turned on), while the remaining switch control signals SW-1 ... SW-n 834-1 ... 834-n are simultaneously turned off (for example, in Figure 8A834-n are turned off). The row select control signal RS 848 turns on the row select transistor 722, and the bias voltage source CAP 838 is turned on. The LOFIC control signal LOF 842 pulses the LOFIC transistor 728, the second transfer control signal STX 836 pulses the second transfer transistor 766, and the first transfer control signal LTX 846 pulses the transfer transistor 716. Near the end of the pre-charge cycle, the row select control signal RS 848 turns off the row select transistor 722, and the bias voltage source capacitor 838 is turned off or decoupled from the LOFIC network 750. At this point during the pre-charge cycle, the first and second photodiodes 714 and 764, the first, second and third floating diffusions FD1 to 3 718, 726, 730 are all reset by the reset transistor 732. Figure 8A 、 8B As depicted in FIG8C , the switch control signal SW-n 834 - n turned on at time t1 remains on until the readout period of the frame period ends.

[0066] In other embodiments, during the precharge cycle, the bias voltage source CAP 838 may remain off, and the overflow gate control signal OFG 825 may turn the overflow gate transistor 760 on and off, as shown in FIG. Figure 8A 、 8B In one example, the overflow gate transistor 760 can be zero biased to provide an overflow path between the second photodiode 764 and the corresponding LOFIC 754-n through the corresponding switch transistor 756-n.

[0067] At time t2, the precharge period ends and the integration (i.e., exposure) period begins. The signals that are active during this period are reset control signal RST 840, dual floating diffusion control signal DFD 844, and the switch control signal SW-n corresponding to the frame. During the integration period, the first and second photodiodes 714 and 764 photogenerate image charge in response to incident light. Pixel circuit 704 is configured so that excess photogenerated charge can overflow from second photodiode 764 through LOFIC transistor 728 to LOFIC network 750 for storage in bright or intense light conditions (e.g., LED light or IR light).

[0068] At time t3, the integration period ends and the readout period begins. Row select control signal RS 848 turns on row select transistor 722, bias voltage source VCAP 838 turns on or couples to apply a bias voltage to LOFIC network 750 for charge readout, and reset control signal RST 840 turns off reset transistor 732.

[0069] Next, a correlated double sampling (CDS) readout of the first photodiode 714 occurs, during which a low conversion gain (LCG) readout occurs from the reset value (R) of the first photodiode 714. Next, the dual floating diffusion control signal DFD 844 turns off the dual floating diffusion transistor 724, and then a high conversion gain (HCG) readout occurs from the reset value (R) of the first photodiode 714. Next, the first transfer control signal LTX 846 pulses the first transfer transistor 716, and then an HCG readout of the signal value (S) occurs based on the charge in the first photodiode 714 and the first floating diffusion FD1 718.

[0070] Next, the dual floating diffusion control signal DFD 844 turns on the dual floating diffusion transistor 724 , and an LCG readout of the signal value (S) occurs based on the charge in the first photodiode 714 , the first floating diffusion FD1 718 , and the second floating diffusion 724 .

[0071] Next, reset control signal RST 840 pulses reset transistor 732, and a second photodiode (SPD) readout of the reset value (R) occurs. Next, second transfer control signal STX 836 pulses second transfer transistor 766, and an SPD readout of the signal value (S) occurs based on the charge in second photodiode 764, first floating diffusion FD1 718, and second floating diffusion 724.

[0072] Next, LOFIC control signal LOF 842 turns on LOFIC transistor 728, and then second transfer control signal STX 836 turns on second transfer transistor 766. Next, LOFIC readout occurs, during which a lateral overflow (LOF) readout of a signal value (S) occurs based on the charge in second photodiode 764, first floating diffusion FD1 718, second floating diffusion 724, and corresponding LOFIC 754-n. Next, reset control signal RST 840 pulses reset transistor 732, LOFIC control signal LOF 842 pulses LOFIC transistor 728 off and back on, and second transfer control signal STX 836 pulses second transfer transistor 766 off and back on. Next, a LOF readout of the reset value (R) occurs. In various examples, the CDS LCG readout may be determined by finding the difference between the LCG signal value (S) and the LCG reset value (R), the CDS HCG readout may be determined by finding the difference between the HCG signal value (S) and the HCG reset value (R), the CDS SPD readout may be determined by finding the difference between the SPD signal value (S) and the SPD reset value (R), and the CDS LOF readout may be determined by finding the difference between the LOF signal value (S) and the LOF reset value (R).

[0073] Afterwards, the reset control signal RST 840 turns on the reset transistor 732 at t4, and all other signals except the double floating diffusion control signal DFD 844 turn off their corresponding transistors. At time t4, for the next frame, the readout cycle ends and the charging cycle begins again. Figure 8A 、 8B 8C, the difference between the frames is which switch control signal SW-n 834-n is turned on. If there are two capacitor switch pairs in the LOFIC network 750, the timing diagram will be Figure 8A and 8B If there are five capacitor switch pairs in the LOFIC network 750, then for the sixth frame, the timing diagram will return to Figure 8A .

[0074] Figure 9 A diagram showing a top-down view of one example of a pixel circuit 904 including a LOFIC network on a substrate and a plurality of photodiodes including two photodiodes is illustrated in accordance with the teachings of the present disclosure. Figure 9 The pixel circuit 904 may be Figure 1 The pixel array 102 shown in FIG. 1 includes a pixel circuit 104 and / or Figure 7923 .

[0075] Figure 9 Other circuit elements shown in the depicted example are represented by dashed lines to show that they are located on different layers on the substrate 962 than the LOFICs 954-1 ... 954-6. These circuit elements include a first photodiode 914, a first transfer transistor 916, a second photodiode 964, a second transfer transistor 966, a first floating diffusion FD1 918, a second floating diffusion FD2 926, a third floating diffusion FD3 930, a double floating diffusion transistor 924, a source follower transistor 920, a row select transistor 922, a reset transistor 932, a LOFIC transistor 928, and a power supply line AVDD. In some embodiments, one or more of these elements may be omitted. In some embodiments, the pixel circuit 904 may include Figure 9 Additional components not shown. Figure 7 and Figure 9 As both illustrate, the third floating diffusion FD3 930 serves as a connection to the LOFIC network.

[0076] Figure 10 A cross section of one example of a pixel circuit 1004 including a LOFIC network 1050 on a substrate 1062 and a plurality of photodiodes including two photodiodes 1014 and 1064 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 10 The pixel circuit 1004 may be Figure 1 The pixel circuit 104 or the pixel circuit 104 included in the pixel array 102 shown in FIG. Figure 7, and similarly named and numbered elements described above may be similarly coupled and function below. As shown in the depicted example, above the first photodiode 1014 (e.g., a large photodiode), the second photodiode 1064 (e.g., a small photodiode), and the substrate 1062 are a gate layer 1005 and a plurality of metal layers, including a first metal layer 1015, a second metal layer 1025, a third metal layer 1035, a fourth metal layer 1045, and a fifth metal layer 1055. In the depicted example, the LOFICs of the LOFIC network 1050 (each LOFIC including a plurality of LOFICs 1054) are disposed in the fourth metal layer 1045. In some embodiments, the LOFICs of the LOFIC network 1050 may be arranged only above and within the photodiode region (e.g., a doped or implanted region) of the first photodiode 1014. In some embodiments, the LOFICs of the LOFIC network 1050 may be disposed over a photodiode region of the first photodiode 1014 and a device transistor region associated with the pixel circuit 1004 .

[0077] exist Figure 10 In the depicted example, pixel circuitry 1004 may include two different interlayer materials: an intermetal dielectric (IMD) 1065 and an interlayer dielectric (ILD) 1067. In various examples, the IMD and ILD have different dielectric constants. Typically, the IMD is used for copper interconnects and includes a high-k material film (e.g., hafnium oxide), while the ILD is used to encapsulate transistor gates and includes an oxide material film with a lower dielectric constant.

[0078] The various embodiments of the LOFIC network described herein can be used with any imaging system that includes MIM capacitors (eg, autosensors).The disclosed LOFIC network helps resolve hysteresis issues associated with imaging systems.

[0079] The above description of the examples illustrated in the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, those skilled in the relevant art will recognize that various modifications are possible within the scope of the present disclosure.

[0080] These modifications may be made to the examples of the present disclosure in light of the above detailed description. The terms used in the appended claims should not be construed to limit the disclosure to the specific examples disclosed in the specification. Rather, the scope of the present disclosure is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A pixel circuit, comprising: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion; a reset transistor coupled between a reset voltage and the floating diffusion; and a plurality of capacitor switch pairs, wherein each of the plurality of capacitor switch pairs is coupled in parallel with each other between the reset transistor and a bias voltage source, wherein each of the plurality of capacitor switch pairs comprises: lateral overflow integration capacitor LOFIC; and A switching transistor is coupled in series between the reset transistor and the LOFIC.

2. The pixel circuit of claim 1 , wherein the switching transistor of a first one of the plurality of capacitor switch pairs is configured to be turned on, and simultaneously the switching transistors of the remaining capacitor switch pairs of the plurality of capacitor switch pairs are configured to be turned off and discharge residual image charge during a first frame period.

3. The pixel circuit of claim 2 , wherein the switching transistor of a second one of the plurality of capacitor switch pairs is configured to be turned on, and simultaneously the switching transistors of the remaining capacitor switch pairs of the plurality of capacitor switch pairs are configured to be turned off and discharge the residual image charge during a second frame period. 4 . The pixel circuit of claim 1 , wherein the plurality of capacitor switch pairs comprises three capacitor switch pairs.

5. The pixel circuit of claim 1 , wherein the floating diffusion is a first floating diffusion, and wherein the pixel circuit further comprises: a second floating diffusion coupled between the first floating diffusion and the reset transistor; a double floating diffusion (DFD) transistor coupled between the first floating diffusion and the second floating diffusion; a third floating diffusion coupled between the second floating diffusion and the reset transistor; and A LOFIC transistor is coupled between the second floating diffusion and the third floating diffusion, wherein the plurality of capacitor switch pairs are coupled between the third floating diffusion and the bias voltage source.

6. The pixel circuit of claim 1 , wherein the pixel circuit is included on a single wafer, and wherein the capacitors of the plurality of capacitor switch pairs are included in an intermetal dielectric (IMD) layer disposed proximate to a semiconductor substrate of the single wafer within a region of the pixel circuit.

7. The pixel circuit of claim 1 , wherein the photodiode, the floating diffusion, the transfer transistor, and the reset transistor are included on a first die, and wherein each capacitor in the plurality of capacitor switch pairs is included on a second die stacked with and coupled to the first die.

8. The pixel circuit of claim 1, wherein the LOFIC of a first one of the plurality of capacitor switch pairs and the LOFIC of a second one of the plurality of capacitor switch pairs are identical in at least one of size, dielectric composition, and dielectric thickness.

9. The pixel circuit of claim 1 , wherein the photodiode is a first photodiode, wherein the transfer transistor is a first transfer transistor, and wherein the pixel circuit further comprises: a second photodiode configured to photogenerate image charge in response to incident light; and A second transfer transistor is coupled between the second photodiode and the floating diffusion, wherein the second transfer transistor is configured to transfer the image charge from the second photodiode to the floating diffusion.

10. The pixel circuit of claim 9, wherein the floating diffusion is a first floating diffusion, and wherein the pixel circuit further comprises: a second floating diffusion coupled between the first floating diffusion and the reset transistor; a double floating diffusion (DFD) transistor coupled between the first floating diffusion and the second floating diffusion; a third floating diffusion; and a LOFIC transistor coupled between the second floating diffusion and the third floating diffusion, wherein the second transfer transistor is coupled between the second floating diffusion and the second photodiode, and Wherein the plurality of capacitor switch pairs are coupled between the third floating diffusion and the bias voltage source. The pixel circuit of claim 9 , wherein the pixel circuit is contained on a single die. 12 . The pixel circuit of claim 11 , wherein the capacitors of the plurality of capacitor switch pairs are included in an intermetal dielectric (IMD) layer disposed proximate to a semiconductor substrate of the single wafer. 13 . The pixel circuit of claim 12 , wherein the semiconductor substrate overlaps a photodiode region associated with the first photodiode, and wherein a photo-sensing area of the first photodiode is larger than a photo-sensing area of the second photodiode.

14. The pixel circuit of claim 9 , wherein the first photodiode, the second photodiode, the floating diffusion, the first transfer transistor, the second transfer transistor, and the reset transistor are included on a first die, and wherein each of the capacitors in the plurality of capacitor switch pairs is included on a second die stacked with and coupled to the first die.

15. The pixel circuit of claim 9 , wherein the switching transistor of a first one of the plurality of capacitor switch pairs is configured to be turned on, and simultaneously the switching transistors of the remaining capacitor switch pairs of the plurality of capacitor switch pairs are configured to be turned off and discharge residual image charge during a first frame period.

16. The pixel circuit of claim 15 , wherein the switching transistor of a second one of the plurality of capacitor switch pairs is configured to be turned on, and simultaneously the switching transistors of the remaining capacitor switch pairs of the plurality of capacitor switch pairs are configured to be turned off and discharge the residual image charge during a second frame period. 17 . The pixel circuit of claim 9 , wherein the plurality of capacitor switch pairs comprises three capacitor switch pairs.

18. The pixel circuit of claim 9, wherein the LOFIC of a first one of the plurality of capacitor switch pairs and the LOFIC of a second one of the plurality of capacitor switch pairs are identical in at least one of size, dielectric composition, and dielectric thickness.

19. A pixel circuit comprising: a photodiode configured to photogenerate image charge in response to incident light; a first floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the first floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the first floating diffusion; a reset transistor coupled between a reset voltage and the first floating diffusion; a second floating diffusion different from the first floating diffusion and coupled between the first floating diffusion and the reset transistor; a double floating diffusion (DFD) transistor coupled between the first floating diffusion and the second floating diffusion; a third floating diffusion coupled between the second floating diffusion and the reset transistor; a lateral overflow integrator capacitor (LOFIC) transistor coupled between the second floating diffusion and the third floating diffusion; as well as a plurality of capacitor switch pairs coupled between the third floating diffusion and a bias voltage source, wherein each of the plurality of capacitor switch pairs comprises— LOFIC, and A switch transistor is coupled in series between the third floating diffusion and the LOFIC.

20. A pixel circuit comprising: a photodiode configured to photogenerate image charge in response to incident light; a first floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the first floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the first floating diffusion; a reset transistor coupled between a reset voltage and the first floating diffusion; a second floating diffusion different from the first floating diffusion and coupled between the first floating diffusion and the reset transistor; a double floating diffusion (DFD) transistor coupled between the first floating diffusion and the second floating diffusion; as well as a plurality of capacitor switch pairs coupled between the second floating diffusion and a bias voltage source, wherein each of the plurality of capacitor switch pairs comprises— LOFIC, and A switch transistor is coupled in series between the second floating diffusion and the LOFIC.

Images