Photovoltaic array bypass diode packaging module and preparation method thereof

Abstract

The present application relates to a photovoltaic array bypass diode packaging module and a preparation method thereof, comprising a first base island and a second base island arranged at intervals on a frame substrate, a control chip and a capacitor arranged on the first base island, and a MOS transistor arranged on the second base island; the MOS transistor is configured as follows: the source is connected to the first end of the control chip via a first wire, the drain is connected to the second end of the control chip via a conductive solder, a copper base island / substrate and a second wire, and the gate is connected to the third end of the control chip via a third wire; wherein the first end of the control chip is connected to the positive electrode of the capacitor, and the second end is connected to the negative electrode of the capacitor, which can at least effectively improve the performance and reliability of the diode packaging module.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a photovoltaic array bypass diode packaging module and a preparation method thereof. Background Art

[0002] With the rapid development of photovoltaic technology, the market has put forward higher requirements on the performance and reliability of photovoltaic arrays. However, in the actual operation of photovoltaic arrays, the non-uniform irradiance caused by shading directly affects the output power of photovoltaic arrays, causing local overheating and hot spot effect, which damages the packaging materials of photovoltaic cells and components.

[0003] In order to prevent hot spots from causing permanent damage to components, bypass diodes are usually connected in reverse parallel to the battery string. Under non-uniform irradiance conditions, the battery string that is most severely shaded will become a load. At this time, the bypass diode will bypass the current flowing through the shaded battery string, thereby effectively reducing the impact of reverse bias voltage on the hot spot battery.

[0004] However, the bypass diode is generally a Schottky diode, which has defects such as large forward voltage drop and severe heat generation, which affects the safety and service life of photovoltaic modules. Summary of the invention

[0005] Based on this, it is necessary to provide a photovoltaic array bypass diode packaging module and a preparation method thereof to address the technical problems in the above-mentioned background technology, which can at least effectively improve the performance and reliability of the diode packaging module.

[0006] According to various embodiments of the present application, the first aspect of the present application provides a diode packaging module, including a first base island, a second base island, a control chip and a capacitor arranged on the first base island, and a MOS transistor arranged on the second base island; the MOS transistor is configured as: the source is connected to the first end of the control chip via a first wire, the drain is connected to the second end of the control chip via conductive solder, the copper base island / substrate and the second wire, and the gate is connected to the third end of the control chip via a third wire; wherein the first end of the control chip is connected to the positive electrode of the capacitor, and the second end is connected to the negative electrode of the capacitor.

[0007] In the diode packaging module in the above embodiment, the control chip and the capacitor are arranged on the first base island, and the MOS transistor is arranged on the second base island. The first base island and the second base island are arranged at intervals to avoid the MOS transistor from heating and baking the control chip and the capacitor, thereby improving the performance and reliability of the control chip and the capacitor. Since the first base island with the control chip and the capacitor is generally used as an anode substrate, and the second base island with the MOS transistor is generally used as a cathode substrate, the isolation channel between the MOS transistor and the control chip can effectively avoid the adverse effects of the extreme high voltage of the MOS transistor drain on the control chip or the capacitor, and effectively reduce the MOS high-current condition. Compared with the related art that uses additional high-voltage insulating glue or insulating gaskets for isolation, this embodiment reduces the voltage resistance specification of the insulating glue, effectively reducing the cost and complexity of the diode packaging module.

[0008] In one embodiment, the first base island includes a first bent portion; the second base island includes a first protruding portion; the first bent portion surrounds the first protruding portion; and the MOS transistor is disposed on a top surface of the first protruding portion.

[0009] In one embodiment, the first bending portion includes a sub-protrusion; wherein the control chip and the capacitor are disposed on the top surface of the sub-protrusion.

[0010] In one embodiment, the first base island and the second base island are arranged at intervals along a first direction; and the control chip and the MOS transistor are arranged at intervals along the first direction.

[0011] In one embodiment, the control chip and the MOS transistor are arranged at intervals along the second direction, and the first direction intersects the second direction.

[0012] In one of the embodiments, the first base island and the second base island can be mounted on the PCB board in the form of SMT component pins; the diode packaging module also includes an epoxy resin plastic packaging body, which together with the first base island and the second base island forms a packaging tube shell, wherein the epoxy resin plastic packaging body is formed by injection molding of epoxy resin molding compound (EMC-Epoxy Molding Compound, EMC); wherein the MOS transistor, the control chip and the capacitor are all located in the packaging tube shell.

[0013] In one embodiment, a gap extending along the second direction is included between the first base island and the second base island.

[0014] In one embodiment, the first base island includes a fixing portion for fixing to the frame substrate, a suspension portion for being suspended above the second base island, and a supporting portion for connecting the fixing portion and the suspension portion; wherein the control chip is arranged on the top surface of the suspension portion.

[0015] According to various embodiments of the present application, a second aspect of the present application provides a photovoltaic array comprising at least two electrically connected battery modules; the battery module comprises a diode package module according to any embodiment of the present application, and a battery string connected in parallel with the diode package module.

[0016] In one embodiment, the battery string includes 36-96 electrically connected battery cells.

[0017] According to various embodiments of the present application, a third aspect of the present application provides a method for preparing a diode packaging module, comprising:

[0018] providing a frame substrate;

[0019] A first base island and a second base island are formed on the frame substrate, wherein the first base island includes a control chip and a capacitor, and the second base island includes a MOS transistor; a first end of the control chip is connected to the positive electrode of the capacitor, and a second end is connected to the negative electrode of the capacitor;

[0020] The control chip is bonded to the MOS transistor, wherein the MOS transistor is configured as follows: the source is connected to the first end of the control chip via a first wire, the drain is connected to the second end of the control chip via a conductive solder, a copper-based island / substrate and a second wire, and the gate is connected to the third end of the control chip via a third wire.

[0021] In the diode packaging module preparation method in the above embodiment, the control chip and the capacitor are arranged on the first base island, and the MOS transistor is arranged on the second base island. The first base island and the second base island are arranged at intervals to avoid the MOS transistor from heating and baking the control chip and the capacitor, thereby improving the performance and reliability of the control chip and the capacitor. Since the first base island with the control chip and the capacitor is generally used as an anode substrate, and the second base island with the MOS transistor is generally used as a cathode substrate, the isolation channel between the MOS transistor and the control chip can effectively avoid the adverse effects of the extreme high voltage of the MOS transistor drain on the control chip or the capacitor. Compared with the related art that uses additional high-voltage insulation glue or insulation gaskets for isolation, this embodiment reduces the voltage resistance specification of the insulation glue, effectively reducing the cost and complexity of the diode packaging module. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying any creative work.

[0023] FIG1 is a schematic diagram of a top view of a diode packaging module provided in a first embodiment of the present application;

[0024] FIG2 is a schematic diagram of a circuit principle of a diode packaging module provided in an embodiment of the present application;

[0025] FIG3 is a schematic diagram of a top view structure of a diode packaging module provided in a second embodiment of the present application;

[0026] FIG4 is a schematic diagram of a top view structure of a diode packaging module provided in a third embodiment of the present application;

[0027] FIG5 is a schematic diagram of a top view structure of a diode packaging module provided in a fourth embodiment of the present application;

[0028] FIG6 is a schematic diagram of a top view structure of a diode packaging module provided in a fifth embodiment of the present application;

[0029] FIG7 is a schematic diagram of a top view of a diode packaging module provided in a sixth embodiment of the present application;

[0030] FIG8 is a schematic diagram of a longitudinal cross-sectional view of a diode packaging module provided in one embodiment of the present application;

[0031] FIG9 is a schematic diagram of a top view structure of a Schottky diode used in an embodiment of the present application;

[0032] FIG10 is a schematic diagram of a top view of a photovoltaic array in an embodiment of the present application;

[0033] FIG. 11 is a schematic diagram of a flow chart of a method for preparing a diode packaging module provided in an embodiment of the present application.

[0034] Description of reference numerals:

[0035] 10. Frame substrate; 11. First base island; 12. Second base island; 13. Control chip; C1. Capacitor; 15. MOS transistor; 151. First wire; 152. Second wire; 153. Third wire; 111. First bending portion; 121. First protrusion; 1111. Sub-protrusion; 16. Glue locking hole; 17. Bonding wire; 101. PCB board; 102. Epoxy resin plastic package; 20. Gap; 1101. Fixing portion; 1102. Suspension portion; 1103. Supporting portion; 200. Battery module; 201. Diode package module; 202. Battery string; 300. Silver-plated area; 400. Shielding area; 203. Positive terminal; 204. Negative terminal. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0038] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0039] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0040] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0041] Please refer to Figures 1-2. In some embodiments, a diode packaging module 201 is provided, including a first base island 11 and a second base island 12, which are spaced apart on a frame substrate (not shown), a control chip 13 and a capacitor C1 arranged on the first base island 11, and a MOS transistor 15 arranged on the second base island 12; the MOS transistor 15 is configured as follows: the source is connected to the first end of the control chip 13 via a first wire 151, the drain is connected to the second end of the control chip 13 via a conductive solder, a copper base island / substrate (not shown) and a second wire 152, and the gate is connected to the third end of the control chip 13 via a third wire 153; wherein the first end of the control chip 13 is connected to the positive electrode of the capacitor C1, and the second end is connected to the negative electrode of the capacitor C1.

[0042] Please continue to refer to Figures 1-2. By setting the control chip 13 and the capacitor C1 on the first base island 11, and setting the MOS transistor 15 on the second base island 12, the first base island 11 and the second base island 12 are spaced apart to avoid the MOS transistor 15 from heating and baking the control chip 13 and the capacitor C1, thereby improving the working performance and reliability of the control chip 13 and the capacitor C1; since the first base island 11 on which the control chip 13 and the capacitor C1 are provided is generally used as an anode substrate, and the second base island 12 on which the MOS transistor 15 is provided is generally used as a cathode substrate, the isolation channel between the MOS transistor 15 and the control chip 13 can effectively avoid the adverse effects of the high voltage at the drain end of the MOS transistor 15 on the control chip 13 or the capacitor C1; compared with the use of an additional high-voltage insulating glue or insulating gasket for isolation in the related art, this embodiment reduces the voltage-resistant specification of the insulating glue, and effectively reduces the cost and complexity of the diode packaging module 201.

[0043] As an example, please continue to refer to Figure 2, where a MOS transistor 15 is provided and sealed with a control chip 13 and a capacitor C1. When the MOS transistor 15 is turned on, the terminal voltage of the diode can be pumped up to a suitable driving voltage using an internal charge pump and stored in the capacitor C1. When the terminal voltage of the capacitor C1 reaches the target voltage, the MOS transistor 15 is driven to be turned on, and the channel of the MOS transistor 15 is conductive, thereby obtaining the forward conduction characteristic of an ideal diode. The forward loss of an ideal diode is one order of magnitude lower than that of a Schottky diode under the same working conditions, and the reverse leakage is two orders of magnitude lower than that of a Schottky diode under the same working conditions. Therefore, a diode package module can be used to replace a Schottky diode.

[0044] Please refer to FIG3. In some embodiments, if the control chip 13 and the capacitor C1 are both arranged on the second base island 12, that is, the control chip 13, the capacitor C1 and the MOS transistor 15 are all arranged on the same base island, since the drain of the control chip 13 is connected to the second end of the control chip 13 via the conductive solder, the copper base island / substrate and the second wire 152, the drain of the MOS transistor 15 may be subjected to a higher voltage, and it is necessary to add an insulating glue or insulating gasket with sufficient withstand voltage between the drain of the MOS transistor 15 and the control chip 13 and the capacitor C1 to achieve high-voltage isolation. On the other hand, the MOS transistor 15 generates a large amount of heat and has a high temperature rise, and the MOS transistor 15 will bake the control chip 13 and the capacitor C1. However, the control chip 13 and the capacitor C1 are highly sensitive to temperature, and the performance of the control chip 13 and the capacitor C1 may significantly decrease with the increase in temperature; if the MOS transistor 15 causes the surrounding temperature to continue to rise, it is easy to cause the driving duty cycle of the MOS transistor 15 to continue to decrease, which seriously affects the performance and reliability of the MOS transistor 15, the control chip 13 and the capacitor C1.

[0045] According to the bypass diode test regulations in IEC61215, the rated current of the junction box must meet the requirement of being greater than 1.25 times Isc (maximum current of the monofacial component / short-circuit current). If applied to bifacial components, the bifacial gain factor of 30% specified in UL1703 must also be considered, so the theoretical maximum current of the junction box for bifacial components is equal to IscX1.25X1.3. Therefore, using the 18.36A short-circuit current of the G12 bifacial component, the maximum theoretical current of the junction box is equal to 29.84A, and a junction box with a rated current of 30A needs to be selected. The maximum theoretical current of the M10 bifacial component is 22.5A based on the short-circuit current, and a junction box with a rated current of 25A needs to be selected, as shown in Table 1.

[0046] Please continue to refer to Table 1. It can be clearly seen that the safety margin left by the 30A junction box is only 0.5%, which means that the subsequent use of other means (such as battery efficiency improvement, new component efficiency improvement technology) to increase the component current is restricted, and the reliability is at risk if there is a slight fluctuation. If the current conventional 10% safety margin design is considered, it is even necessary to develop a junction box above 33A. For M10 components, the safety margin of its junction box needs to reach 10%, which reserves sufficient space for the subsequent application of new technologies. It is a scientific consideration that takes into account both reliability and long-term development.

[0047] Table 1

[0048]

[0049] However, if the design is based on the aforementioned photovoltaic junction box industry standard and the diode packaging module shown in Figure 3 is used, for the M10 component and the G12 component, it is necessary to use junction boxes with a rated current of 25A and 30A, respectively, which still cannot meet the requirement of a 10% safety margin. Compared with the embodiment in Figure 3, the M10 component and the G12 component of the embodiment in Figure 1 of the present application have corresponding junction box rated currents of 30A and 35A, respectively, that is, the through-current specifications are directly improved by one level. Under the condition of the same through-current, since the IC maintains a high duty cycle, the measured temperature of the package shell in the embodiment in Figure 1 drops by more than 25°C compared to the implementation scheme in Figure 3. Therefore, under the same working conditions, the embodiment of the present application effectively reduces the temperature of the package shell while improving the through-current capacity of the product, producing unexpected technical effects.

[0050] Please continue to refer to Figures 1-2. The control chip 13 and the capacitor C1 are arranged on the first base island 11, and the MOS transistor 15 is arranged on the second base island 12. The spacing between the first base island 11 and the second base island 12 physically isolates the control chip 13, the capacitor C1 and the MOS transistor 15, effectively preventing the MOS transistor 15 from heating and baking the control chip 13 and the capacitor C1, thereby improving the working performance and reliability of the control chip 13 and the capacitor C1. Since the first base island 11 on which the control chip 13 and the capacitor C1 are arranged is generally used as an anode substrate, and the second base island 12 on which the MOS transistor 15 is arranged is generally used as a cathode substrate, the isolation channel between the MOS transistor 15 and the control chip 13 can effectively avoid the adverse effects of the high voltage at the drain end of the MOS transistor 15 on the control chip 13 or the capacitor C1. It avoids the cost increase problem caused by the additional addition of insulating glue or insulating gaskets, and effectively reduces the cost and complexity of the diode packaging module 201.

[0051] For example, please continue to refer to Figures 1-2, the second base island 12 includes a silver-plated area 300, and the drain of the MOS transistor 15 can be connected to the silver-plated area 300 via the conductive solder, the copper base island / substrate and the second wire 152, so that the drain of the MOS transistor 15 is connected to the second end of the control chip 13 via the silver-plated area 300, reducing the complexity of wiring in the diode packaging module 201. For example, in one embodiment of the present application, the diameter of the wire can be 0.020 mm (0.8 mil)-0.0254 mm (1 mil).

[0052] For example, please continue to refer to FIG. 1-FIG . 2 , the chip select pin of the MOS transistor 15 can be electrically connected to the corresponding chip select pin on the first base island 11 by using the bonding wire 17 to achieve electrical connection between the MOS transistor 15 and the power supply on the first base island 11 .

[0053] By way of example, the bonding wire may be a copper wire, and the conductive metal in the wire may be copper.

[0054] By way of example, the bonding wire may be a gold wire / palladium gold wire, and the conductive metal in the wire may be gold / palladium gold.

[0055] For example, please continue to refer to Figures 1-2. After the epoxy resin plastic package 102 is formed at the position indicated by the dotted box, the epoxy resin plastic package 102 can be fixed using the glue locking hole 16 to ensure the stability of the connection between the epoxy resin plastic package 102 and the substrate.

[0056] Please refer to FIG. 4-FIG. 5. In some embodiments, the first base island 11 includes a first bending portion 111; the second base island 12 includes a first protruding portion 121; the first bending portion 111 surrounds the first protruding portion 121; wherein the MOS transistor 15 is disposed on the top surface of the first protruding portion 121. The shape and size of the first base island 11 and the shape and size of the second base island 12 can be adjusted according to the requirements of the actual application scenario to meet the specific requirements of circuit wiring.

[0057] Please continue to refer to Figure 4. In some embodiments, the first base island 11 and the second base island 12 are arranged at intervals along a first direction (such as the ox direction); the control chip 13 and the MOS transistor 15 are arranged at intervals along a second direction (such as the oy direction), and the first direction intersects the second direction.

[0058] Please continue to refer to FIG5. In some embodiments, the first bent portion 111 includes a sub-protrusion 1111, wherein the control chip 13 and the capacitor C1 are disposed on the top surface of the sub-protrusion 1111. By increasing the effective patch area of ​​the first base island 11 on the anode side and appropriately adjusting the substrate shape, the patch solution can be optimized to the greatest extent and the package parasitic parameters can be reduced.

[0059] Please continue to refer to Figure 5. In some embodiments, the first base island 11 and the second base island 12 are arranged at intervals along the first direction (for example, the ox direction); the control chip 13 and the MOS transistor 15 are arranged at intervals along the first direction to reduce the cost and complexity of wiring, and improve the integration between the control chip 13, the MOS transistor 15 and the capacitor C1, thereby reducing the volume of the product.

[0060] Please note that FIGS. 4 and 5 only illustrate the shapes and relative positions of the first base island 11 and the second base island 12. In actual applications, the shapes and sizes of the first base island 11 and the second base island 12 can be set according to the actual shapes of the control chip 13 and the MOS transistor 15, the positions of the pads, and the needs of wiring.

[0061] For example, please continue to refer to FIG. 5 , after the insulating shell is formed at the position indicated by the dotted line frame, the insulating shell can be fixed by using the glue locking hole 16 to ensure the stability of the connection between the insulating shell and the substrate.

[0062] Please refer to FIG6. In some embodiments, for an ideal diode using a DFN package or a sTOLL package, the arrangement shown in FIG6 may be adopted. The first base island 11 may be a DFN frame anode substrate, and the second base island 12 may be a DFN frame cathode substrate. The DFN / QFN package is a surface mount package technology. The mounting pad, solder mask and template style design of the printed circuit board (PCB) and the assembly process allow one or more semiconductor devices to be connected in a lead-free package to ensure the flexibility of the package. The sTOLL package may be a leadless package, which can reduce the physical size and overall BOM cost of the terminal product.

[0063] Please refer to Figures 7-8. In some embodiments of transistor outline (TO) packaging, the first base island 11 is set in the form of a three-dimensional conductive frame, so that part of the first base island 11 is mounted on the PCB board and part of it is suspended, which can at least increase the area of ​​the conductive patch without increasing the volume of the packaging module. The first base island 11 and the second base island 12 can be mounted on the printed circuit board (Printed circuitboard, PCB) board 101 in the form of surface mount technology (Surface Mount Technology, SMT) component pins; the diode packaging module 201 also includes an epoxy resin plastic packaging body 102, and the epoxy resin plastic packaging body 102 and the first base island 11 and the second base island 12 together form a complete packaging shell; wherein the MOS transistor 15, the control chip 13 and the capacitor C1 are all located in the packaging shell. The epoxy resin plastic packaging body 102 can prevent external dust or dust and other pollutants from entering the interior of the packaging shell, effectively protect the MOS transistor 15, the control chip 13 and the capacitor C1, and prevent them from being contaminated or oxidized, thereby improving the working reliability of the components.

[0064] Please continue to refer to FIG. 8 . In some embodiments, the first base island 11 and the second base island 12 include a gap 20 extending along the second direction. The first base island 11 includes a fixed portion 1101 mounted on the PCB board 101, a suspension portion 1102 for suspending above the PCB board 101, and a support portion 1103 for connecting the fixed portion 1101 and the suspension portion 1102; wherein the control chip 13 is disposed on the top surface of the suspension portion 1102. The volume of the diode package module can be minimized while increasing the area of ​​the conductive patch.

[0065] For example, please continue to refer to Fig. 8, the materials of the fixing part 1101, the suspension part 1102 and the support part 1103 can be selected from copper, iron, magnesium, etc. and alloys thereof. The epoxy resin plastic package 102 can be a cavity airtight tube shell.

[0066] 8 , in some embodiments, the MOS transistor 15 can be bonded to the top surface of the second base island 12 via conductive adhesive, and the control chip 13 can be bonded to the top surface of the suspension portion 1102 via insulating adhesive. The conductive adhesive is, for example, conductive silver paste or solder.

[0067] Please continue to refer to FIG. 8. In some embodiments, the PCB board 101 may include a bottom conductive layer 120, an insulating layer 130 and a top conductive layer 110 stacked in sequence along a direction perpendicular to the top surface of the first base island 11, such as the oz direction. The bottom conductive layer 120 or the top conductive layer 110 may be a copper layer or other metal conductive layer. The insulating layer 130 may be an epoxy board (FR4) insulating layer.

[0068] For example, please continue to refer to Figure 8. The MOS transistor 15 is the main heat source. Considering that the thermal conductivity of the top conductive layer 110 and the epoxy resin plastic package 102 of the plastic package material differs by at least two orders of magnitude, in actual work, only a small part of the heat is conducted along the path on one side of the control chip 13. After the chip is mounted on the PCB board 101, the second base island 12 below the MOS transistor 15 and the first base island 11 on the side of the control chip 13 are respectively welded on the unconnected copper layer on the PCB, and the heat conduction cannot be carried out well, so the temperature of the control chip 13 and the capacitor C1 drops significantly. In addition, the physical isolation channel between the MOS transistor 15 and the control chip 13 can effectively avoid the adverse effects of the extreme high voltage of the drain of the MOS transistor 15 on the control chip 13 or the capacitor C1; compared with the use of an additional high-voltage insulating glue or insulating gasket for isolation in the related art, this embodiment reduces the voltage withstand specification of the insulating glue, effectively reducing the cost and complexity of the diode packaging module.

[0069] Please refer to Figure 9. In some embodiments, if a Schottky diode D1 is directly used to replace the diode packaging module in the aforementioned embodiment of the present application, under the same working conditions, the forward loss of the Schottky diode is one order of magnitude higher than that of the ideal diode in the aforementioned embodiment of the present application, and the reverse leakage is two orders of magnitude higher than that of the ideal diode in the aforementioned embodiment of the present application; and, the higher the temperature, the better the performance improvement of the ideal diode in the aforementioned embodiment of the present application.

[0070] For example, please continue to refer to FIG. 9 , after the insulating shell is formed at the position indicated by the dotted box by using a plastic encapsulation process, the insulating shell can be fixed by using the glue locking holes 16 to ensure the stability of the connection between the insulating shell and the substrate.

[0071] Please refer to Figure 10. In some embodiments, a photovoltaic array is provided, including at least two electrically connected battery modules 200; the battery module 200 includes a diode package module 201 described in any embodiment of the present application, and a battery string 202 connected in parallel with the diode package module 201.

[0072] For example, the battery string includes 36-96 electrically connected battery cells. For example, the battery string may include 36, 48, 60, 72, or 96 battery cells connected in series or in parallel.

[0073] Please continue to refer to Figure 10. In some embodiments, the positive terminal 203 is used as a forward voltage input / output port, and the negative terminal 204 is used as a negative voltage input / output port. If a shielding area 400 appears in the battery string 202 of a battery module 200 in the photovoltaic array, the non-uniform irradiance caused by the shielding directly affects the output power of the photovoltaic array. At the same time, due to local overheating, a hot spot effect will occur, which may cause damage to the packaging materials of the batteries and components in the photovoltaic array. Since the diode packaging module in the aforementioned embodiment of the present application is used as a bypass diode, the bypass diode is reversely connected in parallel to the battery string. In the case of non-uniform irradiance, the battery string that is most severely shielded will become a load. At this time, the bypass diode will bypass the current flowing through the shielded battery string, which will effectively reduce the impact of the reverse bias voltage on the hot spot battery.

[0074] Referring to FIG. 11 , in some embodiments, a method for preparing a diode packaging module is provided, comprising the following steps:

[0075] Step S602: providing a frame substrate;

[0076] Step S604: forming a first base island and a second base island spaced apart from each other on the frame substrate, wherein the first base island includes a control chip and a capacitor, and the second base island includes a MOS transistor; the first end of the control chip is connected to the positive electrode of the capacitor, and the second end is connected to the negative electrode of the capacitor;

[0077] Step S606: Bond the control chip to the MOS transistor, wherein the MOS transistor is configured as follows: the source is connected to the first end of the control chip via a first wire, the drain is connected to the second end of the control chip via a conductive solder, a copper-based island / substrate and a second wire, and the gate is connected to the third end of the control chip via a third wire.

[0078] Specifically, in the diode packaging module preparation method in the above-mentioned embodiment, by setting the control chip and the capacitor on the first base island, and setting the MOS transistor on the second base island, the first base island and the second base island are spaced apart to avoid the MOS transistor from heating and baking the control chip and the capacitor, thereby improving the performance and reliability of the control chip and the capacitor; since the first base island with the control chip and the capacitor is generally used as the anode substrate, and the second base island with the MOS transistor is generally used as the cathode substrate, the isolation channel between the MOS transistor and the control chip can effectively avoid the adverse effects of the extreme high voltage of the MOS transistor drain on the control chip or the capacitor; compared with the related art that uses additional high-voltage insulating glue or insulating gaskets for isolation, this embodiment reduces the voltage resistance specification of the insulating glue, effectively reducing the cost and complexity of the diode packaging module.

[0079] For example, in the preparation of the diode package module shown in FIG. 1, the prepared control chip 13 and capacitor C1 can be fixed on the first base island 11 through the die bonding process, and the MOS transistor 15 can be fixed on the second base island 12 through the die bonding process. The die bonding process is at room temperature, and no heating or protective gas is required. However, after the die bonding is completed, baking is required, and the baking temperature is 175±5°C, and the baking time is 2 hours. At the same time, vacuum is drawn and nitrogen protection is added. The area of ​​the PCB or DOB board can be effectively reduced, and the patch process is correspondingly reduced, thereby achieving the purpose of reducing material and labor costs.

[0080] For example, in some embodiments, a plastic encapsulation process is used to prepare a diode package module. In the plastic encapsulation process, the mold surface temperature is controlled at 175±10°C, the preheating table surface temperature is controlled at 160±10°C, the mold clamping pressure is controlled at 9MPa-16MPa, the injection pressure is controlled at 5MPa-8MPa, the actual injection time is controlled at 10s-15s, and the curing time is controlled at 110s / mold-120s / mold. After the electroplating process, rib cutting process and finished product testing process are respectively passed, the preparation of the finished diode package module is realized, and finally the manufactured diode package module is put into storage.

[0081] For example, in some embodiments, the manufactured chip is welded to the frame through eutectic or dielectric welding, which is a chip bonding process. The chip bonding process is at room temperature and does not require heating or protective gas. However, after the chip bonding is completed, baking is required. The baking temperature is 175±5°C and the baking time is 2 hours. At the same time, vacuum is drawn and nitrogen protection is added. After baking, the second semi-finished product is obtained.

[0082] For example, in some embodiments, a bonding wire is used to connect the corresponding electrode window in the chip with the corresponding functional pin of the frame, i.e., a bonding process. The bonding process is used to electrically connect the chip select pin of the MOS transistor with the chip select pin on the first base island, thereby realizing electrical connection between the MOS transistor and the power supply on the first base island.

[0083] For example, in some embodiments, the diode packaging module is sealed by an insulating shell to prevent external dust, exhaust gas or water vapor from having adverse effects on circuit elements in the diode packaging module, and to avoid the larger product volume due to the introduction of the insulating shell, which can effectively improve the stability and service life of the product.

[0084] For example, in some embodiments, in the process of forming an insulating shell on the outside of the diode package module by a plastic encapsulation process, the mold surface temperature is controlled at 175±10°C, the temperature of the preheating table surface is controlled at 160±10°C, the mold closing pressure is controlled at 9MPa-16MPa, the injection pressure is controlled at 5MPa-8MPa, the actual injection time is controlled at 10s-15s, and the curing time is controlled at 110s / mold-120s / mold. After electroplating, rib cutting and finished product testing, the finished product is put into storage.

[0085] The specific limitations on the method for preparing the diode package module in the above embodiment can be found in the above limitations on the diode package module, which will not be repeated here.

[0086] It should be understood that, although the various steps in the flowchart of Figure 11 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a portion of the steps in Figure 11 may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0087] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory.

[0088] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0089] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0090] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A diode packaging module, characterized in that: It includes a first base island and a second base island which are spaced apart on a frame substrate, a control chip and a capacitor which are arranged on the first base island, and a MOS transistor which is arranged on the second base island; The MOS transistor is configured as follows: a source electrode is connected to a first terminal of the control chip via a first wire, a drain electrode is connected to a second terminal of the control chip via a conductive solder, a copper-based island / substrate and a second wire, and a gate electrode is connected to a third terminal of the control chip via a third wire, and is used to turn on the channel of the MOS transistor when the terminal voltage of the internal diode is pumped up and the terminal voltage of the capacitor reaches a target voltage; Wherein, a first end of the control chip is connected to the positive electrode of the capacitor, and a second end of the control chip is connected to the negative electrode of the capacitor.

2. The diode packaging module according to claim 1, characterized in that: The first base island includes a first bending portion; The second base island includes a first protrusion; The first bent portion surrounds the first protruding portion; Wherein, the MOS transistor is arranged on the top surface of the first protrusion.

3. The diode packaging module according to claim 2, characterized in that: The first bending portion includes a sub-protrusion; Wherein, the control chip and the capacitor are arranged on the top surface of the sub-protrusion.

4. The diode packaging module according to claim 2, characterized in that: The first base island and the second base island are arranged at intervals along a first direction; The control chip and the MOS transistor are arranged at intervals along the first direction; or the control chip and the MOS transistor are arranged at intervals along the second direction, and the first direction intersects with the second direction.

5. The diode packaging module according to any one of claims 1 to 4, characterized in that: The first base island and the second base island are both mounted on the PCB board in the form of SMT component pins; The diode packaging module also includes: An epoxy resin plastic package body, which together with the first base island and the second base island forms a package tube shell, wherein the epoxy resin plastic package body is formed by injection molding of epoxy resin molding material; Wherein, the MOS transistor, the control chip and the capacitor are all located in the packaging shell.

6. The diode packaging module according to claim 1, characterized in that: A gap extending along a second direction is provided between the first base island and the second base island.

7. The diode packaging module according to claim 1, characterized in that: The first base island includes a fixing portion fixed to the frame substrate, a suspension portion for being suspended above the second base island, and a supporting portion for connecting the fixing portion and the suspension portion; Wherein, the control chip is arranged on the top surface of the suspension part.

8. A photovoltaic array, characterized in that: comprising at least two battery modules electrically connected; The battery module comprises the diode package module according to any one of claims 1 to 7, and a battery string connected in parallel with the diode package module.

9. The photovoltaic array according to claim 8, characterized in that: The battery string includes 36-96 electrically connected battery cells.

10. A method for preparing a diode packaging module, characterized in that: include: providing a frame substrate; A first base island and a second base island are formed on the frame substrate, wherein the first base island includes a control chip and a capacitor, and the second base island includes a MOS transistor; a first end of the control chip is connected to the positive electrode of the capacitor, and a second end is connected to the negative electrode of the capacitor; The control chip is bonded to the MOS transistor, wherein the MOS transistor is configured as follows: a source is connected to a first end of the control chip via a first wire, a drain is connected to a second end of the control chip via a conductive solder, a copper-based island / substrate and a second wire, and a gate is connected to a third end of the control chip via a third wire, for turning on the channel of the MOS transistor when the terminal voltage of the internal diode is pumped up and the terminal voltage of the capacitor reaches a target voltage.

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