A variable threshold temperature switch circuit

Abstract

The application discloses a variable threshold temperature switch circuit, and belongs to the field of integrated circuits, comprising a bandgap reference bias module, a PTAT voltage generation module, a CTAT voltage generation module and a comparator; the bandgap reference bias module is designed based on a bandgap reference source model, combines a common source and common gate structure, realizes a PTAT bias current with a positive temperature change of a high power supply rejection ratio, and provides bias for other modules; the PTAT voltage generation module is provided with a PTAT bias current by the bandgap reference bias module, generates a PTAT voltage with a positive temperature change; the CTAT voltage generation module generates a CTAT voltage with a negative temperature change due to the negative temperature characteristic of a diode voltage V BE ; and the comparator is provided with bias by the bandgap reference bias module, adopts a two-stage structure, and outputs a result after shaping.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit technology, in particular to a variable threshold temperature switch circuit. BACKGROUND

[0002] Traditional temperature detection is mostly based on thermistors, but using thermistors leads to problems such as large structure size, complex system structure, high manufacturing cost, narrow application temperature range, etc. Different from traditional thermistors, integrated chips are used, which can effectively reduce external interference and improve measurement accuracy, and the temperature range can be extended to -55℃ to 125℃.

[0003] The temperature switch module can be used as a chip alone to provide temperature early warning, and can also be used as an important component in a high-performance chip to provide early warning for the entire circuit, and is widely used in a series of high-performance digital and analog integrated circuits such as ADC, DAC and LDO. SUMMARY

[0004] The purpose of the present application is to provide a variable threshold temperature switch circuit to solve the problems in the background art.

[0005] To solve the above technical problems, the present application provides a variable threshold temperature switch circuit, comprising a bandgap reference biasing module, a PTAT voltage generating module, a CTAT voltage generating module and a comparator.

[0006] The bandgap reference biasing module is designed based on a bandgap reference source model and combines a common-source common-gate structure to realize a PTAT biasing current with a positive temperature change and provide biasing for other modules.

[0007] The PTAT voltage generating module is provided with a PTAT biasing current by the bandgap reference biasing module to generate a PTAT voltage with a positive temperature change.

[0008] The CTAT voltage generating module generates a CTAT voltage with a negative temperature change due to the negative temperature characteristic of a diode voltage V BE .

[0009] The comparator is provided with biasing by the bandgap reference biasing module, adopts a two-stage structure and outputs a result after shaping.

[0010] In one embodiment, the bandgap reference biasing module connects the bases of a pair of transistors with a certain ratio of emitter area, connects the collectors to the input ports of an operational amplifier respectively, and connects the emitter of the transistor with larger emitter area to a small resistor.

[0011] The current mirror in the bandgap reference bias module adopts a common-source common-gate structure, and the PSRR of the bias current generation circuit is improved by using the common-source common-gate current mirror.

[0012] In an embodiment, the bandgap reference bias module comprises PMOS tubes M1, M2, M5-M9, M12-M14, NMOS tubes M3, M4, M10, M11, a resistor R1, transistors Q1, Q2, and an amplifier A0.

[0013] The source terminals of the PMOS tubes M1, M5, M8, M9, M12, and M14 are interconnected, the gate terminal and the drain terminal of the PMOS tube M1 are connected to the source terminal of the PMOS tube M2, the gate terminal and the drain terminal of the PMOS tube M2 are connected to the gate terminal of the NMOS tube M4 and the drain terminal of the NMOS tube M3, and the source terminals of the NMOS tubes M3, M4, M10, and M11 are interconnected.

[0014] The drain terminal of the NMOS tube M4 is connected to the gate terminal of the PMOS tube M5, the gate terminal of the PMOS tube M8, and the gate terminal of the PMOS tube M9, the drain terminal of the PMOS tube M5 is connected to the source terminal of the PMOS tube M6, the gate terminal of the PMOS tube M6 is connected to the gate terminal of the PMOS tube M7 and the gate terminal of the PMOS tube M12, the drain terminal of the PMOS tube M6 is connected to the positive input terminal of the amplifier A0 and the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to the emitter of the transistor Q1, the base of the transistor Q1 is connected to the base of the transistor Q2, and the collector of the transistor Q1 is connected to the collector of the transistor Q2.

[0015] The drain terminal of the PMOS tube M8 is connected to the source terminal of the PMOS tube M7, the drain terminal of the PMOS tube M7 is connected to the negative input terminal of the amplifier A0 and the emitter of the transistor Q2, the gate terminal of the PMOS tube M9 is connected to the output terminal of the amplifier A0 and the gate terminal of the PMOS tube M14, the drain terminal of the PMOS tube M9 is connected to the drain terminal of the NMOS tube M10 and the gate terminal of the NMOS tube M3, the drain terminal of the NMOS tube M10 is connected to the gate terminal of the NMOS tube M11 and the gate terminal of the NMOS tube M11.

[0016] The gate terminal of the PMOS tube M12 is connected to the gate terminal of the PMOS tube M13 and the gate terminal of the PMOS tube M7, the drain terminal of the PMOS tube M12 is connected to the drain terminal of the NMOS tube M11, the drain terminal of the PMOS tube M14 is connected to the source terminal of the PMOS tube M13, and the drain terminal of the PMOS tube M13 is connected to the ground.

[0017] In an embodiment, the PTAT voltage generation module utilizes the base-emitter junction voltage difference ΔV BE A PTAT physical quantity with a positive temperature coefficient is constructed, and I PTAT is provided by the bandgap reference bias module through the common-source common-gate current mirror. iGenerating PTAT voltage: V PTAT = (R + r i ) * I PTAT , by adjusting the fuse to produce different output voltage, fuse output through the decoder decoding, control and resistance r i connected to the corresponding switch conduction, modify the resistance r i value, change the PTAT voltage value V PTAT , to change the temperature switch rollover temperature.

[0018] In an embodiment, the PTAT voltage generating module includes PMOS M13, PMOS M14, resistance R and N-bit fuse;

[0019] The source of PMOS M13 is connected to the positive power supply, the gate of PMOS M13 and M14 is connected to the reference source output, the drain of PMOS M13 is connected to the source of PMOS M14, and the drain of PMOS M14 is connected to the N-bit fuse through the resistance R; the N-bit fuse is decoded by the decoder, and the 2 N bit switch is controlled, and the rollover temperature of the variable threshold temperature switch is changed to 2 N bit according to the adjustment of the fuse.

[0020] In an embodiment, the CTAT voltage generating module utilizes the base-emitter junction voltage V BE of the bipolar transistor itself having a negative temperature coefficient temperature characteristic, and provides I PTAT current from the bandgap reference biasing module through the common source and common gate current mirror, thereby generating a base-emitter junction voltage V F which is almost not affected by β BE .

[0021] In an embodiment, the CTAT voltage generating module includes PMOS M15, PMOS M16 and transistor Q3;

[0022] The source of PMOS M15 is connected to the positive power supply, the gate of PMOS M15 and M16 is connected to the reference source output, the drain of PMOS M15 is connected to the source of PMOS M16, and the drain of PMOS M16 is connected to the emitter of transistor Q3, and the base and collector of transistor Q3 are commonly connected to ground.

[0023] In an embodiment, the comparator is a two-stage open-loop structure, the input stage adopts a PMOS differential input pair; the second stage circuit is a single NMOS tube, which converts the differential input to a single output and forms a push-pull structure with the input stage; and the output stage is a two-stage inverter, the inverter area gradually increases, the output waveform is shaped, and the driving capability of the circuit is increased to drive a larger capacitive load.

[0024] In one embodiment, the comparator comprises PMOS M17, PMOS M18, NMOS M19, NMOS M20, PMOS M21, PMOS M22, NMOS M23, NMOS M24, PMOS M25, PMOS M26, PMOS M27, NMOS M28, inverters INV1 and INV2;

[0025] The gate of PMOS M17 and M18 is connected to the reference source output, the gate of PMOS M22 is connected to the PTAT voltage generating module output V PTAT , the gate of PMOS M25 is connected to the CTAT voltage generating module output V CTAT ; the source of PMOS M17, PMOS M21, PMOS M26 and PMOS M27 is interconnected, the drain of PMOS M17 is connected to the source of PMOS M18, and the drain of PMOS M18 is connected to the drain of NMOS M19; the gate of NMOS M19 is connected to its drain.

[0026] The gate of PMOS M21 is connected to its drain and the gate of PMOS M26, the drain of PMOS M21 is connected to the drain of NMOS M20, and the gate of NMOS M20 is connected to the gate of NMOS M19.

[0027] The gate of PMOS M26 is connected to the gate of PMOS M27, the drain of PMOS M26 is connected to the source of PMOS M22 and the source of PMOS M25; the drain and gate of PMOS M22 are connected to the drain of NMOS M23, the drain of PMOS M25 is connected to the drain of NMOS M24, and the gate of NMOS M24 is connected to the gate of NMOS M23.

[0028] The drain of PMOS M27 is connected to the drain of NMOS M28, the gate of NMOS M28 is connected to the drain of NMOS M24, and the source of NMOS M28, the source of NMOS M24, the source of NMOS M23, the source of NMOS M20 and the source of NMOS M19 are interconnected.

[0029] The input of inverter INV1 is connected to the drain of NMOS M28, the output is connected to the input of inverter INV2, and the output of inverter INV2 outputs OUT1 signal.

[0030] The application provides a variable threshold temperature switch circuit, which comprises a bandgap reference bias module, a PTAT voltage generation module, a CTAT voltage generation module and a comparator. Different PTAT voltage values are generated by fuse adjustment, so as to change the flip voltage of the temperature switch. The bandgap reference bias module is generated by a bandgap reference. Since the working range of the temperature switch is wide, the bandgap reference adopts a common source and common gate structure, so as to avoid the influence of channel adjustment effect and ensure that the reference has a good power supply rejection ratio. The bandgap reference bias module generates a PTAT current, which flows through a resistor to generate a PTAT voltage that changes positively with temperature. A diode conduction voltage is used to generate a CTAT voltage that changes negatively with temperature. The PTAT voltage and the CTAT voltage are input into two ends of the comparator. When a certain temperature is reached, the PTAT voltage and the CTAT voltage intersect, the output result of the comparator changes, and the temperature switch flips. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a whole circuit function structure diagram;

[0032] Figure 2 is a circuit diagram of the bandgap reference bias module;

[0033] Figure 3 is a circuit diagram of the PTAT voltage generation module;

[0034] Figure 4 is a circuit diagram of the CTAT voltage generation module;

[0035] Figure 5 is a circuit diagram of the comparator; DETAILED DESCRIPTION

[0036] The application provides a variable threshold temperature switch circuit, which will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and characteristics of the application will be more apparent. It should be noted that the drawings are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting in the description of the embodiments of the application.

[0037] The application is a variable threshold temperature switch circuit realized by fuse resistance adjustment, as shown in Figure 1The diagram shown is a functional structure diagram of the overall circuit of the present invention. The overall circuit includes a bandgap reference bias module, a PTAT voltage generation module, a CTAT voltage generation module, and a comparator. The bandgap reference bias module is designed based on a basic bandgap reference source model. To avoid communication modulation effects and obtain a better power supply rejection ratio, a common-source, common-gate structure is adopted. The PTAT voltage generation module generates a voltage that changes positively with temperature, and the CTAT voltage generation module generates a voltage that changes negatively with temperature. By setting a fuse resistor, the PTAT voltage and CTAT voltage can be made to cross at different temperature points. After comparison by the comparator, the comparator flips at different temperature points, realizing the function of a variable threshold temperature switch.

[0038] like Figure 2 The diagram shows the specific circuit diagram of the bandgap reference bias module. Due to the large operating temperature range of the temperature switch, a common-source, common-gate structure is used for the reference source to reduce channel length modulation effect and increase power supply rejection ratio. The first layer of bias for the current mirror is provided by the output of an operational amplifier, and the second layer of bias consists of PMOS transistors M9, M10, M11, and M12. The startup branch consists of PMOS transistors M1, M2, M3, and M4. PMOS transistors M1 and M2 are inverting ratio transistors, equivalent to large resistors. Initially, the current flowing through the current mirror is zero, and the gate voltage of NMOS transistor M10 is low, causing NMOS transistor M3 to be cut off. Because NMOS transistor M3 is cut off, the startup branch is not open, causing the gate voltage of NMOS transistor M4 to rise. NMOS transistor M4 then conducts, resulting in a low-level bias voltage output from the op-amp, thus turning on the first layer of bias. The op-amp's low-level output causes the second layer of bias transistors M9, M10, M11, and M12 to conduct, thereby enabling the entire bias reference circuit to enter normal operation. When the circuit is operating normally, the conduction of NMOS transistor M10 causes NMOS transistor M3 to conduct, pulling down the gate voltage of NMOS transistor M4, causing NMOS transistor M4 to turn off, thus turning off the startup circuit. Because PMOS transistors M1 and M2 are inverting ratio transistors with relatively high resistance, the quiescent current of the startup circuit is small.

[0039] like Figure 3 The diagram shows the PTAT voltage generation module. PMOS transistors M13 and M14 act as current mirrors, mirroring the PTAT current generated by the bandgap reference bias module. This current flows through a variable resistor to generate a PTAT voltage V that varies positively with temperature. PTAT =(R+r i )*I PTAT The setting of r can be achieved through fuse adjustment. i The resistance value is used to create a temperature switch that flips at different temperature points. The fuse structure is as follows: Figure 3As shown, because the fuse resistance is small, the fuse is not burned out, and the fuse structure outputs low level; the fuse is burned out, the power supply charges through the resistance, and the fuse structure outputs high level; the N-bit fuse is decoded by the decoder, and can control 2 N bit switches, and the switching temperature of the variable threshold temperature switch is changed to 2 N bits according to the fuse trimming.

[0040] As Figure 4 shown is a structure schematic diagram of the CTAT voltage generation module, PMOS tube M15 and PMOS tube M16 are mirror current sources, the CTAT current generated by the mirror bandgap reference bias module, the collector and the base of the triode Q3 are shorted together and connected in the form of a diode, the temperature characteristic of the diode is used to generate a V CTAT voltage which changes negatively with temperature.

[0041] As Figure 5 shown, the comparator is a two-stage comparator, PMOS tube M17, PMOS tube M18, NMOS tube M19, NMOS tube M20, PMOS tube M21 mirror bandgap reference bias module current, provide bias for the comparator; PMOS tube M22, NMOS tube M23, NMOS tube M24, PMOS tube M25, PMOS tube M26 constitute the first stage of the comparator, PMOS tube M26 is the mirror bias current of the comparator, NMOS tube M22 and PMOS tube M25 are the input stage of the comparator, and are connected with PTAT voltage V PTAT and V CTAT voltage respectively; PMOS tube M27, NMOS tube M28 constitute the second stage of the comparator, PMOS tube M27 is the mirror bias current of the second stage of the comparator, and NMOS tube M28 is the output tube; inverters INV1 and INV2 are two-stage inverter shaping circuits, and improve the driving ability of the circuit; when V PTAT >V CTAT , the comparator outputs high level, and when V PTAT is less than V CTAT , the comparator outputs low level.

[0042] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way, and any change and modification of the present application made by the person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A variable threshold temperature switching circuit, characterized in that, Includes a bandgap reference bias module, a PTAT voltage generation module, a CTAT voltage generation module, and a comparator; The bandgap reference bias module is designed based on the bandgap reference source model and combined with a common source and common gate structure to achieve a high power supply rejection ratio and a temperature-dependent positively varying PTAT bias current. The PTAT voltage generation module receives PTAT bias current from the bandgap reference bias module, generating a PTAT voltage that changes positively with temperature; the PTAT voltage generation module utilizes the base-emitter junction voltage difference ΔV between two bipolar transistors. BE A physical quantity with a positive temperature coefficient (PTAT) is constructed, and I is provided by the bandgap reference bias module through a common-source cascode current mirror. PTAT Current, current flows through resistor R+r i PTAT voltage generated: V PTAT =(R+ r i )*I PTAT By adjusting the fuse, different output voltages are generated. The fuse output is decoded by a decoder, controlling the resistor r. i When the connected corresponding switches are turned on, the resistance r is modified. i Resistance value, changing the PTAT voltage value V PTAT This achieves the purpose of changing the switching temperature of the temperature switch; the PTAT voltage generation module includes PMOS transistors M13 and M14, resistor R, and an N-bit fuse; the source of PMOS transistor M13 is connected to the positive power supply, the gates of PMOS transistors M13 and M14 are connected to the reference source output, the drain of PMOS transistor M13 is connected to the source of PMOS transistor M14, and the drain of PMOS transistor M14 is connected to the N-bit fuse through resistor R; the N-bit fuse is decoded by a decoder to control 2 N The toggle temperature of the position switch, a variable threshold temperature switch, changes to 2 based on the fuse adjustment. N Bit; The CTAT voltage generating module, due to the diode voltage V BE The negative temperature characteristic generates a CTAT voltage that varies negatively with temperature; the CTAT voltage generation module utilizes the base-emitter junction voltage V of the bipolar transistor. BE It inherently possesses a negative temperature coefficient temperature characteristic, which is provided by the bandgap reference bias module through a common-source cascode current mirror. PTAT Current, thus producing a current that is almost unaffected by β F The base-emitter junction voltage V affected BE ; The comparator is biased by the bandgap reference bias module and adopts a two-stage structure. The output result is shaped. The PTAT voltage and CTAT voltage are input to the two ends of the comparator. When a certain temperature is reached, the PTAT voltage and CTAT voltage converge, the comparator output result changes, and the temperature switch flips.

2. The variable threshold temperature switching circuit as described in claim 1, characterized in that, The bandgap reference bias module connects the bases of a pair of transistors with a certain ratio of emitter area, and connects their collectors to the input ports of the operational amplifier. The emitter of the transistor with the larger emitter area is connected to a small resistor. The current mirror in the bandgap reference bias module adopts a common source and common gate structure. At the same time, the PSRR of the bias current generation circuit is improved by using the common source and common gate current mirror.

3. The variable threshold temperature switching circuit as described in claim 2, characterized in that, The bandgap reference bias module includes PMOS transistors M1, M2, M5~M9, M12~M14, NMOS transistors M3, M4, M10, M11, resistor R1, transistors Q1, Q2, and amplifier A0. The source terminals of PMOS transistors M1, M5, M8, M9, M12, and M14 are interconnected. The gate and drain terminals of PMOS transistor M1 are connected to the source terminal of PMOS transistor M2. The gate and drain terminals of PMOS transistor M2 are connected to the gate terminal of NMOS transistor M4 and the drain terminal of NMOS transistor M3. The source terminals of NMOS transistors M3, M4, M10, and M11 are interconnected. The drain of NMOS transistor M4 is connected to the gate of PMOS transistors M5, M8, and M9. The drain of PMOS transistor M5 is connected to the source of PMOS transistor M6. The gate of PMOS transistor M6 is connected to the gate of PMOS transistors M7 and M12. The drain of PMOS transistor M6 is connected to the positive input of amplifier A0 and the first end of resistor R1. The second end of resistor R1 is connected to the emitter of transistor Q1. The base of transistor Q1 is connected to the base of transistor Q2. The collector of transistor Q1 is connected to the collector of transistor Q2. The drain of PMOS transistor M8 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 is connected to the negative input of amplifier A0 and the emitter of transistor Q2. The gate of PMOS transistor M9 is connected to the output of amplifier A0 and the gate of PMOS transistor M14. The drain of PMOS transistor M9 is connected to the drain of NMOS transistor M10 and the gate of NMOS transistor M3. The drain of NMOS transistor M10 is connected to its own gate and the gate of NMOS transistor M11. The gate of PMOS transistor M12 is connected to the gate of PMOS transistor M13 and the gate of PMOS transistor M7. The drain of PMOS transistor M12 is connected to the drain of NMOS transistor M11. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M13. The drain of PMOS transistor M13 is grounded.

4. The variable threshold temperature switching circuit as described in claim 1, characterized in that, The CTAT voltage generation module includes PMOS transistor M15, PMOS transistor M16 and transistor Q3; The source of PMOS transistor M15 is connected to the positive power supply. The gates of PMOS transistors M15 and M16 are connected to the reference source output. The drain of PMOS transistor M15 is connected to the source of PMOS transistor M16. The drain of PMOS transistor M16 is connected to the emitter of transistor Q3. The base and collector of transistor Q3 are grounded together.

5. The variable threshold temperature switching circuit as described in claim 1, characterized in that, The comparator is a two-stage open-loop structure. The input stage uses a PMOS differential input pair; the second stage circuit is a single NMOS transistor, which converts the differential input to a single output, forming a push-free structure with the input stage; the output stage is a two-stage inverter with gradually increasing inverter area, which shapes the output waveform while increasing the driving capability of the circuit to drive larger capacitive loads.

6. The variable threshold temperature switching circuit as described in claim 5, characterized in that, The comparator includes PMOS transistors M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, M28, and inverters INV1 and INV2; The gate terminals of PMOS transistors M17 and M18 are connected to the reference source output, and the gate terminal of PMOS transistor M22 is connected to the PTAT voltage generation module output V. PTAT The gate of PMOS transistor M25 is connected to the CTAT voltage generation module output V. CTAT Voltage; the source terminals of PMOS transistors M17, M21, M26, and M27 are interconnected; the drain terminal of PMOS transistor M17 is connected to the source terminal of PMOS transistor M18; the drain terminal of PMOS transistor M18 is connected to the drain terminal of NMOS transistor M19; the gate terminal of NMOS transistor M19 is connected to its own drain terminal. The gate of PMOS transistor M21 is connected to its own drain and the gate of PMOS transistor M26. The drain of PMOS transistor M21 is connected to the drain of NMOS transistor M20. The gate of NMOS transistor M20 is connected to the gate of NMOS transistor M19. The gate of PMOS transistor M26 is connected to the gate of PMOS transistor M27, and the drain of PMOS transistor M26 is connected to the source of PMOS transistor M22 and the source of PMOS transistor M25; the drain of PMOS transistor M22 is connected to the drain and gate of NMOS transistor M23, the drain of PMOS transistor M25 is connected to the drain of NMOS transistor M24, and the gate of NMOS transistor M24 is connected to the gate of NMOS transistor M23. The drain of PMOS transistor M27 is connected to the drain of NMOS transistor M28, the gate of NMOS transistor M28 is connected to the drain of NMOS transistor M24, and the source terminals of NMOS transistor M28, NMOS transistor M24, NMOS transistor M23, NMOS transistor M20, and NMOS transistor M19 are interconnected. The input terminal of inverter INV1 is connected to the drain terminal of NMOS transistor M28, and the output terminal is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 outputs the OUT1 signal.

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