Method for manufacturing Y-type grid and electronic device including the Y-type grid

Abstract

The present invention relates to the field of semiconductor technology, and discloses a method for manufacturing a Y-type gate and an electronic device. The method for manufacturing the Y-type gate comprises: providing a HEMT substrate, and depositing a dielectric layer on the HEMT substrate; coating a first photoresist on the dielectric layer, and processing the first photoresist by exposure and development process to obtain an arc-shaped groove, wherein the bottom of the arc-shaped groove is located on the top surface of the dielectric layer; etching the dielectric layer along the vertical direction from the bottom of the arc-shaped groove to form an I-shaped groove, and the arc-shaped groove is connected with the I-shaped groove to form a Y-shaped groove; baking the first photoresist to adjust the angle of the arc-shaped groove; removing the first photoresist; preparing the Y-type gate in the Y-shaped groove; the manufacturing method only needs to spin-coat the photoresist once, and photolithography and etching once to form the Y-shaped groove, which can simplify the manufacturing process steps of the Y-type gate, thereby improving production efficiency and reducing production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a Y-type gate and an electronic device. Background Art

[0002] GaN has become the preferred semiconductor material for the next generation of RF technology due to its superior material properties. GaN's High Electron Mobility Transistor (HEMT) uses the two-dimensional electron gas formed by the GaN / AlGaN heterojunction to achieve the RF characteristics of the high electron mobility transistor, and uses the high breakdown electric field characteristics of GaN to achieve power amplification of the input signal under high frequency conditions.

[0003] The cut-off frequency fT is the main technical performance indicator for measuring the high-frequency performance of high electron mobility transistors. The cut-off frequency fT is affected by the gate length and gate morphology. The extremely thin gate strip will increase the series resistance. The maximum cut-off frequency fT is max To increase the cut-off frequency fT, a Y-type gate is generally used.

[0004] The manufacturing method of the Y-type gate in the related art usually adopts the method of electron beam multi-direct writing multi-layer photoresist process or multiple exposure multi-layer photoresist, and forms the Y-type gate by taking advantage of the difference in sensitivity of electron beam photoresist. Multiple exposure multi-layer photoresist is to control the development time by taking advantage of the different sensitivities of different layers of photoresist to achieve the purpose of forming a Y-type morphology, which is easy for metal stripping. However, this method has interference between the development of each layer, and has high requirements for the development process. It is necessary to strictly control the development time of each layer to obtain the Y-type morphology; and the multi-layer photoresist is relatively complicated in the process, and it is necessary to increase the process steps and reduce the process efficiency. Summary of the invention

[0005] The present invention provides a method for manufacturing a Y-type grid and an electronic device comprising the Y-type grid, which can simplify process steps, thereby improving production efficiency and reducing production costs.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a method for manufacturing a Y-type grid, comprising:

[0007] Providing a HEMT substrate, and depositing a dielectric layer on the HEMT substrate;

[0008] A first photoresist is coated on the dielectric layer, and an exposure and development process is used to process the first photoresist to obtain an arc-shaped groove, wherein the bottom of the arc-shaped groove is located on the top surface of the dielectric layer;

[0009] The dielectric layer is etched along the vertical direction from the bottom of the arc-shaped groove to form an I-shaped groove, wherein the arc-shaped groove is connected with the I-shaped groove to form a Y-shaped groove;

[0010] Performing baking treatment on the first photoresist to adjust the angle of the arc groove;

[0011] removing the first photoresist;

[0012] The Y-shaped grid is prepared in the Y-shaped groove.

[0013] According to an embodiment of the present invention, preparing the Y-shaped gate in the Y-shaped groove further comprises:

[0014] The top surface of the dielectric layer and the groove wall of the Y-shaped groove are processed by electron beam evaporation metal process to form a metal layer;

[0015] Coating a second photoresist on the metal layer, and treating it by exposure and development process to obtain a photoresist column, wherein the photoresist column fills the Y-shaped groove, and blocks part of the metal layer and exposes part of the metal layer outside the photoresist column;

[0016] Etching the metal layer to etch the portion of the metal layer exposed outside the photoresist column;

[0017] The photoresist column is removed to obtain the Y-type gate.

[0018] According to an embodiment of the present invention, after coating a layer of second photoresist on the metal layer and performing exposure and development processes to obtain photoresist columns, the method further includes:

[0019] The photoresist column is baked to adjust the side wall angle of the photoresist column, wherein the baking temperature is 110° C.-140° C., the baking time is 60s-300s, and the adjustment range of the side wall angle is 30°-80°.

[0020] According to an embodiment of the present invention, the material of the metal layer is one or more of Ti, Al, Ni and Au, and the thickness of the metal layer is 0.3um-4.0um.

[0021] According to one embodiment of the present invention, providing a HEMT substrate further comprises:

[0022] Epitaxially growing a GaN layer on a substrate layer by an MOCVD process, wherein the substrate layer is a Si substrate, a Sapphire substrate or a SiC substrate;

[0023] An epitaxial layer is grown on the top surface of the GaN layer to obtain the HEMT substrate.

[0024] According to an embodiment of the present invention, the material of the dielectric layer is one or more of SiN, SiO2 and Al2O3, and the thickness of the dielectric layer is 500nm-2000nm.

[0025] According to one embodiment of the present invention, when the material of the dielectric layer is SiN and / or SiO2, in the step of etching the dielectric layer from the bottom of the arc-shaped groove along the vertical direction, the etching gas is a fluorine-based gas and O2.

[0026] According to an embodiment of the present invention, when the material of the dielectric layer is Al2O3, in the step of etching the dielectric layer from the bottom of the arc-shaped groove along the vertical direction, the etching gas is a gas containing Cl-based.

[0027] According to an embodiment of the present invention, the first photoresist is KrF photoresist or i-line photoresist.

[0028] In order to solve the above technical problem, another technical solution adopted by the present invention is: to provide an electronic device, comprising: a Y-type grid, wherein the Y-type grid is obtained using the manufacturing method of the Y-type grid.

[0029] The invention has the following beneficial effects: a method for manufacturing a Y-type gate, comprising: providing a HEMT substrate, and depositing a dielectric layer on the HEMT substrate; coating a first photoresist on the dielectric layer, and performing exposure and development processes to obtain an arc-shaped groove, wherein the groove bottom of the arc-shaped groove is located on the top surface of the dielectric layer; etching the dielectric layer along a vertical direction from the groove bottom of the arc-shaped groove to form an I-shaped groove, wherein the arc-shaped groove is connected with the I-shaped groove to form a Y-shaped groove; baking the first photoresist to adjust the angle of the arc-shaped groove; removing the first photoresist; preparing the Y-type gate in the Y-shaped groove; the manufacturing method only requires one spin coating of the photoresist, one photolithography and one etching to form the Y-shaped groove, and can simplify the manufacturing process steps of the Y-type gate, thereby improving production efficiency and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic flow chart of a method for manufacturing a Y-type gate according to an embodiment of the present invention;

[0031] Figure 2 is a SEM image of the pattern obtained with different layout design sizes in step S20 of the embodiment of the present invention;

[0032] Figure 3 is a flow chart of step S60 of an embodiment of the present invention;

[0033] Figure 4 is a flow chart of step S60 of another embodiment of the present invention;

[0034] Figure 5 is a flow chart of step S10 of an embodiment of the present invention;

[0035] Figure 6 is a schematic structural diagram of a HEMT substrate according to an embodiment of the present invention;

[0036] Figure 7 is a schematic structural diagram of a HEMT substrate and a dielectric layer according to an embodiment of the present invention;

[0037] Figure 8 is a schematic structural diagram of a HEMT substrate, a dielectric layer and a first photoresist according to an embodiment of the present invention;

[0038] Fig. 9 1 is a schematic structural diagram of a HEMT substrate, a dielectric layer and a Y-shaped groove according to an embodiment of the present invention;

[0039] Fig.10 is a schematic structural diagram of a HEMT substrate, a dielectric layer and a metal layer according to an embodiment of the present invention;

[0040] Fig.11 It is a schematic structural diagram of a HEMT substrate, a dielectric layer, a metal layer, and a second photoresist according to an embodiment of the present invention;

[0041] Fig.12 It is a schematic structural diagram of a HEMT substrate, a dielectric layer, a metal layer and a photoresist column according to an embodiment of the present invention;

[0042] Fig.13 It is a schematic structural diagram of a HEMT substrate, a dielectric layer and a Y-type gate according to an embodiment of the present invention.

[0043] The meanings of the symbols in the accompanying drawings are:

[0044] 10-HEMT substrate; 101-substrate layer; 102-GaN layer; 103-epitaxial layer; 20-dielectric layer; 30-first photoresist; 301-arc-shaped groove; 302-I-shaped groove; 303-Y-shaped groove; 40-metal layer; 50-photoresist column; 70-Y-shaped gate. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] The terms "first", "second" and "third" in the present invention are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0047] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a Y-type gate according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the method of manufacturing a Y-type gate according to an embodiment of the present invention. Figure 1 The process sequence shown is limited. Figure 1 As shown, the method comprises the steps of:

[0049] Step S10: providing a HEMT substrate, and depositing a dielectric layer on the HEMT substrate.

[0050] In step S10, the material of the dielectric layer is one or more of SiN, SiO2 and Al2O3, and the thickness of the dielectric layer is 500nm-2000nm. The deposition can use low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. The dielectric layer is deposited on the HEMT substrate, and the dielectric layer has a protective effect on the HEMT substrate. The thickness of the dielectric layer is set to be relatively large, which can prevent the HEMT substrate from being damaged when preparing the Y-shaped groove.

[0051] Step S20: coating a layer of first photoresist on the dielectric layer, and performing exposure and development processes to obtain an arc-shaped groove, wherein the bottom of the arc-shaped groove is located on the top surface of the dielectric layer.

[0052] In step S20, the coating and developing equipment may be an industrial track equipment, the exposure equipment may be an industrial stepper lithography machine or a scanner lithography machine, and the exposure wavelength may be 365nm or 248nm.

[0053] The first photoresist can be KrF photoresist or i-line photoresist with a thickness of 0.3um-5.0um. The specific thickness can be selected according to the etching selectivity and line width resolution. The critical dimension (CD) of the pattern after photolithography in this step is determined by the equipment capabilities of the photoresist and the photolithography machine. For example, KrF photoresist combined with ASML photolithography machine 850C can produce a CD of 110nm, and i-line photoresist combined with Iline photolithography machine can achieve a CD of 500nm. The size of the Y-type gate cutoff frequency is determined by the size of the CD (gate length). The size of the CD is mainly determined by the size of the layout design. At the same time, the exposure energy can be adjusted to fine-tune the CD of the photoresist, thereby improving the preparation accuracy of the Y-type gate and further improving the performance of the Y-type gate. Figure 2 As shown in the figure, the characteristic sizes of the following patterns can be achieved by different layout design sizes: in Figure (a), the size of CD is 2.098μm, in Figure (b), the size of CD is 1.411μm, in Figure (c), the size of CD is 1.168μm, and in Figure (d), the size of CD is 0.600μm; by controlling the characteristic size of the pattern, the cutoff frequency of the Y-type gate can be controlled, thereby increasing the cutoff frequency of the HEMT.

[0054] Step S30: etching the dielectric layer from the bottom of the arc-shaped groove along the vertical direction to form an I-shaped groove, and the arc-shaped groove is connected with the I-shaped groove to form a Y-shaped groove.

[0055] In step S30, after the dielectric layer is etched through by the etching machine, the etching machine stops etching. When the dielectric layer is made of SiN and / or SiO2, the etching gas is a fluorine-containing gas and O2, and the fluorine-containing gas is, for example, CF4, wherein the O2 content accounts for 5%-20%. When the dielectric layer is made of Al2O3, the etching gas is a Cl-containing gas, for example, Cl2.

[0056] Step S40: baking the first photoresist to adjust the angle of the arc groove.

[0057] In step S40, the first photoresist is baked to adjust the sidewall angle of the first photoresist, and then adjust the angle of the arc groove, thereby improving the preparation accuracy of the Y-shaped groove. The baking temperature is 110°C-140°C, the baking time is 60s-300s, and the adjustment range of the sidewall angle is 30°-80°.

[0058] Step S50: removing the first photoresist.

[0059] In step S50, dry O2 plasma removal or wet removal can be used, and the wet removal uses one of a degumming solution, NMP (N-methylpyrrolidone) and acetone.

[0060] Step S60: preparing a Y-shaped gate in the Y-shaped groove.

[0061] The manufacturing method of the Y-type gate of the embodiment of the present invention can form the Y-type groove by spin coating a photoresist, photolithography and etching once, which can simplify the manufacturing process steps of the Y-type gate, thereby improving production efficiency and reducing production costs.

[0062] In some embodiments, see Figure 3 , step S60 further includes the following steps:

[0063] Step S601: an electron beam evaporation metal process is used to form a metal layer on the top surface of the dielectric layer and the groove wall of the Y-shaped groove.

[0064] In step S601, the material of the metal layer is one or more of Ti, Al, Ni and Au, which has good corrosion resistance, can remain relatively stable under various environmental conditions, and can improve the molding quality and precision of the Y-type grid. The thickness of the metal layer is 0.3um-4.0um.

[0065] Step S602: coating a second photoresist layer on the metal layer, and performing exposure and development processes to obtain a photoresist column, wherein the photoresist column fills the Y-shaped groove and blocks part of the metal layer and exposes part of the metal layer outside the photoresist column.

[0066] Step S603: etching the metal layer to etch the portion of the metal layer exposed outside the photoresist pillar.

[0067] In step S603, the metal layer without Au is removed by dry etching, and the etching gas is Cl2 or Cl-based gas; the metal layer containing Au is removed by wet etching.

[0068] Step S604: remove the photoresist column to obtain a Y-shaped gate.

[0069] In step S604 , the method of removing the photoresist column is similar to that of step S40 , which will not be described in detail here.

[0070] In some embodiments, see Figure 4 , after step S602, further comprising:

[0071] Step S605: baking the photoresist column to adjust the side wall angle of the photoresist column, wherein the baking temperature is 110° C.-140° C., the baking time is 60s-300s, and the adjustment range of the side wall angle is 30°-80°.

[0072] In this step, a suitable baking temperature and baking time can be selected according to the metal filling effect of step S601 to adjust the side wall angle of the photoresist column, which helps to improve the preparation accuracy and performance of the Y-type gate.

[0073] In some embodiments, see Figure 5 , step S10 further includes:

[0074] Step S101: epitaxially growing a GaN layer on a substrate layer by MOCVD process, wherein the substrate layer is a Si substrate, a Sapphire substrate or a SiC substrate;

[0075] Step S102: growing an epitaxial layer on the top surface of the GaN layer to obtain a HEMT substrate.

[0076] Compared with traditional materials such as silicon and gallium arsenide, HEMT devices made of GaN have faster electron movement speed in GaN, that is, HEMT devices can provide higher operating speed and higher frequency response, and are suitable for high-speed and high-frequency applications. At the same time, the high electron mobility and wide bandgap width of GaN materials enable HEMT devices to withstand higher current density, provide greater power output and higher efficiency, and are suitable for power amplifiers and high-power applications.

[0077] Exemplarily, the manufacturing process of the Y-type gate is as follows: a GaN layer 102 is epitaxially grown on a substrate layer 101 by a MOCVD process, and an epitaxial layer 103 is grown on the top surface of the GaN layer 102 to obtain a HEMT substrate 10, such as Figure 6 As shown; a dielectric layer 20 is deposited on the HEMT substrate 10, as Figure 7 A first photoresist layer 30 is coated on the dielectric layer 20, and an exposure and development process is performed to obtain an arc-shaped groove 301, as shown in FIG. Figure 8 As shown; the dielectric layer 20 is etched along the vertical direction from the bottom of the arc-shaped groove 301 to form an I-shaped groove 302, the arc-shaped groove 301 is connected to the I-shaped groove 302 and forms a Y-shaped groove 303, and the first photoresist 30 is baked to adjust the angle of the arc-shaped groove 301 and remove the first photoresist 30, as shown Fig. 9 The top surface of the dielectric layer 20 and the groove wall of the Y-shaped groove 303 are processed by electron beam evaporation metal process to form a metal layer 40, such as Fig.10As shown; a second photoresist layer is coated on the metal layer 40, and an exposure and development process is performed to obtain a photoresist column 50, wherein the photoresist column 50 fills the Y-shaped groove 303, and blocks part of the metal layer 40 and exposes part of the metal layer 40 outside the photoresist column 50, as shown Fig.11 Etching the metal layer 40 to etch the portion of the metal layer 40 exposed outside the photoresist column 50, as shown in FIG. Fig.12 As shown; remove the photoresist column 50 to obtain a Y-type gate 70, such as Fig.13 shown.

[0078] The embodiment of the present invention further provides an electronic device, comprising: a Y-type gate, wherein the Y-type gate is obtained by using the above-mentioned manufacturing method of the Y-type gate. The electronic device has a higher cutoff frequency and fewer manufacturing process flows, and has higher production efficiency.

[0079] The above are only implementation modes of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a Y-type grid, characterized in that: include: Providing a HEMT substrate, and depositing a dielectric layer on the HEMT substrate; A first photoresist is coated on the dielectric layer, and an exposure and development process is used to process the first photoresist to obtain an arc-shaped groove, wherein the bottom of the arc-shaped groove is located on the top surface of the dielectric layer; The dielectric layer is etched vertically from the bottom of the arc-shaped groove by one-time photolithography to form an I-shaped groove, and finally a Y-shaped groove is formed in the dielectric layer; the material of the dielectric layer is SiN and / or SiO2, and the etching gas is a fluorine-based gas and O2, or the material of the dielectric layer is Al2O3, and the etching gas is a chlorine-based gas; Performing baking treatment on the first photoresist to adjust the angle of the arc groove; removing the first photoresist; preparing the Y-shaped grid in the Y-shaped groove; The preparing the Y-shaped gate in the Y-shaped groove further comprises: The top surface of the dielectric layer and the groove wall of the Y-shaped groove are processed by electron beam evaporation metal process to form a metal layer; Coating a second photoresist on the metal layer, and treating it by exposure and development process to obtain a photoresist column, wherein the photoresist column fills the Y-shaped groove, and blocks part of the metal layer and exposes part of the metal layer outside the photoresist column; Etching the metal layer to etch the portion of the metal layer exposed outside the photoresist column; Removing the photoresist column to obtain the Y-shaped gate; The method further comprises coating a second photoresist on the metal layer and performing exposure and development processes to obtain a photoresist column. The photoresist column is baked to adjust the side wall angle of the photoresist column, wherein the baking temperature is 110° C.-140° C., the baking time is 60s-300s, and the adjustment range of the side wall angle is 30°-80°.

2. The method for manufacturing a Y-type grid according to claim 1, characterized in that: The material of the metal layer is one or more of Ti, Al, Ni and Au, and the thickness of the metal layer is 0.3um-4.0um.

3. The method for manufacturing a Y-shaped grid according to claim 1, characterized in that: Providing a HEMT substrate further comprises: Epitaxially growing a GaN layer on a substrate layer by an MOCVD process, wherein the substrate layer is a Si substrate, a Sapphire substrate or a SiC substrate; An epitaxial layer is grown on the top surface of the GaN layer to obtain the HEMT substrate.

4. The method for manufacturing a Y-type grid according to claim 1, characterized in that: The thickness of the dielectric layer is 500nm-2000nm.

5. The method for manufacturing a Y-type grid according to claim 1, characterized in that: The first photoresist is KrF photoresist or i-line photoresist.

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