A multi-sided pin chip packaging method and packaging structure

Abstract

The application relates to the chip packaging technical field, and particularly provides a multi-surface pin chip packaging method and a packaging structure. The method comprises the following steps: attaching a bottom surface of a multi-surface pin chip to a first conductive layer in a chip accommodating groove in a downward manner; forming a first insulating layer between the multi-surface pin chip and the chip accommodating groove; forming two second conductive layers on the first insulating layer, the two second conductive layers being electrically connected with pins on two side surfaces of the multi-surface pin chip respectively, and a second insulating layer being formed between the two second conductive layers; forming a first conductive column penetrating through a chip accommodating layer on at least one side of the chip accommodating groove, and forming an electrical connection structure on a top surface of the chip accommodating layer; removing a carrier plate and part of the first conductive layer, and forming a plastic sealing layer on the first conductive layer; and sequentially forming the first conductive layer and the chip accommodating layer on the carrier plate. The method can effectively reduce the packaging cost of the multi-surface pin chip and improve the reliability of the multi-surface pin chip packaging structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a multi-face pin chip packaging method and a packaging structure. BACKGROUND

[0002] The prior art needs to use a multi-face pin chip packaging method to package a multi-face pin chip (a chip with pins on the top surface, the bottom surface and two mutually symmetrical side surfaces). The specific process of the existing multi-face pin chip packaging method is as follows: based on a wire bonding device, pins on multiple surfaces of the multi-face pin chip are led out to the same plane (for example, pins on the bottom surface and the two side surfaces are led out to the top surface by using a wire); the multi-face pin chip with the led-out pins is surface-mounted; and the multi-face pin chip with the surface-mounted pins is attached to a packaging substrate. Since the existing multi-face pin chip packaging method needs to use a wire bonding device to lead out pins on multiple surfaces of the multi-face pin chip to the same plane, the device cost of the wire bonding device is high, and the wire is prone to breakage and falling off and causes permanent damage to the pad interface of the multi-face pin chip. Therefore, the existing multi-face pin chip packaging method has the problems of high packaging cost of the multi-face pin chip due to the need to use the wire bonding device to lead out pins on multiple surfaces of the multi-face pin chip to the same plane, and low reliability of the packaging structure obtained by the multi-face pin chip packaging method due to the wire being prone to breakage and falling off and causing permanent damage to the pad interface of the multi-face pin chip.

[0003] At present, there is no effective technical solution to the above problems. SUMMARY

[0004] The purpose of the present application is to provide a multi-face pin chip packaging method and a packaging structure, which can effectively solve the problems of high packaging cost of the multi-face pin chip due to the need to use the wire bonding device to lead out pins on multiple surfaces of the multi-face pin chip to the same plane, and low reliability of the packaging structure obtained by the multi-face pin chip packaging method due to the wire being prone to breakage and falling off and causing permanent damage to the pad interface of the multi-face pin chip.

[0005] In a first aspect, the present application provides a multi-face pin chip packaging method, a multi-face pin chip having pins on the top surface, the bottom surface and two mutually symmetrical side surfaces, the multi-face pin chip packaging method comprising the following steps:

[0006] S1, forming a chip accommodating layer on the side of the first conductive layer away from the carrier plate, the chip accommodating layer being provided with a plurality of chip accommodating grooves;

[0007] S2, attaching the bottom surface of the multi-face pin chip to the first conductive layer in the chip accommodating groove with the bottom surface facing down;

[0008] S3, forming a first insulating layer between the multi-sided pin chip and the chip accommodating groove;

[0009] S4, forming two second conductive layers respectively electrically connected with the pins on the two sides of the multi-sided pin chip on the first insulating layer, and forming a second insulating layer between the two second conductive layers;

[0010] S5, forming a first conductive column penetrating through the chip accommodating layer on at least one side of the chip accommodating groove, and forming an electrical connection structure electrically connected with the first conductive column on the top surface of the chip accommodating layer;

[0011] S6, removing the carrier plate and part of the first conductive layer, so that the pins on the bottom surface of the multi-sided pin chip are conducted through the remaining first conductive layer and the first conductive column outside, and forming a plastic sealing layer on the first conductive layer.

[0012] The multi-sided pin chip packaging method provided by the application first attaches the bottom surface of the multi-sided pin chip downward on the first conductive layer in the chip accommodating groove, forms a first insulating layer between the multi-sided pin chip and the chip accommodating groove, then forms two second conductive layers respectively electrically connected with the pins on the two sides on the first insulating layer, and forms a second insulating layer between the two second conductive layers, and then forms a first conductive column on at least one side of the chip accommodating groove, and forms an electrical connection structure electrically connected with the first conductive column on the top surface of the chip accommodating layer. Since the application can respectively lead out the pins on the two sides of the multi-sided pin chip to the top surface of the multi-sided pin chip through the two second conductive layers, and can also lead out the pins on the bottom surface of the multi-sided pin chip to the top surface of the multi-sided pin chip through the first conductive layer and the first conductive column, the application is equivalent to leading out the pins on the multiple surfaces of the multi-sided pin chip to the same plane through the first conductive layer, the second conductive layer and the first conductive column, that is, the application does not need to use a wire bonding device to lead out the pins on the multiple surfaces of the multi-sided pin chip to the same plane, thereby effectively solving the problems of high packaging cost of the multi-sided pin chip due to the need to use the wire bonding device to lead out the pins on the multiple surfaces of the multi-sided pin chip to the same plane, and low reliability of the packaging structure obtained by the multi-sided pin chip packaging method due to the easy breakage and falling off of the leads and the permanent damage to the pad interface of the multi-sided pin chip.

[0013] Optionally, step S5 comprises:

[0014] S51, forming a first conductive column penetrating through the chip accommodating layer on at least one side of the chip accommodating groove, and forming a first re-wiring layer electrically connected with the first conductive column, the top surface of the multi-sided pin chip and the two second conductive layers respectively on the top surface of the chip accommodating layer;

[0015] S52, forming a solder ball on the first re-wiring layer.

[0016] Optionally, step S51 comprises:

[0017] S511, forming a first patterned passivation film layer on the top surface of the chip accommodating layer, and forming a first conductive column on at least one side of the chip accommodating recess;

[0018] S512, sequentially forming a metal seed layer and a metal copper layer on the top surface of the chip accommodating layer and the top surface of the first conductive column based on the first patterned passivation film layer, to form a first metal wiring layer;

[0019] S513, forming a first patterned photosensitive film layer on the first metal wiring layer, and etching the first metal wiring layer based on the first patterned photosensitive film layer, to remove the first metal wiring layer outside the first conductive column, the top surface of the multi-faceted pin chip, and the two second conductive layers;

[0020] S514, removing the first patterned photosensitive film layer, and forming a second patterned passivation film layer on the first patterned passivation film layer;

[0021] S515, forming a third patterned passivation film layer on the second patterned passivation film layer, and sequentially forming a metal seed layer and a metal copper layer on the first metal wiring layer based on the third patterned passivation film layer, to form a second metal wiring layer.

[0022] Since the metal seed layer can increase the bonding force between the metal copper layer and the contact surface, the technical solution can effectively avoid the situation that the metal copper layer falls off due to the small bonding force between the metal copper layer and the contact surface.

[0023] Optionally, S511 comprises:

[0024] S5111, forming a first passivation film layer on the top surface of the chip accommodating layer;

[0025] S5112, etching the first passivation film layer based on a photolithography process or a laser engraving process using a first pre-set pattern mask, to form a first patterned passivation film layer on the top surface of the chip accommodating layer;

[0026] S5113, forming a first conductive column penetrating through the chip accommodating layer based on the first patterned passivation film layer using an etching process and an electroplating process on at least one side of the chip accommodating recess.

[0027] Optionally, step S6 comprises:

[0028] S61, removing the carrier plate, and etching the first conductive layer based on a dry etching process or a wet etching process, to remove part of the first conductive layer and make the pins on the bottom surface of the multi-faceted pin chip conductive through the remaining first conductive layer and the first conductive column outside thereof;

[0029] S62, forming a plastic encapsulation layer on the first conductive layer.

[0030] Optionally, the step S5 comprises:

[0031] S51', forming a first conductive column penetrating the chip accommodating layer on at least one side of the chip accommodating groove, and forming a second conductive column penetrating the chip accommodating layer on any one side of the chip accommodating groove;

[0032] S52', forming an electrical connection structure electrically connected with the first conductive column and the second conductive column on the top surface of the chip accommodating layer;

[0033] The step S6 further comprises a step performed between the step S61 and the step S62:

[0034] S63, forming a fourth patterned passivation film layer on the first conductive layer;

[0035] S64, forming a third conductive layer electrically connected with the second conductive column based on the fourth patterned passivation film layer;

[0036] S65, forming a fifth patterned passivation film layer on the fourth patterned passivation film layer, and forming a fourth conductive layer electrically connected with the third conductive layer based on the fifth patterned passivation film layer;

[0037] S66, attaching a regular chip with its active surface facing down on the fourth conductive layer;

[0038] The step S62 comprises:

[0039] S621, plastic encapsulating the regular chip to form a plastic encapsulation layer on the first conductive layer.

[0040] Since the prior art needs to use multiple through silicon vias to integrate chips with different performances in the same packaging structure, and the present application can integrate chips with different performances in the same packaging structure through the cooperation of the first conductive layer, the second conductive layer, the first conductive column, the third conductive layer, the fourth conductive layer and the second conductive column, the present application does not need to use multiple through silicon vias, that is, the present application is equivalent to realizing a three-dimensional fan-out packaging structure without using a through silicon via, thereby effectively reducing the packaging cost and packaging volume of the three-dimensional fan-out packaging structure.

[0041] Optionally, the step S1 comprises:

[0042] S11, forming an adhesive layer on the side of the first conductive layer away from the carrier plate;

[0043] S12, forming a second patterned photosensitive film layer on the adhesive layer;

[0044] S13, etching the adhesive layer based on the second patterned photosensitive film layer to form a chip accommodating layer with a plurality of chip accommodating grooves.

[0045] Optionally, the step S3 comprises:

[0046] S31, filling the gap between the multi-sided pin chip and the chip accommodating groove with underfill glue to form a first insulating layer.

[0047] Optionally, the left side and the right side of the multi-sided pin chip are both provided with pins, and the step S4 comprises:

[0048] S41, filling the gap between the left side and the chip accommodating groove and the gap between the right side and the chip accommodating groove with conductive glue or conductive metal to form two second conductive layers on the first insulating layer, which are respectively electrically connected with the pins on the two sides;

[0049] S42, filling the gap between the front side of the multi-sided pin chip and the chip accommodating groove and the gap between the back side of the multi-sided pin chip and the chip accommodating groove with underfill glue to form a second insulating layer between the two second conductive layers.

[0050] In a second aspect, the present application also provides a multi-sided pin chip packaging structure made by the multi-sided pin chip packaging method provided in the first aspect.

[0051] The multi-sided pin chip packaging structure provided by the present application can lead the pins on the two sides of the multi-sided pin chip to the top surface of the multi-sided pin chip through the two second conductive layers, and lead the pins on the bottom surface of the multi-sided pin chip to the top surface of the multi-sided pin chip through the first conductive layer and the first conductive column. Therefore, the present application is equivalent to leading the pins on the multiple surfaces of the multi-sided pin chip to the same plane through the first conductive layer, the second conductive layer and the first conductive column, i.e. the present application does not need to use a wire bonding device to lead the pins on the multiple surfaces of the multi-sided pin chip to the same plane, thereby effectively solving the problems of high packaging cost of the multi-sided pin chip due to the need to use a wire bonding device to lead the pins on the multiple surfaces of the multi-sided pin chip to the same plane, and low reliability of the multi-sided pin chip packaging structure due to the easy breakage and falling off of the leads and the permanent damage to the pad interface of the multi-sided pin chip.

[0052] From the above, the application provides a multi-face pin chip packaging method and packaging structure. The bottom surface of the multi-face pin chip is attached to the first conductive layer in the chip accommodating groove, and the first insulating layer is formed between the multi-face pin chip and the chip accommodating groove. The two second conductive layers electrically connected with the pins on the two side surfaces are formed on the first insulating layer, and the second insulating layer is formed between the two second conductive layers. The first conductive column is formed on at least one side of the chip accommodating groove, and the electrical connection structure electrically connected with the first conductive column is formed on the top surface of the chip accommodating layer. Since the two second conductive layers can lead the pins on the two side surfaces of the multi-face pin chip to the top surface of the multi-face pin chip, and the first conductive layer and the first conductive column can also lead the pins on the bottom surface of the multi-face pin chip to the top surface of the multi-face pin chip, the application can lead the pins on the multiple surfaces of the multi-face pin chip to the same plane through the first conductive layer, the second conductive layer and the first conductive column. That is, the application does not need to use a wire bonding device to lead the pins on the multiple surfaces of the multi-face pin chip to the same plane, thereby effectively solving the problems of high packaging cost of the multi-face pin chip due to the need to use the wire bonding device to lead the pins on the multiple surfaces of the multi-face pin chip to the same plane, and low reliability of the packaging structure obtained by the multi-face pin chip packaging method due to the easy breakage and falling off of the lead wire and the permanent damage to the pad interface of the multi-face pin chip. BRIEF DESCRIPTION OF DRAWINGS

[0053] Fig. 1 A flowchart of a multi-face pin chip packaging method provided by the technical solution of the application.

[0054] Fig. 2 A schematic diagram of a multi-face pin chip packaging method provided by the technical solution of the application.

[0055] Fig. 3 A top view structural schematic diagram of a chip accommodating layer, a second conductive layer, a second insulating layer and a multi-face pin chip provided by the technical solution of the application.

[0056] FIG. 1 is a schematic diagram of a multi-face pin chip packaging method provided by the technical solution of the application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0058] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0059] In a first aspect, as shown in the drawings, the present application provides a multi-sided pin chip packaging method, a top surface, a bottom surface and two mutually symmetrical side surfaces of a multi-sided pin chip 20 are provided with pins, and the multi-sided pin chip packaging method comprises the following steps: Figs. 1-3

[0060] S1, a chip accommodating layer 3 is formed on the side of the first conductive layer 2 away from the carrier board 1, and the chip accommodating layer 3 is provided with a plurality of chip accommodating grooves 19;

[0061] S2, the bottom surface of the multi-sided pin chip 20 is attached to the first conductive layer 2 in the chip accommodating groove 19 with the bottom surface facing down;

[0062] S3, a first insulating layer 4 is formed between the multi-sided pin chip 20 and the chip accommodating groove 19;

[0063] S4, two second conductive layers 5 respectively electrically connected to the pins on the two side surfaces of the multi-sided pin chip 20 are formed on the first insulating layer 4, and a second insulating layer 6 is formed between the two second conductive layers 5;

[0064] S5, a first conductive column 7 penetrating through the chip accommodating layer 3 is formed on at least one side of the chip accommodating groove 19, and an electrical connection structure electrically connected to the first conductive column 7 is formed on the top surface of the chip accommodating layer 3;

[0065] S6, the carrier board 1 and part of the first conductive layer 2 are removed, so that the pins on the bottom surface of the multi-sided pin chip 20 are conductive through the remaining first conductive layer 2 and the first conductive column 7 outside, and a plastic encapsulation layer 8 is formed on the first conductive layer 2.

[0066] ​The multi-sided pin chip 20 of this embodiment includes a top surface, a bottom surface, and four side surfaces, which can be divided into a front side surface, a rear side surface, a left side surface, and a right side surface. The top surface, the bottom surface, and two mutually symmetrical side surfaces (for example, the front side surface and the rear side surface, or the left side surface and the right side surface) of the multi-sided pin chip 20 are each provided with a pin. That is, the multi-sided pin chip 20 of this embodiment is provided with pins on four surfaces.

[0067] The first conductive layer 2 of step S1 is preferably a copper foil. The first conductive layer 2 can be separated from the carrier plate 1. Specifically, the first conductive layer 2 of this embodiment can be a layer structure that is self-provided on the carrier plate 1 and whose bonding surface can be detached. The first conductive layer 2 of this embodiment can also be a layer structure that is formed on the carrier plate 1 based on a physical vapor deposition or chemical vapor deposition process. The chip accommodating layer 3 of step S1 can be a photoresist layer or a dry film layer with photosensitive properties. The chip accommodating layer 3 of step S1 is provided with a plurality of chip accommodating grooves 19. It should be understood that the first conductive layer 2 within the chip accommodating grooves 19 is exposed, and the first conductive layer 2 outside the chip accommodating grooves 19 is shielded by the chip accommodating layer 3. When the first conductive layer 2 is a layer structure that is formed on the carrier plate 1 based on a physical vapor deposition or chemical vapor deposition process, the specific process of step S1 can be as follows: forming a temporary bonding glue layer on the carrier plate 1; forming the first conductive layer 2 on the temporary bonding glue layer based on a physical vapor deposition or chemical vapor deposition process; forming the chip accommodating layer 3 on the first conductive layer 2 based on an existing photoresist layer forming process or dry film forming process; exposing and developing the chip accommodating layer 3 using a second predetermined pattern mask to form a plurality of chip accommodating grooves 19 on the chip accommodating layer 3, the size of the chip accommodating grooves 19 being greater than the size of the multi-sided pin chip 20. When the first conductive layer 2 is a layer structure that is self-provided on the carrier plate 1 and whose bonding surface can be detached, the specific process of step S1 can be as follows: forming the chip accommodating layer 3 on the side of the first conductive layer 2 that is away from the carrier plate 1 based on an existing photoresist layer forming process or dry film forming process; and exposing and developing the chip accommodating layer 3 using a second predetermined pattern mask to form a plurality of chip accommodating grooves 19 on the chip accommodating layer 3. It should be understood that when the first conductive layer 2 is a layer structure that is formed on the carrier plate 1 based on a physical vapor deposition or chemical vapor deposition process, step S6 also needs to remove the temporary bonding glue layer.

[0068] Step S2 can utilize the existing chip picking and chip mounting process to mount the bottom surface of the multi-sided pin chip 20 downward (towards the carrier plate 1) on the first conductive layer 2 in the chip accommodating groove 19, and each chip accommodating groove 19 can be mounted with one multi-sided pin chip 20. The chip accommodating groove 19 can assist in positioning when the bottom surface of the multi-sided pin chip 20 is mounted downward on the first conductive layer 2, so that the mounting precision of the multi-sided pin chip 20 can be effectively improved. Preferably, before the bottom surface of the multi-sided pin chip 20 is mounted downward on the first conductive layer 2 in the chip accommodating groove 19, step S2 first fills the chip accommodating groove 19 with conductive adhesive (a composite material composed of a resin matrix, conductive particles, dispersing additives, and auxiliary agents). It should be understood that after the bottom surface of the multi-sided pin chip 20 is mounted downward on the first conductive layer 2 in the chip accommodating groove 19, the pins on the bottom surface of the multi-sided pin chip 20 are electrically connected to the first conductive layer 2, i.e., the pins on the bottom surface are in electrical conduction with the first conductive layer 2.

[0069] Since step S4 forms two second conductive layers 5 that are respectively electrically connected to the pins on the two side surfaces of the multi-sided pin chip 20, if the first conductive layer 2 is in contact with the second conductive layer 5 (i.e., the first conductive layer 2 is electrically connected to the second conductive layer 5), the pins on the side surfaces of the multi-sided pin chip 20 will be interconnected with the pins on the bottom surface of the multi-sided pin chip 20, i.e., cannot be electrically connected only to the pins on the side surfaces or the bottom surface of the multi-sided pin chip 20. Therefore, step S3 forms a first insulating layer 4 between the multi-sided pin chip 20 and the chip accommodating groove 19 to avoid electrical connection between the first conductive layer 2 and the second conductive layer 5, thereby avoiding the situation where the pins on the side surfaces of the multi-sided pin chip 20 are interconnected with the pins on the bottom surface of the multi-sided pin chip 20. After step S3 is performed, the external voltage can be electrically connected only to the pins on the side surfaces or the bottom surface of the multi-sided pin chip 20. Step S3 can utilize the existing insulating layer forming process to form the first insulating layer 4 between the multi-sided pin chip 20 and the chip accommodating groove 19. It should be understood that the height of the first insulating layer 4 in this embodiment is less than the minimum height of the pins on the side surfaces of the multi-sided pin chip 20, i.e., the first insulating layer 4 in this embodiment does not cover the pins on the side surfaces of the multi-sided pin chip 20.

[0070] Step S4 can form two second conductive layers 5 on the first insulating layer 4 based on a physical vapor deposition or chemical vapor deposition process, which are respectively electrically connected with the pins on the two sides, i.e. each second conductive layer 5 is electrically connected with the pins on one side of the multi-sided pin chip 20, for example, the two second conductive layers 5 are respectively electrically connected with the pins on the left side and the right side. After forming the second conductive layer 5, step S4 can form a second insulating layer 6 between the two second conductive layers 5 by using an existing insulating layer forming process to avoid the electrical connection between the two second conductive layers 5, so as to avoid the interconnection of the pins on the two sides of the multi-sided pin chip 20, i.e. after step S4 is performed, the external voltage can be electrically connected with only the pins on one side of the multi-sided pin chip 20. It should be understood that since the second conductive layer 5 is electrically connected with the pins on the side of the multi-sided pin chip 20, step S4 is equivalent to leading out the pins on the side of the multi-sided pin chip 20 to the top surface of the multi-sided pin chip 20 by using the second conductive layer 5.

[0071] Step S5 forms first conductive pillars 7 through the chip receiving layer 3 at least one side of the chip receiving recess 19, preferably, the embodiment forms first conductive pillars 7 at both sides of the chip receiving recess 19 to enhance the heat conduction capability of the multi-sided pin package structure, the first conductive pillars 7 can be electrically connected with the first conductive layer 2, since the pins on the bottom surface of the multi-sided pin package 20 are electrically connected with the first conductive layer 2 after step S2 is performed, the application is equivalent to leading the pins on the bottom surface of the multi-sided pin package 20 out to the top surface of the multi-sided pin package 20 through the first conductive layer 2 and the first conductive pillars 7. Step S5 can form an electrical connection structure on the chip receiving layer 3 which is electrically connected with the first conductive pillars 7 by using the existing electrical connection structure forming process, i.e. the two ends of the first conductive pillars 7 are connected with the electrical connection structure and the first conductive layer 2 respectively. Since the first conductive layer 2 of the embodiment can be separated from the carrier board 1, step S6 can remove the carrier board 1 by separating the first conductive layer 2 from the carrier board 1, after the carrier board 1 is removed, step S6 can remove part of the first conductive layer 2 by etching, the first conductive pillars 7 can be electrically connected with the pins on the bottom surface of the multi-sided pin package 20 through the remaining first conductive layer 2, step S6 can form the plastic encapsulation layer 8 on the first conductive layer 2 by using the existing plastic encapsulation layer 8 forming process. It should be understood that since the electrical connection structure formed by step S5 can seal and protect the multi-sided pin package 20 and the end of the first conductive pillars 7 which is far away from the first conductive layer 2, step S6 only needs to form the plastic encapsulation layer 8 on the first conductive layer 2 to protect the end of the first conductive pillars 7 which is close to the first conductive layer 2. It should also be understood that since the top surface of the chip receiving layer 3 (the side of the chip receiving layer 3 which is far away from the first conductive layer 2) is upward during the execution of steps S1-S5, and step S6 needs to remove the carrier board 1 and part of the first conductive layer 2 and form the plastic encapsulation layer 8 on the first conductive layer 2, in order to facilitate operation, the embodiment can first flip the entire structure to make the top surface of the chip receiving layer 3 downward before step S6 is performed.

[0072] The application provides a multi-surface pin chip packaging method. The bottom surface of the multi-surface pin chip 20 is attached to the first conductive layer 2 in the chip accommodating groove 19, and the first insulating layer 4 is formed between the multi-surface pin chip 20 and the chip accommodating groove 19. The two second conductive layers 5 are formed on the first insulating layer 4 and are electrically connected to the pins on the two side surfaces, respectively. The second insulating layer 6 is formed between the two second conductive layers 5. The first conductive column 7 is formed on at least one side of the chip accommodating groove 19. The electrical connection structure is electrically connected to the first conductive column 7 on the top surface of the chip accommodating layer 3. Since the two second conductive layers 5 can respectively lead the pins on the two side surfaces of the multi-surface pin chip 20 to the top surface of the multi-surface pin chip 20, and the first conductive layer 2 and the first conductive column 7 can also lead the pins on the bottom surface of the multi-surface pin chip 20 to the top surface of the multi-surface pin chip 20, the application can lead the pins on the multiple surfaces of the multi-surface pin chip 20 to the same plane through the first conductive layer 2, the second conductive layer 5 and the first conductive column 7, that is, the application does not need to use a wire bonding device to lead the pins on the multiple surfaces of the multi-surface pin chip 20 to the same plane, thereby effectively solving the problems of high packaging cost of the multi-surface pin chip 20 due to the need to use the wire bonding device to lead the pins on the multiple surfaces of the multi-surface pin chip 20 to the same plane, and low reliability of the packaging structure obtained by the multi-surface pin chip packaging method due to the easy breakage and falling off of the lead wire and the permanent damage to the pad interface of the multi-surface pin chip 20.

[0073] In some embodiments, step S5 comprises:

[0074] S51, forming the first conductive column 7 on at least one side of the chip accommodating groove 19, and forming the first redistribution layer electrically connected to the first conductive column 7, the pins on the top surface of the multi-surface pin chip 20 and the two second conductive layers 5 on the top surface of the chip accommodating layer 3;

[0075] S52, forming the solder ball 22 on the first redistribution layer.

[0076] Step S51 can use the existing redistribution layer forming process to form the first redistribution layer electrically connected to the first conductive column 7, the top surface of the multi-surface pin chip 20 and the two second conductive layers 5 on the top surface of the chip accommodating layer 3. Step S52 can use the existing ball planting process to form the solder ball 22 on the first redistribution layer. It should be understood that the electrical connection structure of this embodiment includes the first redistribution layer and the solder ball 22, and the pins on the top surface, the bottom surface and the two side surfaces of the multi-surface pin chip 20 correspond to different solder balls 22, that is, this embodiment can make the external voltage electrically connected to the pins on any one of the top surface, the bottom surface and the two side surfaces of the multi-surface pin chip 20.

[0077] In some embodiments, step S51 comprises:

[0078] S511, forming a first patterned passivation film layer 9 on the top surface of the chip accommodating layer 3, and forming a first conductive column 7 on at least one side of the chip accommodating groove 19;

[0079] S512, sequentially forming a metal seed layer and a metal copper layer on the top surface of the chip accommodating layer 3 and the top surface of the first conductive column 7 based on the first patterned passivation film layer 9, so as to form a first metal wiring layer 10;

[0080] S513, forming a first patterned photosensitive film layer 11 on the first metal wiring layer 10, and etching the first metal wiring layer 10 based on the first patterned photosensitive film layer 11, so as to remove the first metal wiring layer 10 outside the first conductive column 7, the top surface of the multi-faceted pin chip 20 and the two second conductive layers 5;

[0081] S514, removing the first patterned photosensitive film layer 11, and forming a second patterned passivation film layer 12 on the first patterned passivation film layer 9;

[0082] S515, forming a third patterned passivation film layer 13 on the second patterned passivation film layer 12, and sequentially forming a metal seed layer and a metal copper layer on the first metal wiring layer 10 based on the third patterned passivation film layer 13, so as to form a second metal wiring layer 14.

[0083] The first patterned passivation film layer 9 of step S511 includes a plurality of openings, which are respectively opposite to the first conductive column 7, the second conductive layer 5 and the pins on the top surface of the multi-faceted pin chip 20, that is, the first patterned passivation film layer 9 of this embodiment will not shield the first conductive column 7, the second conductive layer 5 and the pins on the top surface of the multi-faceted pin chip 20. The first redistribution layer of this embodiment includes the first patterned passivation film layer 9, the first metal wiring layer 10, the second patterned passivation film layer 12, the third patterned passivation film layer 13 and the second metal wiring layer 14. Step S512 first forms a metal seed layer on the top surface of the chip accommodating layer 3 and the top surface of the first conductive column 7, and then forms a metal copper layer on the metal seed layer. Step S515 first forms a metal seed layer on the first metal wiring layer 10, and then forms a metal copper layer on the metal seed layer. Since the metal seed layer can increase the bonding force between the metal copper layer and the contact surface, this embodiment can effectively avoid the situation that the metal copper layer falls off due to the small bonding force between the metal copper layer and the contact surface.

[0084] In some embodiments, S511 includes:

[0085] S5111, forming a first passivation film layer on the top surface of the chip accommodating layer 3;

[0086] S5112, etching the first passivation film layer based on a lithography process or a laser process using a first preset pattern mask to form a first patterned passivation film layer 9 on the top surface of the chip accommodating layer 3;

[0087] S5113, forming the first conductive column 7 penetrating through the chip accommodating layer 3 on at least one side of the chip accommodating groove 19 based on the etching process and the electroplating process using the first patterned passivation film layer 9.

[0088] The first preset pattern mask of step S5112 is a mask with a preset pattern, and etching the first passivation film layer is equivalent to transferring the preset pattern on the first preset pattern mask to the first passivation film layer to form a plurality of openings (including the opening opposite to the first conductive column 7) on the first passivation film layer. The specific process of step S5113 can be: etching the chip accommodating layer 3 based on the etching process using the opening opposite to the first conductive column 7 in the first patterned passivation film layer 9 to form a through hole on at least one side of the chip accommodating groove 19; filling the through hole with conductive metal based on the electroplating process to form the first conductive column 7.

[0089] In some embodiments,

[0090] Step S6 includes:

[0091] S61, removing the carrier plate 1 and etching the first conductive layer 2 based on a dry etching process or a wet etching process to remove part of the first conductive layer 2 and make the pins on the bottom surface of the multi-pin chip 20 conductive with the first conductive column 7 outside through the remaining first conductive layer 2;

[0092] S62, forming a plastic encapsulation layer 8 on the first conductive layer 2.

[0093] The dry etching process and the wet etching process of step S61 can be existing etching processes, which will not be discussed in detail here.

[0094] In some embodiments, step S5 includes:

[0095] S51', forming the first conductive column 7 penetrating through the chip accommodating layer 3 on at least one side of the chip accommodating groove 19, and forming the second conductive column 23 penetrating through the chip accommodating layer 3 on any one side of the chip accommodating groove 19;

[0096] S52', forming an electrical connection structure electrically connected with the first conductive column 7 and the second conductive column 23 on the top surface of the chip accommodating layer 3;

[0097] Step S6 further includes a step executed between step S61 and step S62:

[0098] S63, forming a fourth patterned passivation film layer 15 on the first conductive layer 2.

[0099] S64, forming a third conductive layer 16 electrically connected with the second conductive column 23 based on the fourth patterned passivation film layer 15;

[0100] S65, forming a fifth patterned passivation film layer 17 on the fourth patterned passivation film layer 15, and forming a fourth conductive layer 18 electrically connected with the third conductive layer 16 based on the fifth patterned passivation film layer 17;

[0101] S66, attaching the active surface of the regular chip 21 downward to the fourth conductive layer 18;

[0102] The step S62 comprises:

[0103] S621, plastic packaging the regular chip 21 to form a plastic packaging layer 8 on the first conductive layer 2.

[0104] The regular chip 21 of the embodiment is a chip with different performance from the multi-face pin chip 20, and the embodiment is equivalent to integrating chips with different performance in the same packaging structure. The prior art can integrate chips with different performance in the same packaging structure by first attaching chips with different performance to different through silicon interposers, and then using the through silicon interposer to lead out and interconnect the pins of the chips with different performance. Since the prior art needs to use multiple through silicon interposers to integrate chips with different performance in the same packaging structure, and the present application can integrate chips with different performance in the same packaging structure by cooperation of the first conductive layer 2, the second conductive layer 5, the first conductive column 7, the third conductive layer 16, the fourth conductive layer 18 and the second conductive column 23, the present application does not need to use multiple through silicon interposers, i.e. the present application is equivalent to realizing a three-dimensional fan-out packaging structure without using a through silicon interposer, thereby effectively reducing the packaging cost and volume of the three-dimensional fan-out packaging structure.

[0105] In some embodiments, the step S1 comprises:

[0106] S11, forming an adhesive layer on the side of the first conductive layer 2 away from the carrier board 1;

[0107] S12, forming a second patterned photosensitive film layer on the adhesive layer;

[0108] S13, etching the adhesive layer based on the second patterned photosensitive film layer to form a chip accommodating layer 3 with a plurality of chip accommodating grooves 19 formed thereon.

[0109] The embodiment is equivalent to taking the adhesive layer as the chip accommodating layer 3. Since the adhesive layer has the advantages of high reliability and light weight, the embodiment can effectively improve the reliability of the multi-sided pin chip packaging structure and reduce the weight of the multi-sided pin chip packaging structure. The second patterned photosensitive film layer of the embodiment is provided with a preset pattern. Etching the adhesive layer based on the second patterned photosensitive film layer is equivalent to transferring the preset pattern on the second patterned photosensitive film layer to the adhesive layer. It should be understood that the preset pattern on the second patterned photosensitive film layer is the same as the shape of the chip accommodating groove 19.

[0110] In some embodiments, step S3 comprises:

[0111] S31, filling the gap between the multi-sided pin chip 20 and the chip accommodating groove 19 with underfill glue to form a first insulating layer 4.

[0112] The embodiment can fill the gap between the multi-sided pin chip 20 and the chip accommodating groove 19 with underfill glue by manual means or by using existing underfill glue filling processes.

[0113] In some embodiments, the left side and the right side of the multi-sided pin chip 20 are both provided with pins. Step S4 comprises:

[0114] S41, filling the gap between the left side and the chip accommodating groove 19 and the gap between the right side and the chip accommodating groove 19 with conductive glue or conductive metal to form two second conductive layers 5 on the first insulating layer 4, which are respectively electrically connected to the pins on the two sides;

[0115] S42, filling the gap between the front side of the multi-sided pin chip 20 and the chip accommodating groove 19 and the gap between the back side of the multi-sided pin chip 20 and the chip accommodating groove 19 with underfill glue to form a second insulating layer 6 between the two second conductive layers 5.

[0116] The embodiment is equivalent to first forming the two second conductive layers 5 and then forming the second insulating layer 6. It should be understood that the embodiment can also first form the second insulating layer 6 and then form the second conductive layer 5, i.e., the embodiment can first perform step S42 and then perform step S41.

[0117] From the above, the application provides a multi-face pin chip packaging method, the bottom surface of the multi-face pin chip 20 is attached to the first conductive layer 2 in the chip accommodating groove 19, and the first insulating layer 4 is formed between the multi-face pin chip 20 and the chip accommodating groove 19, the two second conductive layers 5 respectively electrically connected with the pins on the two side surfaces are formed on the first insulating layer 4, the second insulating layer 6 is formed between the two second conductive layers 5, the first conductive column 7 is formed on at least one side of the chip accommodating groove 19, and the electrical connection structure electrically connected with the first conductive column 7 is formed on the top surface of the chip accommodating layer 3. Since the application can lead out the pins on the two side surfaces of the multi-face pin chip 20 to the top surface of the multi-face pin chip 20 through the two second conductive layers 5, and the application can also lead out the pins on the bottom surface of the multi-face pin chip 20 to the top surface of the multi-face pin chip 20 through the first conductive layer 2 and the first conductive column 7, the application is equivalent to leading out the pins on the multiple surfaces of the multi-face pin chip 20 to the same plane through the first conductive layer 2, the second conductive layer 5 and the first conductive column 7, that is, the application does not need to use a wire bonding device to lead out the pins on the multiple surfaces of the multi-face pin chip 20 to the same plane, thereby effectively solving the problems of high packaging cost of the multi-face pin chip 20 due to the need to use a wire bonding device to lead out the pins on the multiple surfaces of the multi-face pin chip 20 to the same plane, and low reliability of the packaging structure obtained by the multi-face pin chip packaging method due to the easy breakage and falling off of the lead wire and the permanent damage to the pad interface of the multi-face pin chip 20.

[0118] In the second aspect, the application further provides a multi-face pin chip packaging structure made by the multi-face pin chip packaging method provided in the first aspect.

[0119] The application embodiment provides a multi-face pin chip packaging structure made by the multi-face pin chip packaging method provided in the first aspect. The principle of the multi-face pin chip packaging structure of the embodiment is the same as that of the multi-face pin chip packaging method provided in the first aspect, which will not be discussed in detail here.

[0120] From the above, it can be seen that the multi-sided pin chip packaging structure provided by the present application can lead out the pins on the two side surfaces of the multi-sided pin chip 20 to the top surface of the multi-sided pin chip 20 through the two second conductive layers 5, and lead out the pins on the bottom surface of the multi-sided pin chip 20 to the top surface of the multi-sided pin chip 20 through the first conductive layer 2 and the first conductive column 7. Therefore, the present application is equivalent to leading out the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane through the first conductive layer 2, the second conductive layer 5 and the first conductive column 7, that is, the present application does not need to use wire bonding equipment to lead out the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane, thereby effectively solving the problems of high packaging cost of the multi-sided pin chip 20 due to the need to use wire bonding equipment to lead out the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane, and low reliability of the multi-sided pin chip packaging structure due to the easy disconnection and falling off of the leads and permanent damage to the solder pad interface of the multi-sided pin chip 20.

[0121] As can be seen from the above, the present application provides a multi-faceted pin chip packaging method and packaging structure, which first attaches the bottom surface of the multi-faceted pin chip 20 downward on the first conductive layer 2 in the chip accommodating groove 19, and forms a first insulating layer 4 between the multi-faceted pin chip 20 and the chip accommodating groove 19, and then forms two second conductive layers 5 electrically connected to the pins on the two side surfaces on the first insulating layer 4, and forms a second insulating layer 6 between the two second conductive layers 5, and then forms a first conductive column 7 on at least one side of the chip accommodating groove 19, and forms an electrical connection structure electrically connected to the first conductive column 7 on the top surface of the chip accommodating layer 3. Since the present application can lead the pins on the two side surfaces of the multi-faceted pin chip 20 to the top surface of the multi-faceted pin chip 20 through the two second conductive layers 5, the present application Please also be able to lead the pins on the bottom surface of the multi-sided pin chip 20 to the top surface of the multi-sided pin chip 20 through the first conductive layer 2 and the first conductive column 7. Therefore, this application is equivalent to leading the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane through the first conductive layer 2, the second conductive layer 5 and the first conductive column 7, that is, this application does not need to use wire bonding equipment to lead the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane, thereby effectively solving the problems of high packaging cost of the multi-sided pin chip 20 due to the need to use wire bonding equipment to lead the pins on multiple surfaces of the multi-sided pin chip 20 to the same plane, and low reliability of the packaging structure obtained by the multi-sided pin chip packaging method due to the easy disconnection and falling off of the leads and permanent damage to the pad interface of the multi-sided pin chip 20.

[0122] In the embodiments provided in the present application, it should be understood that, in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between the entities or operations.

[0123] The above only describes the embodiments of the present application and is not used to limit the protection scope of the present application. Various modifications and changes can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for packaging a multi-sided pin chip, wherein pins are provided on the top surface, the bottom surface and two mutually symmetrical side surfaces of the multi-sided pin chip, characterized in that: The multi-sided pin chip packaging method comprises the following steps: S1. Forming a chip accommodating layer on a side of the first conductive layer away from the carrier, wherein the chip accommodating layer is provided with a plurality of chip accommodating grooves; S2. Attach the multi-faceted pin chip with its bottom surface facing downward onto the first conductive layer in the chip accommodating groove; S3, forming a first insulating layer between the multi-faceted pin chip and the chip accommodating groove; S4, forming two second conductive layers on the first insulating layer, respectively electrically connected to the pins on two side surfaces of the multi-faceted pin chip, and forming a second insulating layer between the two second conductive layers; S5. Forming a first conductive pillar penetrating the chip accommodating layer on at least one side of the chip accommodating groove, and forming an electrical connection structure electrically connected to the first conductive pillar on a top surface of the chip accommodating layer; S6. Remove the carrier and part of the first conductive layer so that the pins on the bottom surface of the multi-sided pin chip are connected to the first conductive pillars outside thereof through the remaining first conductive layer, and form a plastic packaging layer on the first conductive layer.

2. The multi-sided pin chip packaging method according to claim 1, characterized in that: Step S5 includes: S51, forming a first conductive pillar penetrating the chip accommodating layer on at least one side of the chip accommodating groove, and forming a first redistribution layer electrically connected to the first conductive pillar, the top surface of the multi-faceted pin chip, and the two second conductive layers on the top surface of the chip accommodating layer; S52 , forming solder balls on the first redistribution layer.

3. The multi-sided pin chip packaging method according to claim 2, characterized in that: Step S51 includes: S511, forming a first patterned passivation film layer on the top surface of the chip accommodating layer, and forming a first conductive pillar on at least one side of the chip accommodating groove; S512, forming a metal seed layer and a metal copper layer in sequence on the top surface of the chip accommodating layer and the top surface of the first conductive pillar based on the first patterned passivation film layer to form a first metal wiring layer; S513, forming a first patterned photosensitive film layer on the first metal wiring layer, and etching the first metal wiring layer based on the first patterned photosensitive film layer to remove the first metal wiring layer located outside the first conductive pillars, the pins on the top surface of the multi-faceted pin chip, and the two second conductive layers; S514, removing the first patterned photosensitive film layer, and forming a second patterned passivation film layer on the first patterned passivation film layer; S515 , forming a third patterned passivation film layer on the second patterned passivation film layer, and sequentially forming a metal seed layer and a metal copper layer on the first metal wiring layer based on the third patterned passivation film layer to form a second metal wiring layer.

4. The multi-sided pin chip packaging method according to claim 3, characterized in that: Step S511 includes: S5111, forming a first passivation film layer on the top surface of the chip accommodating layer; S5112, etching the first passivation film layer using a first preset pattern mask based on a photolithography process or a laser process to form a first patterned passivation film layer on the top surface of the chip accommodating layer; S5113 , using the first patterned passivation film layer to form a first conductive pillar penetrating the chip accommodating layer on at least one side of the chip accommodating groove based on an etching process and an electroplating process.

5. The multi-sided pin chip packaging method according to claim 1, characterized in that: Step S6 includes: S61, removing the carrier, and etching the first conductive layer based on a dry etching process or a wet etching process to remove a portion of the first conductive layer and connect the pins on the bottom surface of the multi-faceted pin chip to the first conductive pillars outside the first conductive layer through the remaining first conductive layer; S62: Form a plastic packaging layer on the first conductive layer.

6. The multi-sided pin chip packaging method according to claim 5, characterized in that: Step S5 includes: S51′, forming a first conductive pillar penetrating the chip accommodating layer on at least one side of the chip accommodating groove, and forming a second conductive pillar penetrating the chip accommodating layer on any side of the chip accommodating groove; S52′, forming an electrical connection structure electrically connected to the first conductive pillar and the second conductive pillar on the top surface of the chip accommodating layer; Step S6 also includes the following steps performed between step S61 and step S62: S63, forming a fourth patterned passivation film layer on the first conductive layer; S64, forming a third conductive layer electrically connected to the second conductive pillar based on the fourth patterned passivation film layer; S65, forming a fifth patterned passivation film layer on the fourth patterned passivation film layer, and forming a fourth conductive layer electrically connected to the third conductive layer based on the fifth patterned passivation film layer; S66, attaching the conventional chip with its active surface facing downward onto the fourth conductive layer; Step S62 includes: S621 , performing plastic encapsulation on the conventional chip to form a plastic encapsulation layer on the first conductive layer.

7. The multi-sided pin chip packaging method according to claim 1, characterized in that: Step S1 includes: S11, forming an adhesive layer on a side of the first conductive layer away from the carrier; S12, forming a second patterned photosensitive film layer on the adhesive layer; S13. Etching the adhesive layer based on the second patterned photosensitive film layer to form a chip accommodating layer having a plurality of chip accommodating grooves thereon.

8. The multi-sided pin chip packaging method according to claim 1, characterized in that: Step S3 includes: S31 , filling the gap between the multi-faceted pin chip and the chip accommodating groove with underfill to form a first insulating layer.

9. The multi-sided pin chip packaging method according to claim 1, characterized in that: The left side and the right side of the multi-sided pin chip are both provided with pins, and step S4 includes: S41, filling the gap between the left side surface and the chip accommodating groove and the gap between the right side surface and the chip accommodating groove with conductive glue or conductive metal to form two second conductive layers on the first insulating layer that are electrically connected to the pins on the two side surfaces respectively; S42, filling the gap between the front side of the multi-faceted pin chip and the chip accommodating groove and the gap between the back side of the multi-faceted pin chip and the chip accommodating groove with underfill to form a second insulating layer between the two second conductive layers.

10. A multi-faceted pin chip packaging structure, characterized in that: The multi-sided pin chip packaging structure is manufactured by the multi-sided pin chip packaging method according to any one of claims 1 to 9.

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