A method for preparing a C-SOI back cavity through hole

Abstract

The present invention relates to a method for preparing a C-SOI back cavity through hole, comprising: step S1, providing a first substrate to be etched; step S2, forming a hard mask on a first selected surface and a second selected surface of the first substrate, and etching a portion of the hard mask layer on the first selected surface and the second selected surface respectively, thereby respectively exposing a portion of the substrate layer corresponding to the position; step S3, shallowly etching the exposed substrate layer of the first selected surface, and deeply etching the exposed substrate layer of the second selected surface, wherein the etching positions of the first selected surface and the second selected surface correspond to each other and are not connected; step S4, providing a second substrate; step S5, aligning and bonding the second selected surface of the first substrate and any surface of the second substrate; step S6, etching the remaining substrate thickness on the etched position of the first selected surface of the first substrate to form a silicon back cavity through hole. The present invention has the effect of shortening the process time, reducing the influence of etching load, and making etching more uniform.

Description

Technical Field

[0001] The invention relates to the technical field of micro-electromechanical systems, and in particular to a method for preparing a C-SOI back cavity through hole. Background Art

[0002] In recent years, various technologies have steadily moved towards intelligence, greatly promoting the rapid development of micro-electromechanical systems. Some MEMS process structures use SOI wafers for process technology, such as capacitive micro-accelerometers. After the structural layer is etched, the substrate layer needs to be deeply etched to obtain a through hole, and then DHF release is performed. Therefore, higher requirements are placed on the silicon back cavity through-hole process.

[0003] In the manufacturing process of MEMS inertial device chip technology, most processes require silicon back cavity through holes, that is, after the device layer process is completed, the back cavity needs to be etched through holes, and a barrier layer is set between the device layer and the etched through hole position, and the barrier layer serves as the etching stop layer. In the existing deep etching process, due to the problem of etching selectivity, only thick hard masks or composite masks of photoresist and SiO2 or Si3N4 can be used.

[0004] The above schemes have the following defects: the thick hard mask leads to a long process time, and causes excessive stress and increased substrate warpage; for the MEMS through-hole etching process, the only way is to increase the over-etching amount by designing and preparing a barrier layer, which results in long etching time, poor heat dissipation of the substrate, and a sharp drop in the selectivity; during the deep etching process, as the size of the device changes, there are serious difficulties in the design of the etching load, and the etching uniformity can deviate to ≥4%, and the design is often far from the actual situation. Summary of the invention

[0005] In order to shorten the process time, reduce the influence of etching load, and make etching more uniform, the present invention provides a method for preparing a C-SOI back cavity through hole.

[0006] The present invention provides a method for preparing a C-SOI back cavity through hole, which adopts the following technical solution:

[0007] A method for preparing a C-SOI back cavity through hole comprises the following steps:

[0008] Step S1, providing a first substrate to be etched;

[0009] Step S2, forming a hard mask on the first selected surface and the second selected surface of the first substrate, and etching a portion of the hard mask layer on the first selected surface and the second selected surface respectively, thereby exposing a portion of the substrate layer at a corresponding position respectively;

[0010] Step S3, shallowly etching the exposed substrate layer of the first selected surface, and deeply etching the exposed substrate layer of the second selected surface, wherein the etching positions of the first selected surface and the second selected surface correspond to each other and are not connected;

[0011] Step S4, providing a second substrate;

[0012] Step S5, aligning and bonding the second selected surface of the first substrate and any surface of the second substrate;

[0013] Step S6, performing residual substrate thickness etching on the etched position of the first selected surface of the first substrate to form a silicon back cavity through hole.

[0014] By adopting the above technical scheme, deep etching is performed on the second selected surface of the first substrate, and the deep etching is for completing a part of the through-hole preparation. Shallow etching is performed on the first selected surface of the first substrate, and the shallow etching is for positioning on the first selected surface to ensure that after the first substrate and the second substrate are bonded, the position required for etching can still be accurately obtained; after bonding, the space generated after the deep etching of the second selected surface exists as a blocking structure, and etching is performed from the shallowly etched position at this time to obtain a silicon back cavity through-hole. Since the etching is divided into two times, the thickness of the hard mask is reduced compared with the original, reducing the adverse factors brought by the thick hard mask. At the same time, the etching does not need to be too long, so that the heat dissipation performance of the substrate is better. Due to the etching on both sides, the influence of the etching load is reduced, and the etching uniformity is better.

[0015] Optionally, the step of exposing the portion of the substrate layer corresponding to the position in step S2 includes: performing a double-sided photolithography overlay process on the first substrate to respectively etch the portion of the hard mask layer corresponding to the position to expose the portion of the substrate layer corresponding to the position.

[0016] By adopting the above technical solution, the two sides of the first substrate are processed in the same way by using a double-sided photolithography process, so as to obtain the partial hard mask layer corresponding to the position, and then obtain the partial substrate layer corresponding to the position.

[0017] Optionally, the specific steps of step S2 include:

[0018] forming a photoresist layer on the hard mask layer of the first selection surface and the second selection surface respectively;

[0019] exposing and developing the photoresist layer respectively to expose a portion of the hard mask layer;

[0020] The exposed hard mask layers of the first selected surface and the second selected surface are etched respectively, and portions of the substrate layer corresponding to the positions are exposed respectively.

[0021] Optionally, an etching selectivity ratio between the first substrate and the hard mask layer is 100:1, and the hard mask includes a SiO2 hard mask or a Si3N4 hard mask.

[0022] By adopting the above technical solution, compared with the existing solution, a hard mask of the same material is used, but since the first substrate is double-sided etched, the hard mask layer is thinner than the existing solution, avoiding the adverse effects caused by the hard mask layer being too thick.

[0023] Optionally, a thickness selection ratio of the photoresist layer to the hard mask layer is (1-1.3):1.

[0024] By adopting the above technical solution, the required part of the hard mask layer can be better exposed during the processing.

[0025] Optionally, in step 3, the ratio of the etching depth of the second selected surface to the first substrate thickness is 1:2, and the etching depth of the first selected surface is much smaller than the etching depth of the second selected surface.

[0026] By adopting the above technical solution, the shallow etching of the first selected surface serves as a mark, and the deep etching depth occupies half of the thickness of the first substrate, so that the etching after bonding is basically consistent with the deep etching in step 3 in time and process, so that the etching uniformity is better. Compared with the one-time etching process, the etching time of each etching is shortened, and the heat dissipation performance of the substrate is better.

[0027] Optionally, the first substrate is a dry-etched substrate sheet.

[0028] Optionally, the etching method used in step 6 is the same as that in step 3.

[0029] Optionally, the etching in step 3 is to use SPTS deep inductively coupled plasma dry etching to the exposed substrate structure on the first substrate to complete the etching of the surface structure layer of the first substrate; the etching includes a cyclic passivation step and an etching step.

[0030] Optionally, the bonding process uses an AML bonding machine; an infrared camera is used to align the marks between the substrates, nitrogen plasma is used for surface activation, pressure is applied for a period of time under a vacuum degree of 1E-3 for room temperature bonding, and annealing is performed in a nitrogen environment after bonding.

[0031] In summary, the present invention has the following beneficial technical effects:

[0032] 1. The two-time double-sided deep silicon etching method is adopted, which greatly reduces the mask thickness while maintaining the original etching selectivity, and reduces the adverse factors caused by the thick mask;

[0033] 2. After bonding, since the bonding side has been etched, the etched position serves as an etching barrier layer structure, greatly reducing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a flow chart of the method for preparing the C-SOI back cavity through hole in the embodiment of the present application. DETAILED DESCRIPTION

[0035] The following is combined with Figure 1 The present invention is described in further detail.

[0036] The embodiment of the present invention discloses a method for preparing a C-SOI back cavity through hole. Figure 1 , a method for preparing a C-SOI back cavity through hole comprises the following steps:

[0037] Step S1, providing a first substrate to be etched;

[0038] Step S2, forming a hard mask on the first selected surface and the second selected surface of the first substrate, and etching a portion of the hard mask layer on the first selected surface and the second selected surface respectively, thereby exposing a portion of the substrate layer at a corresponding position respectively;

[0039] Step S3, shallowly etching the exposed substrate layer of the first selected surface, and deeply etching the exposed substrate layer of the second selected surface, wherein the etching positions of the first selected surface and the second selected surface correspond to each other and are not connected;

[0040] Step S4, providing a second substrate;

[0041] Step S5, aligning and bonding the second selected surface of the first substrate and any surface of the second substrate;

[0042] Step S6, performing residual substrate thickness etching on the etched position of the first selected surface of the first substrate to form a silicon back cavity through hole.

[0043] The first substrate provided in step S1 is a dry-etched substrate sheet. In this embodiment, the step of providing the first substrate includes:

[0044] a. Prepare silicon wafer materials: The prepared silicon wafer specifications are N-type 100 crystal orientation, 400μm thick, and 0.002-0.005Ω.cm resistivity. Use a laser marking machine to mark and number the silicon wafer, where the marked surface is the back and the non-marked surface is the front, for subsequent data recording.

[0045] b. Cleaning the silicon wafer: Before use, perform standard RCA cleaning on the silicon wafer. Clean the silicon wafer in a mixed solution of sulfuric acid: hydrogen peroxide = 4:1 for 5 min-8 min, and rinse with deionized water; clean it in a mixed solution of ammonia: hydrogen peroxide: deionized water = 1:1:5 for 5 min-8 min, and rinse with deionized water; spin dry.

[0046] In step S2, the first selected surface is the front surface (non-marking surface), the second selected surface is the back surface (marking surface), the etching selectivity of the first substrate and the hard mask layer is 100:1, and the hard mask includes a SiO2 hard mask or a Si3N4 hard mask.

[0047] The step of exposing the part of the substrate layer corresponding to the position in step S2 includes: using a double-sided photolithography overlay process on the first substrate to etch the part of the hard mask layer corresponding to the position to expose the part of the substrate layer corresponding to the position. The double-sided photolithography overlay process can operate on both sides of the substrate more conveniently and accurately to accurately form the double-sided pattern required by the process. In this embodiment, the double-sided overlay process uses a Suss MA6 photolithography machine; a photomask is designed with a central symmetry, and the Back Side alignment function is performed with the patterned substrate to align with the completed patterned surface, and the alignment accuracy is ≤1μm.

[0048] The specific steps of step S2 include:

[0049] a. Forming a photoresist layer on the hard mask layer of the first selection surface and the second selection surface respectively; the thickness of the photoresist layer is 1.4-3 μm, and the thickness selection ratio of the photoresist layer to the hard mask layer is (1-1.3):1.

[0050] b. Spin-coat AZ5214 photoresist on the first and second selected surfaces respectively, and then bake the first substrate on a hot plate at 110°C for 3 to 5 minutes. Then use a photolithography machine to complete the patterned exposure of the photoresist, and finally use a developer to wash away the photoresist removal at the exposed position to expose part of the hard mask layer.

[0051] c. Etching the exposed hard mask layer of the first selected surface and the second selected surface respectively, and exposing the corresponding portions of the substrate layer respectively.

[0052] The etching depth of the second selected surface in step 3 is 1:2 compared to the thickness of the first substrate, and the etching depth of the first selected surface is much smaller than the etching depth of the second selected surface. In this embodiment, a 200 μm deep groove is formed by dry etching on the substrate layer exposed by the second selected surface, and a 10 μm deep groove is formed by dry etching on the substrate layer exposed by the first selected surface, wherein the etching step includes: using a high-density plasma deep silicon etching system to perform SPTS deep inductively coupled plasma dry etching on the silicon structure layer exposed on the silicon substrate silicon wafer, and completing the etching of the silicon structure on the surface of the first substrate. Etching includes a cyclic passivation step and an etching step.

[0053] The etching depth of the second selected surface is half of the thickness of the first substrate, which makes the first selected surface and the second selected surface of the first substrate etched to the same depth. In other embodiments, etching of different depths can also be used, but etching of the same depth on both sides has a better effect, which can minimize the etching load to the greatest extent, reduce the difference between the design and the actual situation, and make the etching uniformity better.

[0054] In step 4, the preparation of the second substrate is the same as that of the first substrate, and the same cleaned silicon wafer with specifications of N-type 100 crystal orientation, thickness of 400 μm, and resistivity of 0.002-0.005 Ω.cm is selected.

[0055] In step 5, the bonding process uses an AML bonding machine; an infrared camera is used to align the marks between the substrates, nitrogen plasma is used for surface activation, pressure is applied for a period of time under a vacuum degree of 1E-3 for room temperature bonding, and annealing is performed in a nitrogen environment after bonding; in this embodiment, a pressure of 3000N-5000N is applied under a vacuum degree of 1E-3 for room temperature bonding, and the pressure application time is 30min-40min; after bonding, annealing is performed at 1100°C in a nitrogen environment for 2-3h.

[0056] In the related art, in order to ensure the smooth preparation of the back cavity through hole and avoid damaging other structures, a barrier layer is generally provided. In this embodiment, after the first substrate and the second substrate are bonded, the second selected surface is used as the bonding surface, and the deep grooves on the second selected surface that are deeply etched are used as the barrier structure. No additional barrier layer is required, and the second substrate is not easily damaged when etching is performed after bonding.

[0057] The etching method used in step 6 is consistent with that in step 3. A high-density plasma deep silicon etching system is used to perform deep inductively coupled plasma dry etching on the exposed silicon structure layer on the silicon substrate silicon wafer to complete the deep etching of the silicon structure on the surface of the silicon substrate silicon wafer. The remaining 200 μm of etching is completed at the shallow etching position of the first selected surface of the first substrate to connect with the deep etching position of the second selected surface to form a back cavity through hole.

[0058] The implementation principle of a method for preparing a C-SOI back cavity through hole in an embodiment of the present invention is as follows:

[0059] After the first substrate and the second substrate are prepared, the same hard mask layer is formed on both sides of the first substrate, which greatly reduces the thickness of the hard mask layer and avoids the adverse effects caused by the excessive thickness of the hard mask layer.

[0060] The two sides of the first substrate are respectively exposed to part of the hard mask layer by double-sided photolithography and overlay process, so as to obtain the corresponding double-sided pattern more accurately. The two sides of the first substrate are respectively etched to expose part of the substrate layer to be etched.

[0061] At this time, the two sides of the substrate layer are respectively deeply etched and shallowly etched as a mark, and then the deeply etched side is bonded to the second substrate. After bonding, etching is continued at the marked shallow etching to connect the shallow etching position with the deep etching position of the bonding surface, completing the preparation of the back cavity through hole.

[0062] By adopting two deep silicon etching methods, the mask thickness is greatly reduced while maintaining the original etching selectivity, reducing the disadvantages caused by the thick mask. After bonding, the process wafer has an SOI wafer etching barrier layer structure, which greatly reduces the process cost.

[0063] The above are all preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Therefore, any equivalent changes made based on the structure, shape, and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a C-SOI back cavity through hole, characterized in that: The following steps are involved: Step S1, providing a first substrate to be etched; Step S2, forming a hard mask on the first selected surface and the second selected surface of the first substrate, and etching a portion of the hard mask layer on the first selected surface and the second selected surface respectively, thereby exposing a portion of the substrate layer at a corresponding position respectively; Step S3, shallowly etching the exposed substrate layer of the first selected surface, and deeply etching the exposed substrate layer of the second selected surface, wherein the etching positions of the first selected surface and the second selected surface correspond to each other and are not connected; Step S4, providing a second substrate; Step S5, aligning and bonding the second selected surface of the first substrate and any surface of the second substrate; Step S6, performing residual substrate thickness etching on the etched position of the first selected surface of the first substrate to form a silicon back cavity through hole; The step of exposing the corresponding part of the substrate layer in step S2 includes: using a double-sided photolithography overlay process on the first substrate to etch the corresponding part of the hard mask layer respectively, so as to expose the corresponding part of the substrate layer; The specific steps of step S2 include: forming a photoresist layer on the hard mask layer of the first selection surface and the second selection surface respectively; exposing and developing the photoresist layer respectively to expose a portion of the hard mask layer; Etching the exposed hard mask layer of the first selected surface and the second selected surface respectively, and exposing the corresponding portions of the substrate layer respectively; The etching selection ratio between the first substrate and the hard mask layer is 100:1, and the hard mask layer includes a SiO2 hard mask or a Si3N4 hard mask; The thickness selection ratio of the photoresist layer to the hard mask layer is (1-1.3): 1; The ratio of the etching depth of the second selected surface in step 3 to the thickness of the first substrate is 1:2, and the etching depth of the first selected surface is much smaller than the etching depth of the second selected surface; The first substrate is a dry-etched substrate sheet; The etching method used in step 6 is the same as that in step 3; The etching in step 3 is to use SPTS deep inductively coupled plasma dry etching to the exposed substrate structure on the first substrate to complete the etching of the surface structure layer of the first substrate; the etching includes a cyclic passivation step and an etching step.

2. The preparation method according to claim 1, characterized in that: The bonding process uses an AML bonding machine; an infrared camera is used to align the marks between the substrates, nitrogen plasma is used for surface activation, pressure is applied for a period of time under a vacuum degree of 1E-3 for room temperature bonding, and annealing is performed in a nitrogen environment after bonding.

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