Connect the detection circuit and the chip

Abstract

The embodiment of the present invention provides a connection detection circuit and a core particle, which relate to the field of communication technology. The connection detection circuit is applied to a first core particle, and the first core particle includes a functional unit and an interconnection interface; the connection detection circuit includes a routing unit, and the routing unit is connected to the functional unit and the interconnection interface; the routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, and in response to detecting that the destination core particle of the data packet is a second core particle, determines a first transmission path, and transmits the data packet based on the first transmission path; in response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path, and transmits the data packet based on the second transmission path. When the connection detection circuit detects that the interconnection between some core particles fails, it reselects the communication path to initiate data transmission, restores the data transmission function, ensures normal data transmission, significantly enhances the reliability of the chip, and is suitable for various core particle interconnection topologies.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a connection detection circuit and a core particle. Background Art

[0002] Moore's Law is an observational and predictive law first proposed by Gordon Moore, one of the founders of Intel, in 1965. The core content of this law is that within a certain period of time, the number of transistors that can be accommodated on an integrated circuit will double, and at the same time, the performance of the integrated circuit will also double. Moore's Law reflects the speed of progress in information technology. In recent years, it has been impossible to further increase the number of transistors that can be accommodated on an integrated circuit by reducing the size of transistors and increasing the area of ​​a single chip. Chiplet technology was born. Chiplet technology integrates modular chips with different processes and functions like building blocks through high-speed inter-chip interconnection and packaging technology, which can achieve low cost and high yield while improving performance. Chiplet technology has gradually become an important way for the semiconductor industry to continue Moore's Law.

[0003] However, as the chip scale continues to expand and the process becomes increasingly complex, the chip packaging yield composed of multiple chips is facing new challenges. On the other hand, the demand for high computing power in complex scenarios such as automobiles, industry, aerospace, etc. is growing rapidly. While the chips meet their low-cost and high-performance requirements, the reliability of interconnection in harsh environments also needs to be effectively guaranteed. For example, Figure 1A As shown, in the ultra-large-scale chip design based on the chiplet design methodology, multiple chiplets are often required to be interconnected into a certain topology to form a complete function. Figure 1A A schematic diagram of a multi-chip design using a two-dimensional grid topology interconnection is shown, where chiplets c1, c2, c3, c4, c5, c6, c7, c8, and c9 are interconnected with adjacent chiplets. However, due to defects in the packaging manufacturing process or interference from the external environment, the communication function of a certain interconnection path or a certain chiplet may fail, such as Figure 1B As shown, the interconnection path between core particles c7 and c8 fails, which causes the entire chip to be scrapped and causes serious losses. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, an embodiment of the present invention provides a connection detection circuit and a chip.

[0005] In a first aspect, an embodiment of the present invention provides a connection detection circuit, wherein the connection detection circuit is applied to a first core particle, wherein the first core particle includes a functional unit and at least one group of interconnection interfaces;

[0006] The connection detection circuit includes a routing unit, and the routing unit is connected to the functional unit and the interconnection interface;

[0007] The routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, determines a first transmission path in response to detecting that the destination core particle of the data packet is the second core particle, and transmits the data packet based on the first transmission path;

[0008] In response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path and transmits the data packet based on the second transmission path.

[0009] In an optional embodiment, the routing unit determines a first transmission direction and a first intermediate core particle corresponding to the data packet, and transmits the data packet to the first intermediate core particle based on an interconnection interface between the first core particle and the first intermediate core particle; in response to detecting an abnormal connection of the interconnection interface between the first core particle and the first intermediate core particle, the routing unit determines a second transmission direction and a second intermediate core particle corresponding to the data packet, and transmits the data packet to the second intermediate core particle based on the interconnection interface between the first core particle and the second intermediate core particle.

[0010] In an optional embodiment, the routing unit determines whether a feedback signal sent by the first intermediate core particle is received in response to transmitting the data packet to the first intermediate core particle; if the feedback signal sent by the first intermediate core particle is not received within a preset time period, it is determined that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal.

[0011] In an optional embodiment, the routing unit receives a feedback signal sent by the first intermediate core particle, and the feedback signal indicates that the first intermediate core particle fails to verify the data packet, then determines that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal.

[0012] In an optional embodiment, the routing unit includes a data receiving subunit, a routing processing subunit and a data sending subunit;

[0013] The data receiving subunit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface;

[0014] The routing processing subunit determines a first transmission path according to the routing rule and the destination information of the data packet;

[0015] The data sending subunit transmits the data packet based on the first transmission path, and detects whether the first transmission path is normal;

[0016] The routing processing subunit determines a second transmission path in response to the data sending subunit detecting that the first transmission path is abnormal;

[0017] The data sending subunit transmits the data packet based on the second transmission path, and detects whether the second transmission path is normal.

[0018] In an optional embodiment, the data receiving subunit includes at least one cache, and the cache stores data packets received by the data receiving subunit.

[0019] In an optional embodiment, the routing processing subunit includes at least one direction arbitrator; the direction arbitrator is coupled to the cache, and the direction arbitrator determines the first transmission path or the second transmission path according to routing rules and destination information of the data packet.

[0020] In an optional embodiment, the routing processing subunit further includes a centralized arbitrator, and the centralized arbitrator is coupled to the at least one direction arbitrator and the data sending subunit;

[0021] The centralized arbitrator receives at least one data packet sent from the at least one direction to the arbitrator, determines the priority of the at least one data packet, and sends the data packet to the data sending subunit according to the priority of the at least one data packet.

[0022] In an optional embodiment, the data sending subunit collects data transmission exception information of each interconnection interface of the first core particle, and disables the interconnection interface when the data transmission exception information of the interconnection interface meets a disabling condition.

[0023] In an optional embodiment, the data packet includes routing information, packet return flag information and a check code of the data packet; the packet return flag information is used to indicate whether the data packet is a returned packet.

[0024] In an optional embodiment, in response to detecting that the first transmission path is abnormal, the routing unit sets a packet return flag of the data packet to a first preset value to identify the data packet as a returned packet.

[0025] In a second aspect, an embodiment of the present invention provides a core particle, including a functional unit, at least one group of interconnection interfaces and a connection detection circuit, wherein the connection detection circuit includes a routing unit; the routing unit is connected to the functional unit and the interconnection interface;

[0026] The routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, determines a first transmission path in response to detecting that the destination core particle of the data packet is the second core particle, and transmits the data packet based on the first transmission path;

[0027] In response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path and transmits the data packet based on the second transmission path.

[0028] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0029] The connection detection circuit provided by the embodiment of the present invention includes a routing unit, which is connected to the functional unit and the interconnection interface of the core particle. The routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, and in response to detecting that the destination core particle of the data packet is the second core particle, determines a first transmission path, and transmits the data packet based on the first transmission path; in response to detecting that the first transmission path is abnormal, determines a second transmission path, and transmits the data packet based on the second transmission path.

[0030] The connection detection circuit provided in the embodiment of the present invention reselects the communication path and reinitiates data transmission when detecting an abnormality in the first transmission path, that is, when the interconnection between some chiplets fails, to ensure normal data transmission. This can significantly enhance the chip reliability under harsh working conditions and is applicable to various chiplet interconnection topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0032] Figure 1A A schematic diagram of a multi-core design interconnected using a two-dimensional mesh topology is shown;

[0033] Figure 1B A schematic diagram showing the failure of a single-point interconnection of multiple core particles interconnected in a two-dimensional grid topology;

[0034] Figure 2 The schematic diagram of the structure of the core particle in the prior art is shown;

[0035] Figure 3 A schematic diagram of the structure of a connection detection circuit provided by an embodiment of the present invention is shown;

[0036] Figure 4 A schematic diagram showing a method for detecting an abnormality in an interconnection interface by a routing unit according to an embodiment of the present invention is shown.

[0037] Figure 5A schematic diagram of the structure of a routing unit provided by an embodiment of the present invention is shown;

[0038] Figure 6 A schematic structural diagram of a routing unit according to another embodiment of the present invention is shown;

[0039] Figure 7 A schematic structural diagram of a routing unit according to another embodiment of the present invention is shown;

[0040] Figure 8 The schematic diagram of the process of interconnect failure detection and data transmission based on routing units is shown;

[0041] Fig. 9A and Fig. 9B The data transmission paths under normal and local abnormal conditions of the interconnection interface in a two-dimensional grid interconnection topology are respectively demonstrated;

[0042] Fig. 10A and Fig. 10B The data transmission paths under normal and local abnormal conditions of the interconnection interface in a two-dimensional grid interconnection topology are respectively demonstrated;

[0043] Fig.11A and Fig. 11B The data transmission paths under normal and local abnormal conditions of the interconnection interface in a two-dimensional grid interconnection topology are shown respectively. DETAILED DESCRIPTION

[0044] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0045] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0046] Figure 2 FIG. 2 shows a schematic diagram of the circuit structure of a chip in the prior art. Figure 2As shown, the core particle consists of a functional unit H1 and one or more groups of core particle interconnection interfaces. Among them, the functional unit H1 may include but is not limited to: CPU (Central Processing Unit), GPU (Graphics Processing Unit), AI (Artificial Intelligence) functional unit, video image codec unit, IO (Input / Output) interconnection unit or composite functional unit, etc. Each group of core particle interconnection interfaces includes two directions: input and output. Figure 2 In the figure, IN1, IN2, IN3, and IN4 represent interconnection interfaces in the input direction, and OUT1, OUT2, OUT3, and OUT4 represent interconnection interfaces in the output direction. Different core particles can have different functional units and different numbers of interconnection interfaces. Data communication is performed through the interconnection interfaces, and they can be combined into chips with higher performance and complete functions.

[0047] Considering that when the scale of chiplet interconnection is large, a single-point interconnection interface failure will cause the entire chip to be scrapped, resulting in major losses or functional accidents, an embodiment of the present invention provides a connection detection circuit, which is applied to the chiplets and is used to detect whether the interconnection interface between the chiplets is normal. When a local interconnection failure is detected, the communication topology can be adaptively rebuilt to maintain normal functions, and it is easy to adapt to various types of chiplet interconnection topology structures.

[0048] Figure 3 FIG. 2 shows a schematic diagram of the structure of a connection detection circuit according to an embodiment of the present invention. Figure 3 As shown, the connection detection circuit includes a routing unit H2, which is coupled to the functional unit H1 of the core particle and the interconnection interface. For example, the routing unit H2 is interconnected with the functional unit H1 through an on-chip high-speed data bus. The data packets sent by the functional unit H1 or the data packets transmitted through the interconnection interface are arbitrated and managed by the routing unit H2.

[0049] The routing unit H2 receives the data packet sent by the functional unit of the core grain or the data packet transmitted by other core grains based on the interconnection interface, and in response to detecting that the destination core grain of the data packet is the second core grain, determines the first transmission path, and transmits the data packet based on the first transmission path. If the routing unit H2 detects that the first transmission path is abnormal, it determines the second transmission path, and retransmits the data packet to the second core grain through the second transmission path. As an optional example, the data packet includes the destination information of the data packet, such as the location information of the destination core grain, and the routing unit H2 determines the first transmission path or the second transmission path according to the destination information of the data packet and the routing rules.

[0050] In an embodiment of the present invention, the routing unit transmits the received data packets, redetermines the transmission path and re-initiates the transmission when a transmission anomaly is detected. This processing mechanism ensures normal data transmission, which can significantly enhance the reliability of the chip under harsh working conditions. The routing unit is suitable for various chip interconnection topologies.

[0051] In an optional embodiment, when receiving a data packet, the routing unit of the first core determines the first transmission direction and the first intermediate core corresponding to the data packet according to the routing rules and the location information of the destination core, and transmits the data packet to the first intermediate core based on the interconnection interface between the first core and the first intermediate core. In response to transmitting the data packet to the first intermediate core, the routing unit detects whether the interconnection interface between the first core and the first intermediate core is connected normally; if it is detected that the interconnection interface between the first core and the first intermediate core is abnormally connected, the second transmission direction and the second intermediate core corresponding to the data packet are determined, and the data packet is transmitted to the second intermediate core based on the interconnection interface between the first core and the second intermediate core. When receiving a data packet, the routing unit of the second intermediate core determines the third transmission direction and the third intermediate core corresponding to the data packet according to the routing rules and the location information of the destination core, and transmits the data packet to the third intermediate core based on the interconnection interface between the second intermediate core and the third intermediate core. In response to transmitting a data packet to the third intermediate core particle, the routing unit of the second intermediate core particle detects whether the interconnection interface between the second intermediate core particle and the third intermediate core particle is connected normally; if it is detected that the interconnection interface between the second intermediate core particle and the third intermediate core particle is abnormally connected, the fourth transmission direction and the fourth intermediate core particle corresponding to the data packet are determined, and the data packet is transmitted to the fourth intermediate core particle based on the interconnection interface between the second intermediate core particle and the fourth intermediate core particle. And so on, until the data packet is delivered to the destination core particle.

[0052] The connection detection circuit provided by the embodiment of the present invention has low logic overhead and low function implementation complexity, and is easy to adapt to various chip interconnection topologies such as two-dimensional grid, ring, and full connection without adding additional process costs. It significantly enhances the reliability of the chip under harsh working conditions and can effectively reduce losses caused by production process defects or external environmental interference.

[0053] In an optional embodiment, after sending a data packet to the first intermediate core, the routing unit of the first core determines whether a feedback signal sent by the first intermediate core is received. If the feedback signal sent by the first intermediate core is not received within a preset time period, it is determined that the interconnection interface connection between the first core and the first intermediate core is abnormal. The preset time period can be flexibly set according to the application scenario, and the present invention is not limited here. As an optional example, the preset time period can be 0.5 seconds, 1 second, etc.

[0054] Figure 4FIG. 2 is a schematic diagram showing a routing unit detecting an abnormality of an interconnection interface according to an embodiment of the present invention. Figure 4 As shown, data packets are transmitted between core c0 and core c1. In addition to the high-speed interconnection data path, the interconnection interface between core c0 and core c1 also has an additional feedback signal path (the feedback signal path is used to transmit feedback signals). Core c0 sends a data packet to core c1 (as shown in FIG. Figure 4 If the interconnection interface between core c0 and core c1 is connected normally, core c1 sends a feedback signal (such as Figure 4 The feedback signal A shown in FIG. 1 is to indicate that the core particle c1 has received the data packet sent by the core particle c0, and the interconnection interface between the core particles c0 and c1 is connected normally. If the interconnection interface between the core particles c0 and c1 is abnormal, the core particle c1 cannot receive the data packet and cannot send a feedback signal to the core particle c0. If the core particle c0 does not receive the feedback signal within a preset time period (for example, within 1 second), it is determined that the interconnection interface between the core particles c0 and c1 is abnormal. Similarly, the core particle c1 sends a data packet to the core particle c0 (such as Figure 4 If the interconnection interface between core c0 and core c1 is connected normally, core c0 sends a feedback signal (such as Figure 4 The feedback signal B shown in FIG. 1 shows that the core c0 receives the data packet sent by the core c1, and the interconnection interface between the core c0 and the core c1 is connected normally. If the interconnection interface between the core c0 and the core c1 is abnormal, the core c0 cannot receive the data packet and cannot send a feedback signal to the core c1. If the core c1 does not receive the feedback signal within a preset time period (for example, within 1 second), it is determined that the interconnection interface between the core c0 and the core c1 is abnormal.

[0055] In some other optional embodiments, the data packet includes a check code. The check code is used to check the correctness of the data packet. In an optional embodiment, the check code can be obtained by a certain operation from the data in the data packet. The data packet sent by the first core to the first intermediate core includes a first check code. When the first intermediate core receives the data packet, it operates on the data in the data packet to obtain a second check code. The first intermediate core compares the first check code with the second check code. If the first check code is consistent with the second check code, it is determined that the interconnection interface between the first core and the first intermediate core is connected normally. The first intermediate core sends a feedback signal indicating that the data packet check is correct to the first core, so as to inform the first core that the interconnection interface between the two is connected normally. If the first check code is inconsistent with the second check code, it is determined that there is an abnormality in the data packet, and the interconnection interface between the first core and the first intermediate core is abnormally connected, then the first intermediate core sends a feedback signal indicating that the data packet check is wrong to the first core, so as to inform the first core that the data packet sent by it is wrong and the interconnection interface between the two is abnormally connected.

[0056] Therefore, in an embodiment of the present invention, after the first core particle transmits a data packet to the first intermediate core particle through the interconnection interface, if the first core particle does not receive a feedback signal sent by the first intermediate core particle within a preset time period, it is determined that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal; if the first core particle receives a feedback signal sent by the first intermediate core particle, and the feedback signal indicates a data packet verification error, it is determined that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal (for example, the interconnection interface connection is unstable, resulting in data loss); if the first core particle receives a feedback signal sent by the first intermediate core particle, and the feedback signal indicates that the data packet verification is correct, it is determined that the interconnection interface connection between the first core particle and the first intermediate core particle is normal.

[0057] In some optional implementation scenarios, the core particles may agree that when the interconnection interface is normal, the receiver will provide feedback every time the sender sends a number of (for example, 1, 2 or 5) data packets. If the receiver receives the agreed number of data packets and the check codes are consistent, the receiver sends a feedback signal to the sender indicating that all data packets have been verified correctly, to inform the sender that the data packets are received correctly and the interconnection interface between the two is normal. If the receiver does not receive the agreed number of data packets, or receives the agreed number of data packets but the check codes are inconsistent, a feedback signal indicating that the number of data packets is incorrect or the data packet verification is wrong is sent to the sender to inform the sender that the interconnection interface between the two is abnormal. Optionally, the format of the feedback signal can be agreed upon between the core particles.

[0058] In an optional embodiment, the routing unit determines the connection status, data packet verification status (such as correct verification, verification error) and data transmission rate of each interconnection interface of the first core particle based on the received feedback signal, and then counts the data transmission exception information (such as bit error rate) of each interconnection interface of the first core particle. When the data transmission exception information of the interconnection interface meets the disabling condition, the interconnection interface is disabled.

[0059] Figure 5 FIG. 2 shows a schematic diagram of the structure of a routing unit provided by an embodiment of the present invention. Figure 5 As shown, the routing unit H2 includes a data receiving subunit H3, a routing processing subunit H4 and a data sending subunit H5.

[0060] Among them, the data receiving subunit H3 is responsible for aggregating and caching input data, the data sending subunit H5 is responsible for data sending and anomaly detection, and the routing processing subunit H4 is responsible for chiplet communication routing rules and direction arbitration.

[0061] For example, the data receiving subunit H3 receives a data packet sent by a functional unit or a data packet transmitted based on an interconnection interface. The routing processing subunit H4 determines a first transmission path according to routing rules and destination information of the data packet; the data sending subunit H5 transmits a data packet based on the first transmission path and detects whether the first transmission path is normal. The routing processing subunit H4 determines a second transmission path in response to the data sending subunit detecting that the first transmission path is abnormal. The data sending subunit H5 transmits a data packet based on the second transmission path and detects whether the second transmission path is normal.

[0062] The routing unit provided by the embodiment of the present invention has low logic overhead and low function implementation complexity, and is easy to adapt to various chip interconnection topologies such as two-dimensional grid, ring, and full connection without adding additional process costs. It significantly enhances the reliability of the chip under harsh working conditions and can effectively reduce losses caused by production process defects or external environmental interference.

[0063] Figure 6 FIG. 2 shows a schematic diagram of the structure of a routing unit according to another embodiment of the present invention. Figure 6 As shown, the routing unit includes a data receiving subunit H3, a routing processing subunit H4 and a data sending subunit H5.

[0064] The data receiving subunit H3 includes at least one buffer H6. The buffer H6 stores the data packets received by the data receiving subunit H3.

[0065] The routing processing subunit H4 includes at least one direction arbitrator H7 and a centralized arbitrator H8. The direction arbitrator H7 is coupled to the cache H6. The direction arbitrator H7 determines the first transmission path or the second transmission path according to the routing rule and the destination information of the data packet. The centralized arbitrator H8 is coupled to the direction arbitrator H7 and the data sending subunit H3. The centralized arbitrator H8 receives at least one data packet sent by the direction arbitrator H7, determines the priority of at least one data packet, and sends the data packet to the data sending subunit H3 according to the priority of at least one data packet.

[0066] The data sending subunit H5 includes an anomaly detector H9. The anomaly detector H9 is used to detect whether the interconnection interface between the two core particles is connected normally. For example, the anomaly detector in the first core particle determines whether a feedback signal sent by the first intermediate core particle is received in response to transmitting a data packet to the first intermediate core particle. If the feedback signal sent by the first intermediate core particle is not received within a preset time period, or a feedback signal indicating a data packet verification error is received, the anomaly detector in the first core particle determines that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal. If a feedback signal indicating that the data packet verification is correct is received, the anomaly detector in the first core particle determines that the interconnection interface connection between the first core particle and the first intermediate core particle is normal.

[0067] Among them, if the first intermediate core receives the data packet sent by the first core, the data in the data packet is calculated to obtain the second check code. The first intermediate core compares the first check code with the second check code. If the first check code is consistent with the second check code, it is determined that the interconnection interface between the first core and the first intermediate core is connected normally. The first intermediate core sends a feedback signal to the first core indicating that the data packet is checked correctly. If the first check code is inconsistent with the second check code, it is determined that there is an abnormality in the data packet, and the interconnection interface between the first core and the first intermediate core is connected abnormally. The first intermediate core sends a feedback signal to the first core indicating that the data packet is checked incorrectly, so as to inform the first core that the data packet sent by it is wrong and the interconnection interface between the two is connected abnormally. If the first intermediate core does not receive the data packet sent by the first core, the first intermediate core cannot send a feedback signal to the first core. If the first core cannot receive the feedback signal, it is determined that the interconnection interface between the first core and the first intermediate core is connected abnormally.

[0068] In an optional embodiment, the anomaly detector counts the data transmission anomaly information of each interconnection interface of the first core particle, and when the data transmission anomaly information of the interconnection interface meets the disabling condition, the interconnection interface is disabled. For example, the anomaly detector counts the connection status of the current interface, the current data packet verification status, the current interconnection rate information and the error statistics data. According to the connection status of the current interconnection interface, the current interconnection rate information and / or the error statistics data, it is judged whether the current interconnection interface meets the disabling condition. If the disabling condition is met, the interconnection interface is disabled. In an optional embodiment, disabling the interconnection interface may include permanent disabling and short-term disabling. If it is permanently disabled, the routing rules are modified to mark the interconnection interface as permanently disabled. If it is short-term disabled, the timing starts when the interconnection interface is disabled, and an attempt is made to restore the connection of the interconnection interface. When the disabling time reaches the conditional formula for disabling release, the disabling of the interconnection interface is released. At the same time, the connection status of the interconnection interface is detected. If the connection is abnormal, the short-term disabled state is entered again to minimize the impact on performance while the self-repair function is provided.

[0069] Figure 7 The schematic diagram of the structure of the routing unit of an embodiment of the present invention is shown. The core particle is provided with four-directional interconnection interfaces (i.e., four-directional input interfaces and four-directional output interfaces), and the routing unit H1 is coupled with the functional unit on the core particle and the four-directional interconnection interfaces to receive data packets sent by the functional unit and data packets transmitted through the interconnection interfaces.

[0070] like Figure 7 As shown, the data receiving subunit H3 includes 5 caches, namely: cache queue 0, cache queue 1, cache queue 2, cache queue 3, and cache queue 4, which cache data packets transmitted by the functional units and the input interfaces in four directions respectively. The data receiving subunit H3 passes the data packets at the head of each cache queue to the routing processing subunit H4 for arbitration.

[0071] The routing processing subunit H4 includes five directional arbitrators H7 and a centralized arbitrator H8. The directional arbitrator H7 determines the output direction of each data packet according to the routing rules and the destination information of each data packet. The centralized arbitrator H8 receives at least one data packet sent by the directional arbitrator H7, determines the priority of the data packet, and sends the data packet to the data sending subunit H3 according to the priority of the data packet.

[0072] The data transmission subunit H5 transmits the data packets through the output interface corresponding to the direction of each data packet in the order in which the centralized arbiter H8 sends the data packets. At the same time, the abnormality detector H9 detects whether the transmission is abnormal, and determines whether to restart the transmission or release the cache corresponding to the data packet according to the detection result. If the data packet transmission is normal, the cache corresponding to the data packet is released. If the data packet transmission is abnormal, the routing processing subunit H4 re-determines the output direction of the data packet, and the data transmission subunit H5 restarts the transmission according to the re-determined output direction.

[0073] refer to Figure 6 or Figure 7 The routing unit shown, such as Figure 8 As shown in the figure, the process of interconnect failure detection and data transmission based on the routing unit of the chiplet includes:

[0074] Step S801: the chip receives a data packet sent from an external interconnection interface or an on-chip functional unit.

[0075] Step S802: the routing unit stores the received data packet into the cache queue corresponding to the input direction.

[0076] Step S803: The routing unit determines the output direction of the data packet according to the routing rules and the destination information of the data packet. For example, in a two-dimensional mesh topology interconnection, the position of the core particle can be abstracted as a two-dimensional coordinate, and the data packet is first sent to the core particle with the same X coordinate as the target core particle, and then sent to the core particle with the same Y coordinate as the target core particle, that is, it reaches the destination core particle.

[0077] Step S804: If the output direction is the chiplet interconnection path, priority arbitration is performed with data packets from other sources (other chiplet input interfaces or on-chip functional unit inputs) of the same output direction to determine the output order of the direction.

[0078] Step S805: while the routing unit outputs the data packet, the routing unit detects whether the interconnection interface in the output direction is connected normally.

[0079] Step S806: If the connection is abnormal, the routing unit re-arbitrates the output direction of the current data packet and re-initiates transmission according to the new transmission direction.

[0080] Step S807: If the connection is normal, the data buffer space occupied by the data packet is released after the transmission is completed.

[0081] Step S808: If there is no available output direction at present, that is, if all output directions of the interconnection interfaces of the core particle are detected to be faulty, the communication establishment fails and is retried after a short delay.

[0082] Step S809: If the data packet is output to an on-chip functional unit (ie, the chip is the data destination), it is directly output and the data cache space occupied by the data is released.

[0083] As an alternative example, Fig. 9A As shown in Figure 1, core particles c1, c2, c3, c4, c5, c6, c7, c8 and c9 form a two-dimensional MESH core particle interconnection topology. When all core particle interconnection interfaces are normal, the data transmission path between core particles c1 and c9 is shown as the blue line. When the interconnection interface between core particles c7 and c8 is abnormal, the data transmission path is as shown in Figure 1. Fig. 9B As shown by the yellow line in the figure. The data transmission process is as follows:

[0084] (1) Corelet c1 transmits a data packet to corelet c4.

[0085] (2) Core c4 receives the data packet and determines the transmission direction of the data packet as: transmitting the data packet to core c7.

[0086] (3) Corelet c4 transmits the data packet to corelet c7.

[0087] (4) Core c7 receives the data packet and determines the transmission direction of the data packet: transmitting the data packet to core c8.

[0088] (5) Core cell c7 transmits the data packet to core cell c8.

[0089] (6) When the core c7 detects that the interconnection interface between it and the core c8 is abnormal, the core c7 re-determines the transmission direction of the data packet. The transmission direction re-determined by the core c7 is: transmitting the data packet to the core c4.

[0090] (7) Core chip c7 sends a data packet to core chip c4.

[0091] (8) Core c4 receives the data packet and determines the transmission direction of the data packet as: transmitting the data packet to core c5.

[0092] (9) Core cell c4 sends a data packet to core cell c5.

[0093] (10) Core c5 receives the data packet and determines the transmission direction of the data packet as: transmitting the data packet to core c8.

[0094] (11) Core cell c5 transmits the data packet to core cell c8.

[0095] (12) Core cell c8 receives the data packet and determines the transmission direction of the data packet as: transmitting the data packet to core cell c9.

[0096] (13) Core cell c8 transmits the data packet to core cell c9.

[0097] Similarly, Fig. 10A and Fig. 10B The data transmission paths under normal and local abnormal conditions of the interconnection interface in a two-dimensional grid interconnection topology are respectively shown; Fig. 10A In the case where all chiplet interconnection interfaces are normal, the data transmission path between chiplet c1 to chiplet c8 is shown as the blue line. Fig. 10B In the example, when the interconnection interface between corelets c6 and c7 is abnormal, the data transmission path between corelets c1 and c8 is shown as a yellow line.

[0098] Fig.11A and Fig. 11B The data transmission paths under normal and local abnormal conditions of the interconnection interface in a fully connected topology are shown respectively. Fig.11A As shown, the data transmission path between corelet c1 and corelet c4 is shown as a blue line. Fig. 11B In the example, when the interconnection interface between corelet c1 and corelet c4 is abnormal, the data transmission path between corelet c1 and corelet c8 is shown as a yellow line.

[0099] In an optional embodiment, the data packet of the embodiment of the present invention may include routing information of the data packet, packet return flag information, specific data and a check code, etc.

[0100] The routing information may include source information and destination information of the data packet.

[0101] The packet return flag is used to indicate whether the data packet is returned. Optionally, if the packet return flag is a first preset value, it indicates that the data packet is returned, and if the packet return flag is a second preset value, it indicates that the data packet is not returned. In an optional embodiment, the packet return flag in the data packet is the second preset value by default. If there is an abnormality in the interconnect interface connection in the transmission path of the data packet, the unsuccessful core updates the packet return flag in the data packet to the first preset value to indicate that the data packet is returned, and the data packet cannot be transmitted through the previous transmission path, and the transmission path needs to be re-determined.

[0102] In an optional embodiment, the core particle that fails to send a data packet returns the data packet to the previous level core particle when updating the packet return flag in the data packet to the first preset value, so that the previous level core particle re-determines the transmission path of the data packet. Fig. 9BAs shown, when core c7 detects that the interconnection interface between it and core c8 is abnormal, core c7 updates the packet return flag in the data packet to the first preset value, and returns the data packet to the upper-level core, that is, to core c4. Core c4 receives the data packet sent by core c7, detects that the packet return flag of the data packet is the first preset value, determines that there is an abnormality in the transmission path through core c7, and re-determines the transmission path of the data packet.

[0103] In an optional embodiment, the present invention also provides a core particle applied to the above connection detection circuit. Figure 3 The core particle includes a functional unit, at least one group of interconnection interfaces and a connection detection circuit, and the connection detection circuit includes a routing unit; the routing unit is connected to the functional unit and the interconnection interface; the routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, and in response to detecting that the destination core particle of the data packet is a second core particle, determines a first transmission path, and transmits the data packet based on the first transmission path; in response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path, and transmits the data packet based on the second transmission path.

[0104] The chip of the embodiment of the present invention can be applied to various chip topology structures. In the event of a single-point interconnection communication failure of the chip, data transmission can be re-initiated through a connection detection circuit to note the normal transmission of data, thereby avoiding the entire chip being scrapped due to a single-point interconnection path failure.

[0105] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0106] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A connection detection circuit, characterized in that: The connection detection circuit is applied to a first core particle, wherein the first core particle includes a functional unit and at least one group of interconnection interfaces; The connection detection circuit includes a routing unit, and the routing unit is connected to the functional unit and the interconnection interface; The routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, determines a first transmission path in response to detecting that the destination core particle of the data packet is the second core particle, and transmits the data packet based on the first transmission path; In response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path and transmits the data packet based on the second transmission path; The routing unit is used for two-dimensional grid, ring and fully connected core-like interconnect topologies; The routing unit includes a data receiving subunit, a routing processing subunit and a data sending subunit; The data sending subunit counts data transmission exception information of each interconnection interface of the first core particle, and disables the interconnection interface when the data transmission exception information of the interconnection interface meets a disabling condition; Disabling the interconnect interface includes permanent disabling and short-term disabling. If it is permanently disabled, the routing rules are modified to mark the interconnect interface as permanently disabled; if it is short-term disabled, the timing starts when the interconnect interface is disabled, and an attempt is made to restore the connection of the interconnect interface. When the disablement time reaches the condition for lifting the disablement, the disablement of the interconnect interface is lifted; the connection status of the interconnect interface is detected. If the connection is abnormal, the short-term disabled state is entered again.

2. The circuit according to claim 1, characterized in that The routing unit determines a first transmission direction and a first intermediate core-grain corresponding to the data packet, and transmits the data packet to the first intermediate core-grain based on an interconnection interface between the first core-grain and the first intermediate core-grain; In response to detecting an abnormal connection between the interconnection interface between the first core particle and the first intermediate core particle, the routing unit determines a second transmission direction and a second intermediate core particle corresponding to the data packet, and transmits the data packet to the second intermediate core particle based on the interconnection interface between the first core particle and the second intermediate core particle.

3. The circuit according to claim 2, characterized in that In response to transmitting the data packet to the first intermediate core particle, the routing unit determines whether a feedback signal sent by the first intermediate core particle is received; if the feedback signal sent by the first intermediate core particle is not received within a preset time period, it is determined that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal.

4. The circuit according to claim 3, characterized in that The routing unit receives a feedback signal sent by the first intermediate core particle, and the feedback signal indicates that the first intermediate core particle fails to verify the data packet, and then determines that the interconnection interface connection between the first core particle and the first intermediate core particle is abnormal.

5. The circuit according to any one of claims 1 to 4, characterized in that: The data receiving subunit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface; The routing processing subunit determines a first transmission path according to a routing rule and destination information of the data packet; The data sending subunit transmits the data packet based on the first transmission path, and detects whether the first transmission path is normal; The routing processing subunit determines a second transmission path in response to the data sending subunit detecting that the first transmission path is abnormal; The data sending subunit transmits the data packet based on the second transmission path, and detects whether the second transmission path is normal.

6. The circuit according to claim 5, characterized in that The data receiving subunit includes at least one cache, and the cache stores data packets received by the data receiving subunit.

7. The circuit according to claim 6, characterized in that The routing processing subunit includes at least one direction arbitrator; the direction arbitrator is coupled to the cache, and the direction arbitrator determines the first transmission path or the second transmission path according to routing rules and destination information of the data packet.

8. The circuit according to claim 7, characterized in that The routing processing subunit further includes a centralized arbitrator, the centralized arbitrator is coupled to the at least one direction arbitrator and the data sending subunit; The centralized arbitrator receives at least one data packet sent from the at least one direction to the arbitrator, determines the priority of the at least one data packet, and sends the data packet to the data sending subunit according to the priority of the at least one data packet.

9. The circuit according to claim 1, characterized in that The data packet includes routing information and packet return flag information of the data packet; the packet return flag information is used to indicate whether the data packet is a packet return.

10. The circuit according to claim 9, characterized in that In response to detecting that the first transmission path is abnormal, the routing unit sets a packet return flag of the data packet to a first preset value to identify the data packet as a packet return.

11. A core particle, characterized in that: It includes a functional unit, at least one group of interconnection interfaces and a connection detection circuit, wherein the connection detection circuit includes a routing unit; the routing unit is connected to the functional unit and the interconnection interface; The routing unit receives a data packet sent by the functional unit or a data packet transmitted based on the interconnection interface, determines a first transmission path in response to detecting that the destination core particle of the data packet is the second core particle, and transmits the data packet based on the first transmission path; In response to detecting that the first transmission path is abnormal, the routing unit determines a second transmission path and transmits the data packet based on the second transmission path; The routing unit is applicable to various types of chiplet interconnection topologies, including: two-dimensional grid, ring, and fully connected; When a local abnormality occurs in the interconnection interface under the two-dimensional grid interconnection topology, the data packet returns to the starting node and is routed to the original destination node through another transmission path; The routing unit includes a data receiving subunit, a routing processing subunit and a data sending subunit; The data sending subunit counts data transmission exception information of each interconnection interface of the first core particle, and disables the interconnection interface when the data transmission exception information of the interconnection interface meets the disabling condition; Disabling the interconnect interface includes permanent disabling and short-term disabling. If it is permanently disabled, the routing rules are modified to mark the interconnect interface as permanently disabled; if it is short-term disabled, the timing starts when the interconnect interface is disabled, and an attempt is made to restore the connection of the interconnect interface. When the disablement time reaches the conditional formula for lifting the disablement, the disablement of the interconnect interface is lifted; the connection status of the interconnect interface is detected. If the connection is abnormal, the short-term disabled state is entered again.

Images