Method, device, medium and product for multi-core chip verification

Abstract

The present invention discloses a method, device, medium and product for multi-core chip verification. The method includes: designing a multi-core architecture for managing multi-core operation; based on the designed multi-core architecture, creating UART tasks, command processing tasks and queues, and designing a multi-core verification command menu based on a serial port; the UART task receives and parses the serial port command for multi-core verification, and sends the command to a designated core through a queue according to the parsing result; the designated core executes the command processing task and calls a test case. The present invention reduces the complexity and resource consumption in the verification process and improves the efficiency and flexibility of verification by designing a streamlined multi-core architecture and performing multi-core command selection based on a serial port.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip verification, and specifically relates to a method, device, medium and product for multi-core chip verification. Background Art

[0002] Currently, multi-core operating systems are commonly used to manage program execution on multi-core MCUs. Functional verification of multi-core MCUs is primarily performed by writing test cases in the C language. This approach allows developers to simulate various real-world application scenarios and comprehensively test all chip functions. However, due to the complexity of multi-core MCUs, separate verification projects typically need to be managed and executed for each core, which undoubtedly increases the complexity and workload of the verification process.

[0003] If the verification code for a multi-core MCU is equipped with a multi-core operating system, the code space will increase significantly, making it unsuitable for MCUs with limited resources. In addition, the complex logic of the operating system itself will increase the difficulty of the debugging process, making problems discovered during the verification process more difficult to analyze and solve.

[0004] Without a multi-core operating system, the verification process typically requires managing test code across multiple independent projects, one for each core. This approach requires downloading multiple projects to the corresponding core for each test, increasing both the complexity of the verification work and the time cost of testing. Summary of the Invention

[0005] The purpose of the present invention is to address the problems existing in the prior art and provide a method, device, medium and product for multi-core chip verification. By designing a streamlined multi-core architecture and performing multi-core command selection based on a serial port, the complexity and resource consumption in the verification process are reduced, and the efficiency and flexibility of verification are improved.

[0006] According to one aspect of the present invention, a method for multi-core chip verification is provided, comprising:

[0007] Design a multi-core architecture to manage multi-core operations;

[0008] Based on the designed multi-core architecture, create UART tasks, command processing tasks and queues, and design a multi-core verification command menu based on the serial port;

[0009] The UART task receives and parses serial port commands for multi-core verification, and sends the commands to the specified core through the queue based on the parsing results;

[0010] The specified core executes the command processing task and calls the test case.

[0011] As a further technical solution, during the initialization phase, the multi-core architecture specifies an independent stack space for each core.

[0012] As a further technical solution, each core adopts a task polling scheduling method to cyclically check and execute the assigned tasks in sequence.

[0013] As a further technical solution, the task polling scheduling adopts infinite loop polling to execute each task, and when the CoreID of the current running core is the same as the TaskCoreId of the running core specified by the task, the specified task is executed.

[0014] As a further technical solution, a multi-core verification command menu is designed based on the serial port, including: commands for specifying the test cases to be executed; core selection parameters for specifying which core the test cases will run on; and test case parameters for passing test case parameters.

[0015] As a further technical solution, the core selection parameter is set to C[n][n+1][n+2]…, n=0, 1, 2…, where n corresponds to the CoreID of the core.

[0016] According to one aspect of the present invention, there is provided a device for multi-core chip verification, comprising:

[0017] A multi-core architecture design module, used to design a multi-core architecture for managing multi-core operations;

[0018] Task creation module, used to create UART tasks, command processing tasks and queues based on the designed multi-core architecture;

[0019] Multi-core verification command design module, used to design multi-core verification command menu based on serial port in multi-core architecture;

[0020] The multi-core verification command receiving and parsing module is used by the UART task to receive and parse serial port commands for multi-core verification, and send the commands to the designated core through the queue based on the parsing results;

[0021] The task execution module is used to execute the specified core command to process the task and call the test case.

[0022] According to one aspect of the present invention, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method for multi-core chip verification are implemented.

[0023] According to one aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method for multi-core chip verification.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The streamlined multi-core architecture designed in this invention is simple and easy to implement. Using this architecture, a single project can manage multi-core operations without relying on an operating system. This not only avoids the additional code space requirements and complexity introduced by using a multi-core operating system, but also simplifies debugging and problem analysis, making functional verification of multi-core chips more efficient and straightforward.

[0026] This invention uses a UART-based command menu system that supports multiple cores. Testers can use the serial port assistant to send commands to select a specific core to run test cases. This mechanism of selecting cores through commands makes it easy to run test cases on different cores. This avoids the tedious step of repeatedly downloading code to each core for each test, greatly simplifying the test operation process.

[0027] The present invention uses a single project to uniformly manage the operation of multiple cores, significantly reducing the complexity and resource consumption in the verification process. At the same time, it selects the specified core to run test cases based on UART menu commands, thereby improving the efficiency and flexibility of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the multi-core chip verification method according to an embodiment of the present invention.

[0029] Figure 2 Schematic diagram of the multi-core architecture process according to an embodiment of the present invention.

[0030] Figure 3 2 is a schematic diagram of a multi-core verification command menu according to an embodiment of the present invention.

[0031] Figure 4 2 is a schematic diagram of a multi-core command processing flow according to an embodiment of the present invention.

[0032] Figure 5 Schematic diagram of a multi-core verification process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] It should be noted that:

[0034] A multi-core operating system refers to an operating system that runs on a multi-core processor and can utilize the multi-core computing capabilities.

[0035] A multi-core processor (such as the multi-core MCU mentioned below) is a processor that integrates two or more complete computing engines.

[0036] Existing multi-core MCU verification requires a multi-core operating system, which is not suitable for MCUs with limited resources; or it requires multiple independent projects to manage the code, making the verification work complicated. To solve this technical problem, the present invention provides a multi-core chip verification method. Through a streamlined multi-core architecture design, it can support the use of a single project to manage the operation of multiple cores without the need for a multi-core operating system, significantly reducing the complexity and resource consumption of the verification process. In addition, within this multi-core architecture, serial port menu commands can be used to select a specific core to run the task, improving the efficiency and flexibility of verification.

[0037] Some of the processes described in the specification and claims of the present invention and the accompanying drawings include multiple operations that appear in a specific order. However, it should be understood that these operations may not be performed in the order in which they appear herein or may be performed in parallel. For example, the sequence numbers "step 1," "step 2," etc., are merely used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations may be performed sequentially or in parallel.

[0038] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] The present invention provides a method for multi-core chip verification. By designing a streamlined multi-core architecture, the method can use the same project to manage the operation of multiple cores without relying on a multi-core operating system, and can select a specified core to run test cases based on UART menu commands, thereby improving the efficiency and flexibility of verification.

[0040] like Figure 1 As shown, the method for multi-core chip verification includes:

[0041] Step 1: Design a multi-core architecture to manage multi-core operations.

[0042] This paper designs a streamlined multi-core architecture for multi-core verification. Using this architecture, the same project can be used to manage multi-core operations without relying on an operating system. The implementation scheme is as follows:

[0043] 1) Program running

[0044] All cores boot from the same address and run the same program code. The program uses the Core ID of the currently running core to distinguish the execution logic of different cores. This way, although all cores run the same code, they can execute different tasks or functions based on the Core ID.

[0045] 2) Independent stack space

[0046] In order to avoid conflicts and competition in stack space between different cores, the main stack pointer (MSP) is modified to enable each core to use an independent stack space.

[0047] 3) Task creation

[0048] This multi-core architecture enables easy task creation. When creating a task, you can specify the core to run the task by configuring TaskCoreId.

[0049] 4) Queue

[0050] The multi-core architecture enables easy queue creation, which is used to send and receive information between different tasks through queues.

[0051] 5) Task polling scheduling

[0052] Unlike traditional priority-based preemptive scheduling, this architecture uses a simple round-robin scheduling approach. Each core continuously checks and executes its assigned tasks through a while(1) loop. This scheduling approach greatly simplifies the scheduling logic and reduces the overhead of context switching.

[0053] like Figure 2 As shown, taking dual-core as an example, the process of the above simplified multi-core architecture is:

[0054] Step 1.1: Get the Core ID of the currently running core and assign an independent stack space to the core corresponding to the Core ID. For example, in a dual-core system, if the Core ID of the currently running core is n, set the stack pointer MSP to core n, which is the top of the running stack space.

[0055] Step 1.2: Obtain a task index, and when the task index meets a preset condition, obtain the Core ID of the currently running core in real time.

[0056] After obtaining the task index, first determine whether the index number is less than the maximum task number. If not, reset the index number and index again one by one; if not, obtain the Core ID of the currently running core.

[0057] It should be noted that multiple cores are running dynamically. When a task is indexed, the Core ID of the currently running core is not determined. Therefore, it is necessary to obtain the Core ID of the currently running core in real time and then compare the Core ID with the TaskCoreId.

[0058] In step 1.3, when the CoreID of the currently running core is the same as the TaskCoreId obtained by indexing, a serial port menu command is issued.

[0059] When creating a task, the core on which the task is to be run is specified by configuring TaskCoreId. Therefore, by comparing CoreID with TaskCoreId, you can determine on which core the task is to be run.

[0060] If the comparison result shows that the Core ID and TaskCoreId are the same, the next task is run; if the comparison result shows that the Core ID and TaskCoreId are different, the index number is incremented and the task index is re-entered.

[0061] Step 2: Based on the designed multi-core architecture, create UART tasks, command processing tasks and queues, and design a multi-core verification command menu based on the serial port.

[0062] like Figure 3 As shown in the figure, the command menu for multi-core verification based on a serial port consists of commands, core selection parameters, and test case parameters. Commands specify the test case to be executed. Core selection parameters specify which core the test case will run on. Test case parameters are used to pass test case parameters, increasing test case flexibility.

[0063] The kernel selection parameter can be expressed as C[n][n+1][n+2] (n=0,1,2…).

[0064] Taking a dual-core system as an example, C0 indicates that Core 0 is selected, and C1 indicates that Core 1 is selected. The test case is run only on the selected core.

[0065] C01 indicates that Core 0 and Core 1 are selected. The test case runs on both Core 0 and Core 1 simultaneously.

[0066] Alternatively, if there are three cores, the core selection commands can be C0, C1, C2, C01, C12, C012, where C012 means that the test case runs simultaneously on Core0, Core1 and Core2.

[0067] The above command structure uses a serial port menu command-based approach to select a specified core through simple commands, allowing test cases to run on different cores.

[0068] In step 3, the UART task receives and parses the serial port command for multi-core verification, and sends the command to the specified core through the queue according to the parsing result.

[0069] like Figure 4As shown in the figure, after the UART task receives the serial port command for multi-core verification, it performs the following steps:

[0070] Parse the received serial port characters according to the structure of the multi-core verification command menu to obtain the information of command + core selection parameters + test case parameters;

[0071] The core to execute the task is selected based on the parsed core selection parameters, and the command + test case parameter information is sent to the core to execute the task through the command queue.

[0072] Step 4: The designated core executes the command processing task and calls the test case.

[0073] After the designated core receives the command queue, it executes the following steps:

[0074] Read the command queue;

[0075] Find the corresponding test case according to the read command and obtain the test case parameters;

[0076] Based on the obtained test case parameters, the test case is executed and the test results are output (such as printing).

[0077] Taking dual-core Core n and Core n+1 (n=0, 1, 2 ...) as an example, based on the multi-core architecture of the present invention, implementing multi-core verification requires implementing three tasks and two queues for communication between tasks.

[0078] (1) Command receiving task

[0079] Create a command receiving task and assign it to the Main Core (Core n or Core n+1, configurable). This task receives and parses UART commands. After determining the core selection parameters, it queues and sends them to different command processing tasks.

[0080] (2) Command processing task n

[0081] Create a command processing task and specify it to be run by Core n. This task reads commands and parameters from the queue, then calls the corresponding test case and prints the return result.

[0082] (3) Command processing task n+1

[0083] Create a command processing task and specify it to be run by Core n+1. This task reads commands and parameters from the queue, calls the corresponding test case, and prints the return results.

[0084] (4) Command queue n

[0085] Create a command queue for Main Core to pass command messages to Core n.

[0086] (5) Command queue n+1

[0087] Create a command queue for the Main Core to pass command messages to Core n+1.

[0088] like Figure 5 As shown, taking dual-core as an example, the process of multi-core chip verification based on the designed multi-core architecture and multi-core verification command menu is as follows:

[0089] After power-on, the UART is initialized and independent stack space is assigned to each core;

[0090] Create a command receiving task and configure TaskCoreId=n;

[0091] Create command processing task n and configure TaskCoreId=n;

[0092] Create command processing task n+1 and configure TaskCoreId=n+1. It should be noted that if the number of cores is greater than 2, you can continue to create corresponding command processing tasks.

[0093] After all cores' command processing tasks are created, command queues are created. The number of command queues created is the same as the number of cores.

[0094] The command receiving task and the command processing task check and execute the tasks according to the while (1) loop. After the command receiving task receives the UART command, it parses it in combination with the structure of the multi-core verification command menu and sends the command to the specified core through the queue according to the parsing result.

[0095] The designated core executes the command processing task, calls the corresponding test case for testing according to the received command, and outputs the test results.

[0096] Based on the same inventive concept as the aforementioned method, the present invention further provides a device for multi-core chip verification, comprising:

[0097] A multi-core architecture design module, used to design a multi-core architecture for managing multi-core operations;

[0098] Task creation module, used to create UART tasks, command processing tasks and queues based on the designed multi-core architecture;

[0099] Multi-core verification command design module, used to design multi-core verification command menu based on serial port in multi-core architecture;

[0100] The multi-core verification command receiving and parsing module is used by the UART task to receive and parse serial port commands for multi-core verification, and send the commands to the designated core through the queue based on the parsing results;

[0101] The task execution module is used to execute the specified core command to process the task and call the test case.

[0102] It should be noted that the implementation solution provided by the device is similar to the implementation solution recorded in the above method. Therefore, the specific limitations in the implementation of the aforementioned modules can be found in the limitations of the method for implementing multi-core chip verification above, and will not be repeated here.

[0103] Based on the same inventive concept as the aforementioned method, the present invention also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method for multi-core chip verification are implemented.

[0104] Based on the same inventive concept as the aforementioned method, the present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method for multi-core chip verification.

[0105] In summary, the multi-core architecture designed in this invention is simple and easy to implement. Using this architecture, a single project can manage multi-core operations without relying on an operating system. This not only avoids the additional code space requirements and complexity introduced by using a multi-core operating system, but also simplifies debugging and problem analysis, making functional verification of multi-core chips more efficient and straightforward.

[0106] This invention uses a UART-based command menu system that supports multiple cores. Testers can use the serial port assistant to send commands to select a specific core to run test cases. This mechanism of selecting cores through commands makes it easy to run test cases on different cores. This avoids the tedious step of repeatedly downloading code to each core for each test, greatly simplifying the test operation process.

[0107] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0111] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for multi-core chip verification, characterized in that: Independent of the multi-core operating system, the specified core is selected based on the UART menu command to run the test cases, including: A streamlined multi-core architecture is designed for managing multi-core operation; in the multi-core architecture, all cores are started from the same address and run the same set of program codes, and the execution logic of different cores is distinguished by using the Core ID of the currently running core in the program; each core uses an independent stack space; the core running the task is specified when the task is created; different tasks send and receive messages to each other through queues; Based on the designed multi-core architecture, UART tasks, command processing tasks and queues are created, and a multi-core verification command menu is designed based on the serial port, wherein the multi-core verification command menu designed based on the serial port includes: commands for specifying the test cases to be executed; core selection parameters for specifying which core the test cases will run on; and test case parameters for passing test case parameters; The UART task and command processing task check and execute the task according to the while (1) loop. After the UART task receives the UART command, it parses it in combination with the structure of the multi-core verification command menu and sends the command to the specified core through the queue according to the parsing result. The designated core executes the command processing task, calls the corresponding test case for testing according to the received command, and outputs the test results.

2. The method for multi-core chip verification according to claim 1, characterized in that: During the initialization phase, the multi-core architecture specifies an independent stack space for each core.

3. The method for multi-core chip verification according to claim 1, characterized in that: Each core uses task polling scheduling to cyclically check and execute the assigned tasks in sequence.

4. The method for multi-core chip verification according to claim 3, characterized in that: The task polling scheduling uses an infinite loop polling to execute each task, and when the CoreID of the current running core is the same as the TaskCoreId of the running core specified by the task, the specified task is executed.

5. The method for multi-core chip verification according to claim 1, characterized in that: The core selection parameter is set to C[n][n+1][n+2]..., n=0,1,2..., where n corresponds to the CoreID of the core.

6. A device for multi-core chip verification, characterized in that: Independent of multi-core operating system, the specified core is selected to run test cases based on UART menu commands, including A multi-core architecture design module is used to design a streamlined multi-core architecture for managing multi-core operation; in the multi-core architecture, all cores are started from the same address and run the same set of program codes, and the Core ID of the currently running core is used in the program to distinguish the execution logic of different cores; each core uses an independent stack space; the core running the task is specified when the task is created; different tasks send and receive messages to each other through queues; Task creation module, used to create UART tasks, command processing tasks and queues based on the designed multi-core architecture; Multi-core verification command design module, used to design multi-core verification command menu based on serial port in multi-core architecture; The command menu for multi-core verification based on serial port design includes: commands, which are used to specify the test cases to be executed; core selection parameters, which are used to specify which core the test cases will run on; and test case parameters, which are used to pass the parameters of the test cases; The multi-core verification command receiving and parsing module is used for the UART task and the command processing task to check and execute the task according to the while (1) loop. After the UART task receives the UART command, it is parsed in combination with the structure of the multi-core verification command menu, and the command is sent to the specified core through the queue according to the parsing result; The task execution module is used to execute the specified core command processing task, call the corresponding test case for testing according to the received command, and output the test results.

7. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method for multi-core chip verification as described in any one of claims 1 to 5 are implemented.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for multi-core chip verification described in any one of claims 1 to 5 are implemented.

Images