Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure, located on the SOI substrate; a first source / drain region and a second source / drain region, located on both sides of the gate structure; a trench conduction structure, located on a side of the first source / drain region away from the gate structure, and located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is connected to the lower substrate through the trench conduction structure. The technical solution of the present invention can dissipate the heat generated during the operation of the semiconductor device in a timely manner, thereby improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] The advantage of the SOI (Semiconductor-On-Insulator) process is that the gate has better control over the channel, which reduces the short channel effect and thus eliminates the need to compensate for the drop in threshold voltage by doping, or at least reduces the doping concentration to a lower level so that scattering between carriers and doping ions is prevented, thereby improving carrier mobility and reducing threshold voltage fluctuations caused by random doping fluctuations that occur as the number of doping ions increases.

[0003] However, the SOI substrate is currently limited by the self-heating effect. The insulating buried layer in the SOI substrate is an excellent insulator, and it is difficult to dissipate the heat generated during operation, causing the temperature of the device to rise, which in turn causes the mobility of the device to decrease, thereby causing the channel current to decrease.

[0004] Therefore, how to dissipate the heat generated during the operation of the device in a timely manner is a problem that needs to be solved urgently. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can dissipate the heat generated during the operation of the semiconductor device in a timely manner, thereby improving the performance of the semiconductor device.

[0006] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0007] An SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0008] A gate structure, located on the SOI substrate;

[0009] A first source / drain region and a second source / drain region are located on both sides of the gate structure;

[0010] A trench conduction structure is located on a side of the first source / drain region away from the gate structure and is located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is conductively connected to the underlying substrate through the trench conduction structure.

[0011] Optionally, the first source / drain region is a source region or a drain region.

[0012] Optionally, a top surface of the trench conduction structure is flush with a top surface of the semiconductor layer.

[0013] Optionally, a trench isolation structure is formed around the semiconductor device, and the trench isolation structure extends from the semiconductor layer or the trench conductive structure into the underlying substrate.

[0014] Optionally, a portion of the trench isolation structure is formed in the trench conduction structure, or a portion of the trench isolation structure is located on a side of the trench conduction structure away from the gate structure.

[0015] Optionally, the first source / drain region is formed in at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed in the semiconductor layer on the other side of the gate structure; or, the first source / drain region is formed on at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed on the semiconductor layer on the other side of the gate structure.

[0016] Optionally, the trench conduction structure is made of semiconductor material or metal.

[0017] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0018] Providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0019] forming a groove in the semiconductor layer and the insulating buried layer, wherein the groove exposes the underlying substrate;

[0020] forming a trench conduction structure in the trench;

[0021] forming a gate structure on the SOI substrate;

[0022] forming a first source / drain region and a second source / drain region on both sides of the gate structure;

[0023] The trench conduction structure is located at a side of the first source / drain region away from the gate structure, and the first source / drain region is conductively connected to the underlying substrate through the trench conduction structure.

[0024] Optionally, the first source / drain region is a source region or a drain region.

[0025] Optionally, a top surface of the trench conduction structure is flush with a top surface of the semiconductor layer.

[0026] Optionally, after forming the trench conduction structure, the method for manufacturing the semiconductor device further includes:

[0027] A trench isolation structure is formed, wherein the trench isolation structure extends from the semiconductor layer or the trench conductive structure into the underlying substrate.

[0028] Optionally, a portion of the trench isolation structure is formed in the trench conduction structure, or a portion of the trench isolation structure is located on a side of the trench conduction structure away from the gate structure.

[0029] Optionally, the first source / drain region is formed in at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed in the semiconductor layer on the other side of the gate structure; or, the first source / drain region is formed on at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed on the semiconductor layer on the other side of the gate structure.

[0030] Optionally, the trench conduction structure is formed by an epitaxial process.

[0031] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0032] 1. The semiconductor device of the present invention comprises: an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure located on the SOI substrate; a first source / drain region and a second source / drain region located on both sides of the gate structure; a trench conduction structure located on a side of the first source / drain region away from the gate structure and located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is connected to the lower substrate through the trench conduction structure, so that the heat generated during the operation of the semiconductor device can be dissipated in time, thereby improving the performance of the semiconductor device.

[0033] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing an SOI substrate, wherein the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming grooves in the semiconductor layer and the insulating buried layer, wherein the grooves expose the lower substrate; forming a trench conduction structure in the groove; forming a gate structure on the SOI substrate; forming a first source / drain region and a second source / drain region on both sides of the gate structure; wherein the trench conduction structure is located on a side of the first source / drain region away from the gate structure, and the first source / drain region is conductively connected to the lower substrate through the trench conduction structure, so that the heat generated during the operation of the semiconductor device can be dissipated in time, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0036] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0037] Figure 4~Figure 10 yes Figure 3 A device schematic diagram of a method for manufacturing a semiconductor device is shown.

[0038] Among them, Figure 1 to Figure 10 The reference numerals are described as follows:

[0039] 101 - lower substrate; 102 - buried insulating layer; 103 - semiconductor layer; 11 - trench; 111 - first patterned mask layer; 12 - trench conduction structure; 13 - trench isolation structure; 131 - second patterned mask layer; 14 - gate structure; 15 - first source / drain region; 16 - second source / drain region. DETAILED DESCRIPTION

[0040] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] An embodiment of the present invention provides a semiconductor device, comprising: an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; a gate structure, located on the SOI substrate; a first source / drain region and a second source / drain region, located on both sides of the gate structure; a trench conduction structure, located on a side of the first source / drain region away from the gate structure, and located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is conductively connected to the lower substrate through the trench conduction structure.

[0042] See below Figure 1~Figure 2 The semiconductor device provided by this embodiment is described in more detail. Figure 1~Figure 2 It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0043] The SOI (Semiconductor-On-Insulator) substrate includes, from bottom to top, a lower substrate 101 , an insulating buried layer 102 and a semiconductor layer 103 .

[0044] The lower substrate 101 and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0045] The gate structure 14 is located on the SOI substrate.

[0046] The gate structure 14 may include a gate dielectric layer, a gate layer and a sidewall spacer. The gate dielectric layer and the gate layer are formed on the SOI substrate from bottom to top, and the sidewall spacer is formed on the sidewalls of the gate dielectric layer and the gate layer.

[0047] The first source / drain region 15 and the second source / drain region 16 are located at two sides of the gate structure 14 .

[0048] The first source / drain region 15 is a source region or a drain region. When the first source / drain region 15 is a source region, the second source / drain region 16 is a drain region; when the first source / drain region 15 is a drain region, the second source / drain region 16 is a source region.

[0049] The trench conduction structure 12 is located on a side of the first source / drain region 15 away from the gate structure 14, and is located in the semiconductor layer 103 and the insulating buried layer 102, that is, the trench conduction structure 12 penetrates the semiconductor layer 103 and the insulating buried layer 102 and is electrically connected to the underlying substrate 101; wherein, the first source / drain region 15 is conductively connected to the underlying substrate 101 through the trench conduction structure 12.

[0050] In one embodiment, the trench conductive structure 12 is made of semiconductor material or metal.

[0051] In one embodiment, the trench conduction structure 12 is made of silicon and is formed by an epitaxial process.

[0052] Since the first source / drain region 15 is a source region or a drain region, the source region or the drain region is conductively connected to the underlying substrate 101 , and the source region and the drain region are not conductively connected to the underlying substrate 101 at the same time.

[0053] The first source / drain region 15 is formed at least in the semiconductor layer 103 and / or the trench conduction structure 12 on one side of the gate structure 14, and the second source / drain region 16 is formed in the semiconductor layer 103 on the other side of the gate structure 14; or, the first source / drain region 15 is formed on at least the semiconductor layer 103 and / or the trench conduction structure 12 on one side of the gate structure 14, and the second source / drain region 16 is formed on the semiconductor layer 103 on the other side of the gate structure 14.

[0054] Wherein, when the first source / drain region 15 is formed in the semiconductor layer 103 and the trench conduction structure 12 on one side of the gate structure 14, the first source / drain region 15 extends from the semiconductor layer 103 on one side of the gate structure 14 to the trench conduction structure 12; when the first source / drain region 15 is formed on the semiconductor layer 103 and the trench conduction structure 12 on one side of the gate structure 14, Figure 1 and Figure 2 As shown, the first source / drain region 15 extends from the semiconductor layer 103 on one side of the gate structure 14 to the trench conductive structure 12. Figure 1 and Figure 2 As shown, the first source / drain region 15 and the second source / drain region 16 are raised source / drain regions (RSD, Raised Source / Drain).

[0055] Preferably, the top surface of the semiconductor layer 103 is flush with the top surface of the trench conductive structure 12 , so that a device structure can be formed on the semiconductor layer 103 and the trench conductive structure 12 based on a flat surface.

[0056] A trench isolation structure 13 is formed around the semiconductor device, and the trench isolation structure 13 is used to isolate the semiconductor device from other devices. The other devices may be the semiconductor device, or may be devices different from the semiconductor device.

[0057] The trench isolation structure 13 extends from the semiconductor layer 103 or the trench conductive structure 12 into the lower substrate 101. Figure 1 As shown, a portion of the trench isolation structure 13 is formed in the trench conduction structure 12, or, as shown in FIG. Figure 2 As shown, a portion of the trench isolation structure 13 is located on a side of the trench conduction structure 12 away from the gate structure 14 .

[0058] When a portion of the trench isolation structure 13 is formed in the trench conduction structure 12, the trench isolation structure 13 at least extends from the top surface of the trench conduction structure 12 toward the lower substrate 101 until the bottom surface of the trench isolation structure 13 contacts the top surface of the lower substrate 101; preferably, the trench isolation structure 13 extends into the lower substrate 101.

[0059] When a portion of the trench isolation structure 13 is located on a side of the trench conduction structure 12 away from the gate structure 14, the trench isolation structure 13 at least extends from the top surface of the semiconductor layer 103 or the trench conduction structure 12 toward the lower substrate 101 until the bottom surface of the trench isolation structure 13 contacts the top surface of the buried oxide layer 102; preferably, the trench isolation structure 13 extends into the lower substrate 101.

[0060] The top surface of the trench isolation structure 13 is flush with the top surface of the semiconductor layer 103 , or is slightly lower than or slightly higher than the top surface of the semiconductor layer 103 .

[0061] The trench isolation structure 13 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0062] From the above content, it can be seen that since the trench conduction structure 12 is formed in the semiconductor layer 103 and the insulating buried layer 102 on the side of the first source / drain region 15 away from the gate structure 14, the first source / drain region 15 can be connected to the lower substrate 101 through the trench conduction structure 12, so that the heat generated in the semiconductor layer 103 during the operation of the semiconductor device can be quickly transferred to the lower substrate 101 through the trench conduction structure 12, and then dissipated in time through the lower substrate 101, thereby avoiding the temperature increase of the semiconductor device, and then avoiding the reduction of the mobility of the semiconductor device, thereby avoiding the reduction of the channel current.

[0063] In addition, when voltage is applied to the gate structure 14 to make the semiconductor device work, electrons move from the source region to the drain region, causing the semiconductor device to generate more heat on the drain region side. Therefore, when the first source / drain region 15 is the drain region, the heat can be dissipated faster.

[0064] In summary, the semiconductor device provided by the present invention comprises: an SOI substrate, the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; a gate structure, located on the SOI substrate; a first source / drain region and a second source / drain region, located on both sides of the gate structure; a trench conduction structure, located on the side of the first source / drain region away from the gate structure, and located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is connected to the lower substrate through the trench conduction structure. The semiconductor device of the present invention can dissipate the heat generated during the operation of the semiconductor device in a timely manner, thereby improving the performance of the semiconductor device.

[0065] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 3 , Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0066] Step S1, providing an SOI substrate, wherein the SOI substrate comprises, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer;

[0067] Step S2, forming a groove in the semiconductor layer and the insulating buried layer, wherein the groove exposes the underlying substrate;

[0068] Step S3, forming a trench conduction structure in the trench;

[0069] Step S4, forming a gate structure on the SOI substrate;

[0070] Step S5, forming a first source / drain region and a second source / drain region on both sides of the gate structure; wherein the trench conduction structure is located on a side of the first source / drain region away from the gate structure, and the first source / drain region is conductively connected to the underlying substrate through the trench conduction structure.

[0071] See below Figure 1~Figure 2 , Figure 4~Figure 10 The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figure 1~Figure 2 , Figure 4~Figure 10 It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0072] Follow step S1, refer to Figure 4 , providing an SOI substrate, wherein the SOI substrate includes, from bottom to top, a lower substrate 101, an insulating buried layer 102 and a semiconductor layer 103.

[0073] The lower substrate 101 and the semiconductor layer 103 may be made of any suitable semiconductor material, including but not limited to: Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, other III / V or II / VI compound semiconductors and other semiconductor materials, and the insulating buried layer 102 is, for example, a silicon oxide layer.

[0074] According to step S2, refer to Figure 5 , a trench 11 is formed in the semiconductor layer 103 and the insulating buried layer 102, and the trench 11 exposes the underlying substrate 101. That is, the trench 11 penetrates the semiconductor layer 103 and the insulating buried layer 102, and the bottom of the trench 11 exposes the underlying substrate 101.

[0075] The step of forming the groove 11 may include: first, forming a first patterned mask layer 111 on the semiconductor layer 103; then, using the first patterned mask layer 111 as a mask to sequentially etch the semiconductor layer 103 and the buried insulating layer 102 to form the groove 11.

[0076] The material of the first patterned mask layer 111 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and silicon carbide nitride, etc., or the first patterned mask layer 111 may be photoresist.

[0077] According to step S3, refer to Figure 6 , a trench conduction structure 12 is formed in the trench 11 .

[0078] Before or after forming the trench conductive structure 12 in the trench 11 (eg Figure 7 As shown), the first patterned mask layer 111 is removed.

[0079] In one embodiment, the trench conductive structure 12 is made of semiconductor material or metal.

[0080] In another embodiment, the trench conductive structure 12 is made of silicon formed by an epitaxial process.

[0081] When the trench conductive structure 12 is made of semiconductor material, the trench conductive structure 12 may be grown using an epitaxial process.

[0082] Preferably, the top surface of the semiconductor layer 103 is flush with the top surface of the trench conductive structure 12 , so that a device structure can be formed on the semiconductor layer 103 and the trench conductive structure 12 based on a flat surface.

[0083] See also Fig. 9After forming the trench conduction structure 12 , the method for manufacturing the semiconductor device further includes: forming a trench isolation structure 13 , wherein the trench isolation structure 13 extends from the semiconductor layer 103 or the trench conduction structure 12 into the lower substrate 101 .

[0084] The trench isolation structure 13 is formed around the semiconductor device, and the trench isolation structure 13 is used to isolate the semiconductor device from other devices.

[0085] The other device may be the semiconductor device, or a device different from the semiconductor device.

[0086] Since the temperature used when forming the trench conduction structure 12 by the epitaxial process is very high, forming the trench isolation structure 13 after forming the trench conduction structure 12 can dissipate the heat generated by the epitaxial process in time and avoid the influence of high temperature on subsequent processes.

[0087] like Figure 1 As shown, a portion of the trench isolation structure 13 is formed in the trench conduction structure 12, or, as shown in FIG. Figure 2 As shown, a portion of the trench isolation structure 13 is located on a side of the trench conduction structure 12 away from the gate structure 14 .

[0088] The steps of forming the trench isolation structure 13 may include: first, Figure 8 As shown, a second patterned mask layer 131 is formed on the semiconductor layer 103 and the trench conductive structure 12; then, the SOI substrate is etched using the second patterned mask layer 131 as a mask, or the SOI substrate and the trench conductive structure 12 are etched to form a groove (not shown); then, an insulating material is filled in the groove to form a trench isolation structure 13 in the groove; then, as shown Fig. 9 As shown, the second patterned mask layer 131 is removed. In one embodiment, a portion of the height of the trench isolation structure 13 may be removed.

[0089] The material of the second patterned mask layer 131 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and silicon carbide nitride, etc., or the second patterned mask layer 131 may be photoresist.

[0090] When a portion of the trench isolation structure 13 is formed in the trench conduction structure 12, the trench isolation structure 13 at least extends from the top surface of the trench conduction structure 12 toward the lower substrate 101 until the bottom surface of the trench isolation structure 13 contacts the top surface of the lower substrate 101; preferably, the trench isolation structure 13 extends into the lower substrate 101.

[0091] When a portion of the trench isolation structure 13 is located on a side of the trench conduction structure 12 away from the gate structure 14, the trench isolation structure 13 at least extends from the top surface of the semiconductor layer 103 or the trench conduction structure 12 toward the lower substrate 101 until the bottom surface of the trench isolation structure 13 contacts the top surface of the buried oxide layer 102; preferably, the trench isolation structure 13 extends into the lower substrate 101.

[0092] The top surface of the trench isolation structure 13 is flush with the top surface of the semiconductor layer 103 , or is slightly lower than or slightly higher than the top surface of the semiconductor layer 103 .

[0093] The trench isolation structure 13 may be made of insulating materials such as silicon oxide or silicon oxynitride.

[0094] According to step S4, refer to Fig.10 , forming a gate structure 14 on the SOI substrate.

[0095] The gate structure 14 may include a gate dielectric layer, a gate layer and a sidewall spacer. The gate dielectric layer and the gate layer are formed on the SOI substrate from bottom to top, and the sidewall spacer is formed on the sidewalls of the gate dielectric layer and the gate layer.

[0096] According to step S5, refer to Fig.10 , forming a first source / drain region 15 and a second source / drain region 16 on both sides of the gate structure 14; wherein the trench conduction structure 12 is located on a side of the first source / drain region 15 away from the gate structure 14, and the first source / drain region 15 is conductively connected to the underlying substrate 101 through the trench conduction structure 12.

[0097] The first source / drain region 15 is a source region or a drain region. When the first source / drain region 15 is a source region, the second source / drain region 16 is a drain region; when the first source / drain region 15 is a drain region, the second source / drain region 16 is a source region.

[0098] Since the first source / drain region 15 is a source region or a drain region, the source region or the drain region is conductively connected to the underlying substrate 101 , and the source region and the drain region are not conductively connected to the underlying substrate 101 at the same time.

[0099] The first source / drain region 15 is formed at least in the semiconductor layer 103 and / or the trench conduction structure 12 on one side of the gate structure 14, and the second source / drain region 16 is formed in the semiconductor layer 103 on the other side of the gate structure 14; or, the first source / drain region 15 is formed on at least the semiconductor layer 103 and / or the trench conduction structure 12 on one side of the gate structure 14, and the second source / drain region 16 is formed on the semiconductor layer 103 on the other side of the gate structure 14.

[0100] Wherein, when the first source / drain region 15 is formed in the semiconductor layer 103 and the trench conduction structure 12 on one side of the gate structure 14, the first source / drain region 15 extends from the semiconductor layer 103 on one side of the gate structure 14 to the trench conduction structure 12; when the first source / drain region 15 is formed on the semiconductor layer 103 and the trench conduction structure 12 on one side of the gate structure 14, Figure 1 and Figure 2 As shown, the first source / drain region 15 extends from the semiconductor layer 103 on one side of the gate structure 14 to the trench conductive structure 12. Figure 1 and Figure 2 As shown, the first source / drain region 15 and the second source / drain region 16 are raised source / drain regions (RSD, Raised Source / Drain).

[0101] From the above content, it can be seen that since the trench conduction structure 12 is formed in the semiconductor layer 103 and the insulating buried layer 102 on the side of the first source / drain region 15 away from the gate structure 14, the first source / drain region 15 can be connected to the lower substrate 101 through the trench conduction structure 12, so that the heat generated in the semiconductor layer 103 during the operation of the semiconductor device can be quickly transferred to the lower substrate 101 through the trench conduction structure 12, and then dissipated in time through the lower substrate 101, thereby avoiding the temperature increase of the semiconductor device, and then avoiding the reduction of the mobility of the semiconductor device, thereby avoiding the reduction of the channel current.

[0102] In addition, when voltage is applied to the gate structure 14 to make the semiconductor device work, electrons move from the source region to the drain region, causing the semiconductor device to generate more heat on the drain region side. Therefore, when the first source / drain region 15 is the drain region, the heat can be dissipated faster.

[0103] In summary, the manufacturing method of the semiconductor device provided by the present invention includes: providing an SOI substrate, the SOI substrate includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top; forming grooves in the semiconductor layer and the insulating buried layer, the grooves exposing the lower substrate; forming a groove conduction structure in the groove; forming a gate structure on the SOI substrate; forming a first source / drain region and a second source / drain region on both sides of the gate structure; wherein the groove conduction structure is located on the side of the first source / drain region away from the gate structure, and the first source / drain region is connected to the lower substrate through the groove conduction structure. The manufacturing method of the semiconductor device of the present invention can dissipate the heat generated during the operation of the semiconductor device in a timely manner, thereby improving the performance of the semiconductor device.

[0104] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: An SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; A gate structure, located on the SOI substrate; A first source / drain region and a second source / drain region are located on both sides of the gate structure; A trench conduction structure, located on a side of the first source / drain region away from the gate structure and located in the semiconductor layer and the insulating buried layer; wherein the first source / drain region is conductively connected to the lower substrate through the trench conduction structure; a trench isolation structure, a portion of which is formed in the trench conduction structure; The trench conduction structure is formed by an epitaxial process, and the trench isolation structure is formed after the trench conduction structure is formed.

2. The semiconductor device according to claim 1, wherein The first source / drain region is a source region or a drain region.

3. The semiconductor device according to claim 1, wherein The top surface of the trench conduction structure is flush with the top surface of the semiconductor layer.

4. The semiconductor device according to claim 1, wherein The trench isolation structure extends from the trench conduction structure into the underlying substrate.

5. The semiconductor device according to claim 1, wherein: The first source / drain region is formed in at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed in the semiconductor layer on the other side of the gate structure; or, the first source / drain region is formed on at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed on the semiconductor layer on the other side of the gate structure.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The trench conductive structure is made of semiconductor material.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing an SOI substrate, the SOI substrate comprising, from bottom to top, a lower substrate, an insulating buried layer and a semiconductor layer; forming a groove in the semiconductor layer and the insulating buried layer, wherein the groove exposes the underlying substrate; Forming a trench conduction structure in the trench by using an epitaxial process; forming a trench isolation structure after forming the trench conduction structure, wherein a portion of the trench isolation structure is formed in the trench conduction structure; forming a gate structure on the SOI substrate; forming a first source / drain region and a second source / drain region on both sides of the gate structure; The trench conduction structure is located at a side of the first source / drain region away from the gate structure, and the first source / drain region is conductively connected to the underlying substrate through the trench conduction structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The first source / drain region is a source region or a drain region.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The top surface of the trench conduction structure is flush with the top surface of the semiconductor layer.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The trench isolation structure extends from the trench conduction structure into the underlying substrate.

11. The method for manufacturing a semiconductor device according to claim 7, wherein: The first source / drain region is formed in at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed in the semiconductor layer on the other side of the gate structure; or, the first source / drain region is formed on at least the semiconductor layer and / or the trench conduction structure on one side of the gate structure, and the second source / drain region is formed on the semiconductor layer on the other side of the gate structure.

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