A high-precision PPS phase following method based on FPGA carry chain
By using the carry chain method in FPGA, the problems of high hardware dependence and complexity in the traditional PPS time reference phase follow method are solved, and high-precision and low-cost PPS phase follow are achieved, which improves the real-time and stability of the system.
Patent Information
- Application Number
- CN202410937811.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2044-07-12
AI Technical Summary
Traditional PPS time reference phase following methods require additional hardware support and complex calibration processes, resulting in increased system complexity and cost, and loop locking and loss of phase-locking loops reduce real-time and stability.
Using the FPGA-based carry chain method, the high-precision phase difference measurement and follow-up is achieved by receiving external PPS signals and processing them in the carry4 carry chain inside the FPGA. The global clock, register latch, period counting and other means are used to achieve high-precision phase difference measurement and follow-up, avoiding the extra Hardware dependency.
It realizes all digital and high-precision PPS phase follow-up, improves real-time and stability, reduces system complexity and cost, and eliminates hardware resources such as ADC and phase-locked loops.
Smart Images
Figure CN118473401B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of high-precision time-frequency transmission and synchronization, and in particular to a high-precision PPS phase following method based on FPGA carry chain. Background Art
[0002] In areas such as collaborative detection, navigation and positioning, communications, and digital communications, high-precision time-frequency synchronization is crucial for ensuring the proper operation of distributed network systems, such as wireless sensor networks and distributed radar systems. The quality of time-frequency synchronization directly impacts the overall performance of distributed systems. Some distributed systems with extremely high inter-node synchronization requirements even require picosecond-level synchronization accuracy. Therefore, a high-precision phase-following method capable of providing an externally inputted time reference is urgently needed to provide reliable time-frequency reference synchronization services for distributed systems.
[0003] The traditional PPS time reference phase following method achieves phase synchronization between the internal signal and the external time reference through the ADC module sampling the reference frequency homologous to the PPS and the internal frequency phase-locked loop. This brings the following problems: ① Following the PPS phase requires additional hardware support for the reference frequency homologous to the PPS; ② Modules such as the phase-locked loop require additional hardware circuit support such as the ADC module, and require complex calibration and debugging, which increases the complexity and cost of the system; ③ The loop locking and recapture of the phase-locked loop will cause system delays, reducing the real-time and stability of the PPS phase following. Summary of the Invention
[0004] Based on this, it is necessary to provide a high-precision PPS phase following method and circuit based on FPGA carry chain to address the above technical problems.
[0005] A high-precision PPS phase following method based on FPGA carry chain, the method comprising:
[0006] Receive an external PPS signal and input the external PPS signal into the FPGA internal carry4 carry chain;
[0007] When the rising edge of the global clock arrives, the carry4 carry chain output is latched using a two-stage register and converted into a binary number;
[0008] When the carry4 carry chain output is not all 1s, the single-cycle phase difference is calculated and the single-cycle valid update flag is set to 1;
[0009] When the carry4 carry chain outputs are all 1, the single-cycle valid update flag is set to 0, and the rising edge of the global clock is continuously counted until the single-cycle valid update flag is 1, and the cycle count value at the current moment is recorded;
[0010] According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single-cycle phase difference, cycle detection is performed to obtain the phase difference, and high-precision PPS phase tracking is performed according to the phase difference.
[0011] In one embodiment, the carry4 carry chain is formed by cascading multiple carry4 carry units; the number of cascades of the carry4 carry chain is determined according to the size of the cycle of the global clock; and the maximum cascade height of the carry4 carry chain is determined by the FPGA chip column height limit.
[0012] In one embodiment, the further embodiment further includes: when the carry4 carry chain output is not all 1s, it indicates that the current single-cycle phase difference value is valid;
[0013] According to the binary number, the number of minimum delay units of the carry4 unit is determined , get the minimum delay unit time interval of the carry4 carry unit of FPGA as ;
[0014] According to the stated quantity and the time interval is , calculate the single cycle phase difference as:
[0015] ;
[0016] in, Represents the single cycle phase difference.
[0017] In one embodiment, when the single-cycle valid update flag is 1, the cycle detection results include: normal cycle, delayed cycle, and advanced cycle.
[0018] In one embodiment, when the cycle detection result is that the cycle is normal, the cycle ambiguity is 0; and the method further includes: performing cycle detection based on the cycle count value, the frequency of the global clock, the period of the global clock, and the single-cycle phase difference to obtain a phase difference of:
[0019] ;
[0020] in, Indicates the phase difference.
[0021] In one embodiment, when the cycle detection result is a cycle hysteresis, the method further comprises: calculating a cycle ambiguity according to the cycle count value and the frequency of the global clock;
[0022] According to the cycle ambiguity, the period of the global clock and the single-cycle phase difference, the phase difference obtained by performing cycle detection is:
[0023] ;
[0024] Among them, the periodic ambiguity is , Indicates the phase difference.
[0025] In one embodiment, when the cycle detection result is that the cycle is ahead, the method further comprises: calculating the cycle ambiguity according to the cycle count value and the frequency of the global clock;
[0026] According to the cycle ambiguity, the period of the global clock and the single-cycle phase difference, the phase difference obtained by performing cycle detection is:
[0027] ;
[0028] Among them, the periodic ambiguity is , Indicates the phase difference.
[0029] In one embodiment, the method further includes: recording the current cycle ambiguity and the cycle ambiguity flag; when the cycle is normal, the cycle ambiguity flag is updated to 0; when the cycle is delayed, the cycle ambiguity flag is updated to 1; when the cycle is advanced, the cycle ambiguity flag is updated to 2.
[0030] In one embodiment, the cycle count value is equal to the number of internal global clock pulses required for each single-cycle phase difference to effectively update the rising edge of the flag.
[0031] A high-precision PPS phase following circuit based on an FPGA carry chain is provided. The circuit is composed of a logic circuit; the logic circuit includes a carry4 carry chain module, a register, and a clock management module. When the logic circuit is running, it executes the high-precision PPS phase following method based on an FPGA carry chain.
[0032] The above-mentioned high-precision PPS phase following method based on the FPGA carry chain measures the single-cycle phase difference through the carry4 carry unit within the FPGA. In combination with the internal global clock counting method, it solves the period ambiguity problem of the external input reference signal, and updates the total phase difference information between the internal global clock and the external reference signal in real time, achieving fully digital and high-precision phase following of the external 1PPS reference signal. In the above method, the carry4 carry chain has a picosecond delay resolution and a working clock cycle-level phase measurement response time, which can quickly achieve high-precision phase difference measurement and improve the real-time and stability of PPS phase following. In addition, the present invention only uses a digital programmable chip FPGA and does not require hardware resources such as an ADC, a phase-locked loop, and additional sinusoidal frequency signals homologous to the PPS, making the system simple, flexible, and lightweight, reducing system cost and complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 1 is a flow chart of a high-precision PPS phase following method based on an FPGA carry chain in one embodiment;
[0034] Figure 2 A diagram showing the internal structure of an FPGA in a high-precision PPS phase following method based on an FPGA carry chain in one embodiment;
[0035] Figure 3 Schematic diagram of a flow chart of a high-precision PPS phase following method based on FPGA carry chain in another embodiment. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.
[0037] In one embodiment, Figure 1 As shown, a high-precision PPS phase following method based on FPGA carry chain is provided, including the following steps:
[0038] Step 102: Receive an external PPS signal and input the external PPS signal into the carry4 carry chain inside the FPGA.
[0039] Step 104: When the rising edge of the global clock arrives, the carry4 carry chain output is latched using a two-stage register, and the carry4 carry chain output is converted into a binary number.
[0040] Step 106: When the carry4 carry chain output is not all 1s, calculate the single-cycle phase difference and set the single-cycle valid update flag to 1.
[0041] Step 108: When the carry4 carry chain outputs are all 1, the single-cycle valid update flag is set to 0, and the rising edge of the global clock is continuously counted until the single-cycle valid update flag is 1, and the current cycle count value is recorded.
[0042] Step 110 , performing cycle detection to obtain a phase difference based on the cycle count value, the frequency of the global clock, the cycle of the global clock, and the single-cycle phase difference, and performing high-precision PPS phase tracking based on the phase difference.
[0043] In the above-mentioned high-precision PPS phase following method based on the FPGA carry chain, the single-cycle phase difference is measured by the carry4 carry unit within the FPGA. In combination with the internal global clock counting method, the period ambiguity problem of the external input reference signal is solved, and the total phase difference information between the internal global clock and the external reference signal is updated in real time, achieving fully digital and high-precision phase following of the external 1PPS reference signal. In the above-mentioned method, the carry4 carry chain has a picosecond delay resolution and a working clock cycle-level phase measurement response time, which can quickly achieve high-precision phase difference measurement and improve the real-time and stability of PPS phase following. In addition, the present invention only uses a digital programmable chip FPGA and does not require hardware resources such as an ADC, a phase-locked loop, and additional sinusoidal frequency signals homologous to the PPS, making the system simple, flexible, and lightweight, reducing system cost and complexity.
[0044] The framework of the method of the present invention is as follows Figure 2 As shown, the FPGA includes single-cycle phase difference measurement, cycle ambiguity detection and a global clock unit.
[0045] For single-cycle phase difference measurement, in one embodiment, a carry4-carry chain is formed by cascading multiple carry4-carry units; the number of cascaded carry4-carry chains is determined based on the size of the global clock cycle; and the maximum cascade height of the carry4-carry chain is determined by the FPGA chip row height limit. In this embodiment, the size of the global clock cycle within the FPGA can also determine the phase difference measurement range, and the position of the first carry4-carry unit is fixed within the FPGA. Due to the physical placement constraints of the carry4-carry unit, the remaining carry4-carry units are automatically placed above the previous carry4-carry unit. The maximum cascade height is determined by the FPGA chip row height limit. The external input PPS reference signal is input from the first carry4-carry unit in the carry chain and begins to propagate forward.
[0046] In another embodiment, when the carry4 carry chain output is not all 1, it indicates that the current single-cycle phase difference value is valid; according to the binary number, the number of minimum delay units of the carry4 carry unit is determined. , get the minimum delay unit time interval of the carry4 carry unit of FPGA as ; According to quantity and the time interval is , calculate the single cycle phase difference as:
[0047] ;
[0048] in, Represents the phase difference of a single cycle. It is worth noting that A valid update means that the PPS of the external input sampled by the internal global clock is high and the output of the carry chain is not all 1. Each time the single-cycle phase difference is effectively updated, the single-cycle valid update flag is set to 1.
[0049] Regarding cycle ambiguity detection, in one embodiment, when the single-cycle valid update flag is set to 1, the cycle detection results include: normal cycle, delayed cycle, and advanced cycle.
[0050] In this embodiment, the FPGA internal global clock counting method is used to count the number of internal global clock pulses required for each single-cycle phase difference to effectively update the rising edge of the marker, thereby solving the period ambiguity problem of the external input PPS reference signal.
[0051] In another embodiment, when the cycle detection result is that the cycle is normal, the cycle ambiguity is 0; based on the cycle count value, the frequency of the global clock, the period of the global clock, and the single-cycle phase difference, the cycle detection is performed to obtain a phase difference of:
[0052] ;
[0053] in, Indicates the phase difference.
[0054] In one embodiment, when the cycle detection result is cycle hysteresis, the cycle ambiguity is calculated based on the cycle count value and the frequency of the global clock. Based on the cycle ambiguity, the period of the global clock, and the single-cycle phase difference, the cycle detection is performed to obtain a phase difference of:
[0055] ;
[0056] Among them, the periodic ambiguity is , Indicates the phase difference.
[0057] In one embodiment, when the cycle detection result is a cycle advance, the cycle ambiguity is calculated based on the cycle count value and the frequency of the global clock. Based on the cycle ambiguity, the cycle of the global clock, and the single-cycle phase difference, the cycle detection is performed to obtain a phase difference of:
[0058] ;
[0059] Among them, the periodic ambiguity is , Indicates the phase difference.
[0060] In another embodiment, the current cycle ambiguity and cycle ambiguity flag are recorded; when the cycle is normal, the cycle ambiguity flag is updated to 0; when the cycle is delayed, the cycle ambiguity flag is updated to 1; when the cycle is advanced, the cycle ambiguity flag is updated to 2.
[0061] In another embodiment, the cycle count value is equal to the number of internal global clock pulses required for each single-cycle phase difference to effectively update the rising edge of the flag.
[0062] The following is a specific example of the above process. Figure 3 The specific steps are as follows:
[0063] S1, FPGA model xc7z045fg900-2, externally inputs PPS signal and global 60MHz clock signal, and executes step (2);
[0064] S2, the external input PPS signal enters the carry4 carry chain and executes step (3);
[0065] S3, if the global clock rising edge has not arrived, continue waiting; if the clock rising edge arrives, execute step (4);
[0066] S4, latch the carry chain output of carry4 using a two-stage register and execute step (5);
[0067] S5, convert the output of the carry4 carry chain of the FPGA into a binary number and execute step (6);
[0068] S6, determine whether the single-cycle phase difference is validly updated. If the external PPS signal sampled by the rising edge of the global clock is high and the output of the carry4 carry chain is not all 1, it means that the current single-cycle phase difference value is valid, and execute step (7); if the current single-cycle phase difference value is invalid, execute step (8);
[0069] S7, update the number of delay units for a single cycle to And the single cycle valid update flag is set to 1. According to the experimental calibration, the minimum delay unit time interval of carry4 inside the FPGA model xc7z045fg900-2 is .
[0070] ;
[0071] Where is Single cycle phase difference.
[0072] S8, set the single cycle valid flag to 0, and execute step (9);
[0073] S9, if the rising edge of the global clock arrives, execute step (10);
[0074] S10, the cycle count value is incremented by 1, and step (11) is executed;
[0075] S11, determine whether the single-cycle valid update flag is 1. If the single-cycle valid update flag is not 1, return to step (9); if the single-cycle valid update flag is 1, execute step (12);
[0076] S12, the cycle count value is cleared and step (13) is executed;
[0077] S13, perform period ambiguity detection. The period ambiguity detection uses the FPGA internal global clock counting method to count the number of internal global clock pulses required for each single-cycle phase difference to effectively update the rising edge of the mark, thereby solving the period ambiguity problem of the external input PPS reference signal.
[0078] Frequency of the global clock inside the FPGA The global clock cycle is 60MHz. is 16.7ns, and the cycle count value is They are 60000000, 59999999 and 60000003 respectively. The total phase difference is Indicates that when the single-cycle phase difference valid update flag appears a rising edge, the internal global clock pulse count begins and the counting stops when the next valid update flag appears a rising edge. The results of the cycle detection have the following three situations:
[0079] ① When When the cycle is normal: the cycle ambiguity is 0, the cycle ambiguity flag is set to 1, then the total phase difference It can be expressed as
[0080] ;
[0081] ②When When the periodic lag is: the periodic ambiguity is 3, the periodic ambiguity flag is set to 1, then the total phase difference It can be expressed as
[0082] ;
[0083] ③When When the cycle advances: the cycle ambiguity is 1, the cycle ambiguity flag is set to 2, then the total phase difference It can be expressed as
[0084] ;
[0085] Where the global clock frequency , the global clock cycle is used , cycle count value , the total phase difference , Single cycle phase difference.
[0086] After the periodic ambiguity detection is completed, execute step (14);
[0087] S14, update the cyclic ambiguity and the cyclic ambiguity flag, and return to step (1).
[0088] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0089] In one embodiment, a high-precision PPS phase following circuit based on an FPGA carry chain is provided. The circuit is composed of a logic circuit; the logic circuit includes: a carry4 carry chain module, a register, and a clock management module. When the logic circuit is running, it executes the above-mentioned high-precision PPS phase following method based on an FPGA carry chain.
[0090] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0091] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0092] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.
Claims
1. A high-precision PPS phase following method based on FPGA carry chain, It is characterized in that The method comprises: Receive an external PPS signal and input the external PPS signal into the carry4 carry chain inside the FPGA; When the rising edge of the global clock arrives, the carry4 carry chain output is latched using a two-stage register and the carry4 carry chain output is converted into a binary number; When the carry4 carry chain output is not all 1s, the single-cycle phase difference is calculated, and the single-cycle valid update flag is set to 1; When the carry4 carry chain outputs are all 1, the single-cycle valid update flag is set to 0, and the cycle count value at the current moment is recorded by continuously counting the rising edge of the global clock until the single-cycle valid update flag is 1; According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single cycle phase difference, cycle detection is performed to obtain the phase difference, and high-precision PPS phase following is performed according to the phase difference; the carry4 carry chain is formed by cascading multiple carry4 carry units; the number of cascades of the carry4 carry chain is determined according to the size of the cycle of the global clock; the maximum cascade height of the carry4 carry chain is determined by the height limit of the FPGA chip column; When the carry4 carry chain output is not all 1s, the current single cycle phase difference is calculated, including: When the carry4 carry chain output is not all 1, it indicates that the current single-cycle phase difference value is valid; According to the binary number, determine the number of minimum delay units of the carry4 carry unit , get the minimum delay unit time interval of the carry4 unit of the FPGA as ; According to the quantity and the time interval is , calculate the single cycle phase difference as: in, Represents the single cycle phase difference; When the cycle detection result is cycle hysteresis; According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single cycle phase difference, including: Calculating a cycle ambiguity according to the cycle count value and the frequency of the global clock; According to the cycle ambiguity, the cycle of the global clock and the single cycle phase difference, the cycle detection is performed to obtain the phase difference: The periodic ambiguity is , represents the phase difference, N Indicates the cycle count value, represents the global clock period, Indicates the frequency of the global clock inside the FPGA; When the cycle detection result is that the cycle is ahead of schedule; According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single cycle phase difference, including: Calculating a cycle ambiguity according to the cycle count value and the frequency of the global clock; According to the cycle ambiguity, the cycle of the global clock and the single cycle phase difference, the cycle detection is performed to obtain the phase difference: The periodic ambiguity is , Indicates the phase difference.
2. The method according to claim 1, It is characterized in that When the single-cycle valid update flag is 1, the cycle detection results include: normal cycle, delayed cycle, and advanced cycle.
3. The method according to claim 2, It is characterized in that When the cycle detection result is that the cycle is normal, the cycle ambiguity is 0; According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single cycle phase difference, cycle detection is performed to obtain the phase difference, including: According to the cycle count value, the frequency of the global clock, the cycle of the global clock and the single cycle phase difference, the cycle detection is performed to obtain the phase difference: in, Indicates the phase difference.
4. The method according to claim 3, It is characterized in that The method further comprises: Record the current cycle ambiguity and cycle ambiguity flag; when the cycle is normal, the cycle ambiguity flag is updated to 0; when the cycle is lagging, the cycle ambiguity flag is updated to 1, and when the cycle is ahead, the cycle ambiguity flag is updated to 2.
5. The method according to claim 2 or 3, It is characterized in that The cycle count value is equal to the number of internal global clock pulses required for each single-cycle phase difference to effectively update the rising edge of the mark.