Data processing method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a data processing method, device, electronic device and readable storage medium, the method comprising: reading an operand to be processed from a data buffer; performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result; writing the operation result back to the data buffer according to the storage mode for reading by the node where the cache or memory is located. The embodiment of the present invention ensures the consistency and integrity of data through atomic operation units, without large-scale modification or upgrading of the existing system, reducing the integration cost and the design complexity of the on-chip network, and improving the compatibility of the on-chip network with different processor architectures and application scenarios.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a data processing method, device, electronic device and readable storage medium. Background Art

[0002] As computing demands continue to grow, multi-core processors are becoming more and more popular because they can provide higher computing power and better energy efficiency. However, a key challenge in multi-core processor design is how to maintain data consistency and synchronization between multiple processor cores. In a multi-core system, each core may have its own cache, which needs to be consistent with the data in the main memory to avoid data inconsistency issues.

[0003] In order to achieve memory data consistency more efficiently, most modern instruction set architectures or coherent interconnect protocols include atomic memory operations. Atomic operations are special operations that ensure that in a multi-core environment, when one core is accessing memory, other cores cannot access the memory location at the same time. This operation is critical to maintaining data integrity and system stability.

[0004] Nevertheless, some existing on-chip network implementations do not support atomic operations, which limits their use in applications that require high data consistency. On the other hand, those on-chip networks that support atomic operations have problems such as overly complex design, high power consumption, and large area. These problems not only increase the design and manufacturing costs of the processor, but also affect the performance and energy efficiency of the processor. Summary of the invention

[0005] The embodiments of the present invention provide a data processing method, device, electronic device and readable storage medium, which can solve the problems of complex design and high power consumption of on-chip networks supporting atomic operations in related technologies.

[0006] On the one hand, an embodiment of the present invention discloses a data processing method, which is applied to a network on chip, wherein the network on chip integrates a processor, a cache, a memory, and an atomic operation unit; the atomic operation unit is placed in a node where the cache or memory of the network on chip is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located; the method comprises:

[0007] Reading a pending operation number from the data buffer;

[0008] According to the storage mode of the operand to be processed, a logical operation is performed on the operand to be processed to obtain an operation result;

[0009] The operation result is written back to the data buffer according to the storage mode, so as to be read by the node where the cache or memory is located.

[0010] Optionally, the operands to be processed include a first operand and a second operand; the logical operation includes an addition operation;

[0011] The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes:

[0012] When the storage mode is the little-endian mode, the first operand and the second operand are added byte by byte, and the bits are carried from the low address bit byte to the high address bit byte in sequence to obtain the operation result;

[0013] When the storage mode is the big-endian mode, the first operand and the second operand are added byte by byte, and carry is performed from the high address bit byte to the low address bit byte in sequence to obtain the operation result.

[0014] Optionally, the operands to be processed include a third operand and a fourth operand; the logical operation includes a numerical comparison operation;

[0015] The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes:

[0016] Negate the third operand to obtain a first parameter;

[0017] adding the first parameter and the fourth operand according to the storage mode to obtain a first result;

[0018] The magnitude relationship between the third operand and the fourth operand is determined according to the sign bit of the first result.

[0019] Optionally, the atomic operation unit includes a data input logic, a first register, an operation unit, a second register and a data output logic; the first register is arranged between the data input logic and the operation unit, and the second register is arranged between the operation unit and the data output logic;

[0020] The step of reading the operand to be processed from the data buffer comprises:

[0021] The data input logic reads a group of operands to be processed from the data buffer, writes the operands to be processed into the first register, and then continues to read the next group of operands to be processed;

[0022] The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes:

[0023] The operation unit reads the operand to be processed from the first register, and performs a logic operation on the operand to be processed according to a storage mode of the operand to be processed to obtain an operation result;

[0024] After the operation unit writes the operation result into the second register, it continues to process the next group of pending operands;

[0025] Writing the operation result back to the data buffer according to the storage mode for reading by the node where the cache or memory is located includes:

[0026] The data output logic reads the operation result from the second register and writes the operation result back to the data buffer.

[0027] Optionally, the atomic operation unit is used to perform at least one of the following atomic operations: an atomic write operation, an atomic read operation, an atomic exchange operation, and an atomic comparison operation.

[0028] On the other hand, an embodiment of the present invention discloses a data processing device, which is applied to a network on chip, wherein the network on chip integrates a processor, a cache, a memory and an atomic operation unit; the atomic operation unit is placed in a node where the cache or memory of the network on chip is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located; the device comprises:

[0029] A reading module, used for reading the operands to be processed from the data buffer;

[0030] An operation module, used for performing a logic operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result;

[0031] A write-back module is used to write the operation result back to the data buffer according to the storage mode, so as to be read by the node where the cache or memory is located.

[0032] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned data processing method.

[0033] An embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned data processing method.

[0034] The embodiments of the present invention include the following advantages:

[0035] The embodiment of the present invention provides a data processing method, in which an atomic operation unit is integrated in the on-chip network, and the atomic operation unit is used to realize the logical operation of the operand, so that the on-chip network can adapt to various data consistency protocols and synchronization mechanisms more flexibly, whether in a traditional single-core processor or in a modern multi-core, multi-threaded processor system, the consistency and integrity of the data can be ensured by the atomic operation unit, without large-scale modification or upgrading of the existing system, reducing the integration cost and the design complexity of the on-chip network, and improving the compatibility of the on-chip network with different processor architectures and application scenarios. In addition, the present invention places the atomic operation unit in the node where the cache or memory of the on-chip network is located, and the atomic operation unit directly reuses the data buffer of the node where the cache or memory is located, so that the atomic operation unit is tightly integrated with the cache or memory in the on-chip network, realizing efficient utilization of data buffering, reducing the occupied area of ​​silicon wafers, and reducing production costs, so that the atomic operation unit can be widely used in chip designs of various sizes. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0037] Figure 1 is a flow chart of steps of an embodiment of a data processing method of the present invention;

[0038] Figure 2 is a schematic diagram of the architecture of a network on chip of the present invention;

[0039] Figure 3 It is a schematic diagram of the architecture of an atomic operation unit of the present invention;

[0040] Figure 4 is a structural block diagram of an embodiment of a data processing device of the present invention;

[0041] Figure 5 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0044] Method Embodiment

[0045] First, some professional terms that may be involved in the present invention are explained:

[0046] On-chip network: A network topology implemented inside a chip, used to connect various functional modules or processing units inside the chip to achieve data transmission and communication.

[0047] Atomic operation: During the execution of an operation involving multiple data values, the loading of the original value, the execution of the operation, and the storage of the updated value are completed atomically. That is, during the entire operation, no other device can access the memory location.

[0048] Tight coupling: refers to a relationship in which components in a system are highly interdependent and interact closely with each other. In a tightly coupled system, the communication and data transfer between two components are frequent, and the modifications and impacts between them are relatively direct.

[0049] Cache: A high-speed memory used to temporarily store data, located between the main memory and the CPU. Its purpose is to improve system performance by providing fast access when the CPU needs data, thereby reducing the number of accesses to the slow main memory.

[0050] Buffer: An area used to temporarily store data, generally used to solve problems such as speed mismatch in data transmission.

[0051] Big endian: When storing a multi-byte value, the most significant byte is stored at the lowest memory address, and the remaining bytes are stored in descending order.

[0052] Little endian: When storing a multi-byte value, the least significant byte is stored at the lowest memory address, and the remaining bytes are stored in increasing order.

[0053] Multi-core processor: Two or more independent processing cores (CPU cores) are integrated on a processor chip. Each core can independently execute instructions, process tasks and execute threads.

[0054] Multithreaded processor: Also known as a hyper-threaded processor, it enables a single physical processor core to process two or more threads simultaneously by implementing additional execution resources and control logic within the core.

[0055] Coherence Base Node (HN-F): Located in the interconnect network, it receives protocol transactions from requesting nodes. It contains a coherence point that manages coherence by listening to the required coherence requesting nodes (RN-Fs), aggregating the listener responses, and sending a single response to the requesting requesting nodes. It also acts as a serialization point and is responsible for managing the order between memory requests.

[0056] Consistency master node (RN-F): Also known as the request node, it generates request transactions (including read transactions, write transactions, and atomic transactions) and sends them to the interconnection network. It contains hardware consistency cache and supports listening transactions.

[0057] Slave Node (SN): Receives requests from the master node, performs required operations, and returns responses. Can be used to connect peripherals or general memory.

[0058] Reference Figure 1 , shows a flow chart of steps of a data processing method embodiment of the present invention, the method may specifically include the following steps:

[0059] Step 101, read the operand to be processed from the data buffer;

[0060] Step 102: Perform a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result;

[0061] Step 103: Write the operation result back to the data buffer according to the storage mode, so that the node where the cache or memory is located can read it.

[0062] The data processing method provided in the embodiment of the present invention can be applied to a network on chip. Figure 2 , shows a schematic diagram of the architecture of a network on chip provided by an embodiment of the present invention. Figure 2As shown, the on-chip network integrates a processor, a cache, a memory and an atomic operation unit. The atomic operation unit is placed in the node where the cache or memory of the on-chip network is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located. In other words, the atomic operation unit and the node where the cache or memory is located share the same data buffer. Therefore, when the atomic operation unit is integrated in the on-chip network, the existing data buffer resources can be directly reused, and there is no need to design an additional storage unit for the atomic operation unit, which reduces the area occupied by the silicon chip and reduces the design cost and resource consumption of the on-chip network.

[0063] It should be noted that the cache and memory are placed in the node where the cache or memory is located. In an on-chip network, there may be multiple processors (cores) and multiple nodes where the cache or memory is located. The node where the cache or memory is located is connected to the processor through an interconnection module.

[0064] Optionally, the atomic operation unit is used to perform at least one of the following atomic operations: an atomic write operation, an atomic read operation, an atomic exchange operation, and an atomic comparison operation.

[0065] Taking the design and implementation of atomic operation units based on the AMBA CHI protocol as an example, the CHI protocol includes four types of atomic operations: AtomicStore (atomic write operation), AtomicLoad (atomic read operation), AtomicSwap (atomic swap operation) and AtomicCompare (atomic comparison operation). Among them, AtomicStore and AtomicLoad respectively include 8 operations: ADD (addition), CLR (clear), EOR (exclusive OR), SET (set), SMAX (return maximum value), SMIN (return minimum value), UMAX (maximum value of unsigned number), UMIN (minimum value of unsigned number), namely addition, clear, exclusive OR, set, size comparison. AtomicSwap means exchanging two operands, while AtomicCompare decides whether to exchange operands based on the size of the operands.

[0066] Atomic operations are special operations that ensure that in a multi-core environment, when one core is accessing memory, other cores cannot access that memory location at the same time. This operation maintains data integrity and system stability of the on-chip network.

[0067] For example, the on-chip network in the embodiment of the present invention may be an on-chip network implemented based on a consistent interconnection protocol such as AMBA CHI. AMBA CHI is a high-performance consistent interconnection protocol that allows efficient data exchange between different nodes in the on-chip network while maintaining data consistency.

[0068] In an embodiment of the present invention, the atomic operation unit is placed in a consistency base node (HN-F), a consistency master node (RN-F) or a memory slave node (SN) of the on-chip network. Among them, the consistency base node and the master node are nodes where the cache is located, including a high-speed cache; the memory slave node is connected to the memory system. A buffer module for temporarily storing data is generally configured outside the cache or memory system to speed up the reading and writing of data. In an embodiment of the present invention, the atomic operation unit is tightly coupled with the data buffer of the cache or memory. The atomic operation unit can directly read the operands to be processed from the data buffer, and perform logical operations according to the storage mode of the operands to be processed. Then, the operation results are written back to the data buffer for reading by the node where the cache or memory is located, thereby reducing the data transmission time between the processor core, cache and memory, optimizing the data transmission path, and improving the overall performance of the on-chip network.

[0069] Furthermore, in an embodiment of the present invention, the data cache can also be implemented by a register group. The characteristic of the register group is that the data can be directly read from the output port after entering, so it can directly enter the input logic in the current clock cycle. If the register group is used as a data buffer, the process of the atomic operation unit reading the operand to be processed from the data buffer for calculation can be completed within one to two clock cycles. For example, after the number "1234567890" is stored in the register, the entire process of generating the atomic operand 000567 after being processed by the atomic operation unit can be completed within one clock cycle. The data buffer tightly coupled with the atomic operation unit is realized by the register group, which reduces the delay of the atomic operation and improves the data processing efficiency of the on-chip network.

[0070] It is understandable that the design complexity of the on-chip network mainly comes from the need to implement complex control logic and synchronization mechanisms in the on-chip network to ensure the correct execution of atomic operations. The power consumption problem is directly related to the complexity of these control logics, because more complex logic usually means higher energy consumption. The area problem refers to the fact that the hardware that implements these functions occupies a large amount of chip space, which limits the integration and scalability of the processor.

[0071] The network on chip of the present invention significantly improves compatibility with different processor architectures and application scenarios by integrating atomic operations. This design allows the network on chip to adapt to various data consistency protocols and synchronization mechanisms more flexibly. Whether in traditional single-core processors or in modern multi-core, multi-threaded processor systems, the consistency and integrity of data can be ensured through atomic operation units, without the need for large-scale modification or upgrade of existing systems, reducing integration costs and design complexity of the network on chip.

[0072] Furthermore, the atomic operation unit in the present invention is tightly integrated with the cache or memory in the on-chip network, achieving efficient use of data buffering, reducing the occupied area of ​​the silicon wafer, and reducing production costs, so that the atomic operation unit can be widely used in chip designs of various sizes.

[0073] The storage mode of operands can be divided into big-endian mode and little-endian mode. Among them, the big-endian mode means that when storing a multi-byte value, the most significant byte is stored at the lowest memory address, and the remaining bytes are stored in descending order. The little-endian mode means that when storing a multi-byte value, the least significant byte is stored at the lowest memory address, and the remaining bytes are stored in ascending order.

[0074] It is understandable that different storage modes will result in different data reading and carry methods, so when performing logical operations on processor operands, corresponding operations can be performed according to the storage mode.

[0075] The atomic operation unit in the present invention can seamlessly support operands in both big-endian and little-endian storage modes. This flexibility enhances the compatibility of the on-chip network, enabling it to adapt to different data processing requirements and software ecosystems.

[0076] Optionally, the operand to be processed includes a first operand and a second operand; the logical operation includes an addition operation; and performing a logical operation on the operand to be processed according to a storage mode of the operand to be processed to obtain an operation result includes:

[0077] Step S11, when the storage mode is the little-endian mode, the first operand and the second operand are added byte by byte, and the bits are carried from the low address bit byte to the high address bit byte in sequence to obtain the operation result;

[0078] Step S12: When the storage mode is the big-endian mode, the first operand and the second operand are added byte by byte, and the bytes are carried from the high-address byte to the low-address byte in sequence to obtain a calculation result.

[0079] For example, when performing an addition operation, for operands stored in little-endian mode, it is necessary to carry from the low-address byte to the high-address byte in sequence when adding; for operands stored in big-endian mode, it is necessary to carry from the high-address byte to the low-address byte in sequence when adding.

[0080] For example, assuming that one bit of the operand corresponds to one byte, for the two numbers "4321" and "6789", if they are stored in little-endian mode, the two numbers will be "4321" and "6780" when stored. Then, when adding them, just carry from the low bit to the high bit, and the final result will be "11101". However, if they are stored in big-endian mode, the two numbers will be stored as "1234" and "0876". If they are still added from the high bit to the low bit, the result will be "2110", which is obviously wrong, because the addition of big-endian numbers requires carrying from the high bit to the low bit to get the correct result "10111", which is the big-endian storage method of "11101".

[0081] It should be noted that when the final calculation result is written back to the data buffer, it also needs to be stored according to the storage mode of the operand so that the cache node and the memory node can correctly read the calculation result.

[0082] Optionally, the operand to be processed includes a third operand and a fourth operand; the logical operation includes a numerical comparison operation; and performing a logical operation on the operand to be processed according to a storage mode of the operand to be processed to obtain an operation result includes:

[0083] Step S21, negate the third operand to obtain a first parameter;

[0084] Step S22, adding the first parameter and the fourth operand according to the storage mode to obtain a first result;

[0085] Step S23: Determine the size relationship between the third operand and the fourth operand according to the sign bit of the first result.

[0086] In an embodiment of the present invention, when the atomic operation unit processes the size comparison of operands, it can be implemented by reusing the adder in the on-chip network, avoiding additional hardware overhead. While retaining the functional integrity of the atomic operation unit, it also reduces the hardware requirements for dedicated comparison logic, thereby achieving a reduction in silicon chip area while maintaining high compatibility of the on-chip network, which is beneficial to improving the overall performance of the on-chip network.

[0087] For example, for two operands that need to be compared in size, one operand can be selected to be negated and added to the other operand, and the size of the operand can be determined based on the sign bit of the result. Taking the third operand negated and then added to the fourth operand as an example, if the sign bit of the first result indicates that the first result is a negative number, it means that the third operand is greater than the fourth operand; if the sign bit of the first result indicates that the first result is a positive number, it means that the third operand is less than the fourth operand; if the first result is equal to 0, it means that the third operand is equal to the fourth operand.

[0088] It is understandable that the negation of the operand can also be achieved through an adder, that is, the adder is used as a subtractor, for example, ab=a+(-b), that is, b is negated and then added to a.

[0089] In addition, in the embodiment of the present invention, simple operations such as shift, chip selection, and negation can be performed to provide operands with controllable bit width to the atomic operation unit, and the operation results can be written back to the data buffer in a similar manner.

[0090] For example, a storage unit (cache line) can store 64 bytes of numbers, but only a part of it is used for atomic operations. Generally, the port width of the atomic operation unit is only 16 bytes, so shift and bit selection operations are required to generate operands. For example, only "456789" in the number "1234567890" participates in the atomic operation, so it needs to be selected. If only "567" is needed, it also needs to be moved to the low bit, that is, "000567". Writing the operation result back to the data buffer is the reverse operation of inputting the data into the atomic operation unit.

[0091] The atomic operation unit of the present invention realizes flexible control of the operand bit width by using simple shift and chip selection logic operations in the data input and output stages. This design not only simplifies the complexity of the logic circuit, but also reduces the number of required logic gates and wiring, effectively reducing the area occupied by the entire atomic operation unit. At the same time, the simplified logic operation also means that less power is consumed during the execution process, thereby reducing the overall power consumption of the on-chip network.

[0092] In an optional embodiment of the present invention, the atomic operation unit includes data input logic, a first register, an operation unit, a second register and data output logic; the first register is arranged between the data input logic and the operation unit, and the second register is arranged between the operation unit and the data output logic.

[0093] The step 101 of reading the operand to be processed from the data buffer includes:

[0094] Step S31, the data input logic reads a group of operands to be processed from the data buffer, writes the operands to be processed into the first register, and then continues to read the next group of operands to be processed;

[0095] Step 102, performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result, includes:

[0096] Step S32, the operation unit reads the operand to be processed from the first register, and performs a logic operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result;

[0097] Step S33, after the operation unit writes the operation result into the second register, it continues to process the next group of pending operands;

[0098] Step 103, writing the operation result back to the data buffer according to the storage mode for reading by the node where the cache or memory is located, includes:

[0099] Step S34: the data output logic reads the operation result from the second register, and writes the operation result back to the data buffer.

[0100] The atomic operation unit in the on-chip network of the present invention can adopt pipeline technology and reasonably insert registers in the atomic operation module to improve the operation frequency and sorting performance. Figure 3 , shows a schematic diagram of the architecture of an atomic operation unit provided by an embodiment of the present invention. Figure 3 As shown, the atomic operation unit includes data input logic, an operation unit and data output logic, wherein the data input logic is used to perform simple processing on the data in the data buffer and then send it to the operation unit for calculation. Exemplarily, the data input logic can perform shifting, chip selection and other processing on the data in the data buffer, and convert the data in the buffer into atomic operands that can be directly processed by the operation unit. For example, the operand "1234567890" in the data buffer is processed by the data input logic to generate the atomic operand "000567", which is sent to the operation unit for calculation. The operation unit is used to perform arithmetic and logical operations such as addition, XOR, clearing, setting, size comparison and exchange on the operands. The data output logic is used to write the operation results of the operation unit back to the data buffer for reading by the node where the cache or memory is located.

[0101] In an embodiment of the present invention, a first register is inserted between the data input logic and the operation unit, and the first register is used to temporarily store the operands processed by the data input logic. After the data input logic reads a group of operands from the data buffer, the group of operands can be temporarily stored in the first register, and the next group of operands can be read. The operation unit can directly read the operands to be processed from the first register for operation. During the calculation process of the operation unit, the data input logic can continue to read the next group of operands without waiting for the operation unit to process the current operands before reading the next group of operands.

[0102] Similarly, a second register is inserted between the operation unit and the data output logic, and the second register is used to temporarily store the operation result of the operation unit. When the operation unit processes a group of operands, the operation result can be temporarily stored in the second register for the data output logic to read. When the data output logic reads the operation result from the second register and writes it back to the data buffer, the operation unit can continue to process the next group of operands.

[0103] For example, data enters the operation unit from the data input logic, is calculated, and then goes out from the data output logic. The whole process consumes 3ns (one clock cycle is 3ns). Assuming that the three processes of data input, calculation, and output each take 1ns, the two components of the operation unit and data output logic are not working during the first 1ns of the data input logic. Similarly, when the data is calculated in the operation unit (the second 1ns), the other two input and output components are also idle, which wastes hardware resources. Inserting registers between these three components to temporarily store various sub-results can reduce the clock cycle to 1ns, that is, when the operation unit is processing the previous operand, the data input logic has already started to process the next operand, which is equivalent to allowing the three components to process three groups of operands simultaneously and in parallel. A 1ns clock cycle corresponds to a frequency of 1GHz, which is 3 times the original frequency before the register is inserted.

[0104] The embodiment of the present invention significantly improves the operating frequency and overall performance of the atomic operation unit by reasonably inserting registers in the atomic operation unit, optimizes the data processing flow, and enables the next operation to be processed while one operation is completed, effectively improving the throughput and response speed of the atomic operation unit. At the same time, pipelining also balances the load of each processing stage, avoids performance bottlenecks, and makes more reasonable use of resources.

[0105] In summary, the embodiment of the present invention provides a data processing method, in which an atomic operation unit is integrated in the on-chip network, and the atomic operation unit is used to realize the logical operation of the operand, so that the on-chip network can adapt to various data consistency protocols and synchronization mechanisms more flexibly and efficiently, whether in a traditional single-core processor or in a modern multi-core, multi-threaded processor system, the consistency and integrity of the data can be ensured by the atomic operation unit, without large-scale modification or upgrading of the existing system, reducing the integration cost and the design complexity of the on-chip network, and improving the compatibility of the on-chip network with different processor architectures and application scenarios. In addition, the present invention places the atomic operation unit in the node where the cache or memory of the on-chip network is located, and the atomic operation unit directly reuses the data buffer of the node where the cache or memory is located, so that the atomic operation unit is tightly integrated with the cache or memory in the on-chip network, realizing efficient utilization of data buffering, reducing the occupied area of ​​silicon wafers, and reducing production costs, so that the atomic operation unit can be widely used in chip designs of various sizes.

[0106] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0107] Device Embodiment

[0108] Reference Figure 4 , shows a structural block diagram of a data processing device of the present invention, which is applied to a network on chip, wherein the network on chip integrates a processor, a cache, a memory and an atomic operation unit; the atomic operation unit is placed in a node where the cache or memory of the network on chip is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located; the device may specifically include:

[0109] A reading module 401 is used to read the operands to be processed from the data buffer;

[0110] The operation module 402 is used to perform a logic operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result;

[0111] The write-back module 403 is used to write the operation result back to the data buffer according to the storage mode, so as to be read by the node where the cache or memory is located.

[0112] Optionally, the operands to be processed include a first operand and a second operand; the logical operation includes an addition operation;

[0113] The operation module comprises:

[0114] A first adding module, configured to add the first operand and the second operand byte by byte when the storage mode is a little-endian mode, and carry bits from a low address byte to a high address byte in sequence to obtain a calculation result;

[0115] The second addition module is used for adding the first operand and the second operand byte by byte when the storage mode is the big-endian mode, and carrying from the high-address byte to the low-address byte in sequence to obtain a calculation result.

[0116] Optionally, the operands to be processed include a third operand and a fourth operand; the logical operation includes a numerical comparison operation;

[0117] The operation module comprises:

[0118] A negation submodule, used for negating the third operand to obtain a first parameter;

[0119] an operation submodule, configured to add the first parameter and the fourth operand according to the storage mode to obtain a first result;

[0120] A determination submodule is used to determine the size relationship between the third operand and the fourth operand according to the sign bit of the first result.

[0121] Optionally, the atomic operation unit includes a data input logic, a first register, an operation unit, a second register and a data output logic; the first register is arranged between the data input logic and the operation unit, and the second register is arranged between the operation unit and the data output logic;

[0122] The data input logic is used to read a group of operands to be processed from the data buffer, write the operands to be processed into the first register, and then continue to read the next group of operands to be processed;

[0123] The computing unit is used for:

[0124] Reading the operand to be processed from the first register, and performing a logic operation on the operand to be processed according to a storage mode of the operand to be processed to obtain an operation result;

[0125] After writing the operation result into the second register, continue to process the next group of pending operands;

[0126] The data output logic is used to read the operation result from the second register and write the operation result back to the data buffer.

[0127] Optionally, the atomic operation unit is used to perform at least one of the following atomic operations: an atomic write operation, an atomic read operation, an atomic exchange operation, and an atomic comparison operation.

[0128] The embodiment of the present invention provides a data processing device, in which an atomic operation unit is integrated in the on-chip network, and the atomic operation unit is used to implement the logical operation of the operand, so that the on-chip network can adapt to various data consistency protocols and synchronization mechanisms more flexibly and efficiently. Whether in a traditional single-core processor or in a modern multi-core, multi-threaded processor system, the atomic operation unit can be used to ensure the consistency and integrity of the data, without the need for large-scale modification or upgrading of the existing system, reducing the integration cost and the design complexity of the on-chip network, and improving the compatibility of the on-chip network with different processor architectures and application scenarios. In addition, the present invention places the atomic operation unit in the node where the cache or memory of the on-chip network is located, and the atomic operation unit directly reuses the data buffer of the node where the cache or memory is located, so that the atomic operation unit is tightly integrated with the cache or memory in the on-chip network, realizing efficient use of data buffering, reducing the occupied area of ​​silicon wafers, and reducing production costs, so that the atomic operation unit can be widely used in chip designs of various sizes.

[0129] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0132] Reference Figure 5 , is a structural block diagram of an electronic device for data processing provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the data processing method of the aforementioned embodiment.

[0133] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0134] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0135] The memory can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0136] The embodiment of the present invention also provides a non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is able to execute Figure 1 The data processing method shown.

[0137] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0138] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0139] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0142] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0143] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0144] The data processing method, device, electronic device and readable storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data processing method, characterized in that: Applied to a network on chip, the network on chip integrates a processor, a cache, a memory and an atomic operation unit; the atomic operation unit is placed in a node where the cache or memory of the network on chip is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located; The atomic operation unit includes a data input logic, a first register, an operation unit, a second register and a data output logic; the first register is arranged between the data input logic and the operation unit, and the second register is arranged between the operation unit and the data output logic; The method comprises: The data input logic reads the operand to be processed from the data buffer; The operation unit performs a logic operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result; The data output logic writes the operation result back to the data buffer according to the storage mode, so as to be read by the node where the cache or memory is located.

2. The method according to claim 1, characterized in that The operands to be processed include a first operand and a second operand; the logic operation includes an addition operation; The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes: When the storage mode is the little-endian mode, the first operand and the second operand are added byte by byte, and the bits are carried from the low address bit byte to the high address bit byte in sequence to obtain the operation result; When the storage mode is the big-endian mode, the first operand and the second operand are added byte by byte, and carry is performed from the high address bit byte to the low address bit byte in sequence to obtain the operation result.

3. The method according to claim 1, characterized in that The operands to be processed include a third operand and a fourth operand; the logical operation includes a numerical comparison operation; The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes: Negate the third operand to obtain a first parameter; adding the first parameter and the fourth operand according to the storage mode to obtain a first result; The magnitude relationship between the third operand and the fourth operand is determined according to the sign bit of the first result.

4. The method according to claim 1, characterized in that: The step of reading the operand to be processed from the data buffer comprises: The data input logic reads a group of operands to be processed from the data buffer, writes the operands to be processed into the first register, and then continues to read the next group of operands to be processed; The step of performing a logical operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result includes: The operation unit reads the operand to be processed from the first register, and performs a logic operation on the operand to be processed according to a storage mode of the operand to be processed to obtain an operation result; After the operation unit writes the operation result into the second register, it continues to process the next group of pending operands; Writing the operation result back to the data buffer according to the storage mode for reading by the node where the cache or memory is located includes: The data output logic reads the operation result from the second register and writes the operation result back to the data buffer.

5. The method according to any one of claims 1 to 4, characterized in that: The atomic operation unit is used to perform at least one of the following atomic operations: an atomic write operation, an atomic read operation, an atomic exchange operation, and an atomic comparison operation.

6. A data processing device, characterized in that: Applied to a network on chip, the network on chip integrates a processor, a cache, a memory and an atomic operation unit; the atomic operation unit is placed in a node where the cache or memory of the network on chip is located, and the atomic operation unit reuses the data buffer of the node where the cache or memory is located; The atomic operation unit includes a data input logic, a first register, an operation unit, a second register and a data output logic; the first register is arranged between the data input logic and the operation unit, and the second register is arranged between the operation unit and the data output logic; The device comprises: A reading module, used for the data input logic to read the operand to be processed from the data buffer; An operation module, used for the operation unit to perform a logic operation on the operand to be processed according to the storage mode of the operand to be processed to obtain an operation result; A write-back module is used for the data output logic to write the operation result back to the data buffer according to the storage mode, so as to be read by the node where the cache or memory is located.

7. The device according to claim 6, characterized in that The operands to be processed include a first operand and a second operand; the logic operation includes an addition operation; The operation module comprises: A first adding module, configured to add the first operand and the second operand byte by byte when the storage mode is a little-endian mode, and carry bits from a low address byte to a high address byte in sequence to obtain a calculation result; The second addition module is used for adding the first operand and the second operand byte by byte when the storage mode is the big-endian mode, and carrying from the high-address byte to the low-address byte in sequence to obtain a calculation result.

8. The device according to claim 6, characterized in that The operands to be processed include a third operand and a fourth operand; the logical operation includes a numerical comparison operation; The operation module comprises: A negation submodule, used for negating the third operand to obtain a first parameter; an operation submodule, configured to add the first parameter and the fourth operand according to the storage mode to obtain a first result; A determination submodule is used to determine the size relationship between the third operand and the fourth operand according to the sign bit of the first result.

9. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the data processing method according to any one of claims 1 to 5.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the data processing method as claimed in any one of claims 1 to 5.

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