Signal probability estimation method and device based on ANN testing and diagnosis

Abstract

The present application relates to a signal probability estimation method and device based on ANN test and diagnosis, the method comprising: using an automatic diagnostic vector generation method to generate an optimal diagnostic vector set in a circuit, wherein the diagnostic vector set includes multiple diagnostic vectors; simulating the diagnostic vectors in sequence on the circuit through a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector; for any lead, taking the average value of the test signal of the lead under different diagnostic vectors as the sample signal probability of the lead being high or low; training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include the topological structure of the circuit and the set of faults to be tested; inputting the actual fan-in features of the lead into the trained probability prediction model to obtain the actual signal probability of the lead. The present application relates to improving the efficiency of generating diagnostic vectors.

Description

Technical Field

[0001] The present application relates to the technical field of simulation and fault diagnosis, and in particular to a signal probability estimation method and device based on ANN testing and diagnosis. Background Art

[0002] In the actual chip generation process, defects are inevitable. In order to detect defects in chip manufacturing as early as possible, the Design for Testability (DFT) method has become an important process in chip design. Among them, the Automatic Test Pattern Generation (ATPG) method generates test vectors for the chip to be tested during the design phase. After the chip is manufactured, it will be loaded onto the Automatic Test Equipment (ATE). The previously generated vectors will be used on the machine to detect defects in the chip. For defective chips, these vectors will be used for further fault diagnosis processes. The test vectors generated for fault diagnosis problems are called Diagnosis Pattern Generation (DPG). Test Application Time (TAT) and Test Volume (TV) are important indicators for evaluating the quality of diagnostic vectors generated by ATPG.

[0003] Signal probability prediction is mainly aimed at the problem of test point insertion. In the existing technology, signal probability prediction is generally performed through AI (Artificial Intelligence) or COP method, and it is assumed that the signal probability of the input leads is 0.5. However, these methods do not take into account the application of signal probability prediction in diagnostic vector generation. Once signal probability prediction needs to be applied in diagnostic vector generation, the signal probability prediction needs to be processed multiple times, which will lead to low efficiency in diagnostic vector generation. Summary of the invention

[0004] The present application provides a signal probability estimation method and device based on ANN testing and diagnosis to solve the problem of low efficiency in generating diagnostic vectors.

[0005] In a first aspect, the present application provides a signal probability estimation method based on ANN testing and diagnosis, the method comprising:

[0006] An automatic diagnostic vector generation method is used to generate an optimal diagnostic vector set in a circuit, wherein the diagnostic vector set includes a plurality of diagnostic vectors;

[0007] Simulating the diagnostic vectors in sequence on the circuit through a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector;

[0008] For any lead, the average value of the test signal of the lead under different diagnostic vectors is used as the sample signal probability that the lead is at a high level or a low level;

[0009] Training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include a circuit topology and a set of faults to be tested;

[0010] The actual fan-in characteristics of the lead are input into a trained probability prediction model to obtain the actual signal probability of the lead, and the probability prediction model is an artificial neural network.

[0011] Optionally, the formula for calculating the sample signal probability is:

[0012] , where p is the sample signal probability, j is the jth diagnostic vector, is the simulation test set, sim is the result of logic simulation, and i is the i-th lead.

[0013] Optionally, the sample fan-in feature or the actual fan-in feature includes multiple sub-features, and the sub-features are: the type of logic gate, the minimum number of input signals for the lead to be controlled to a low level, the minimum number of input signals for the lead to be controlled to a high level, the minimum number of input signals when the lead fails at the least, whether reconvergence occurs, whether there is an SA0 fault, and whether there is an SA1 fault, wherein the logic gate uses the lead for signal input.

[0014] Optionally, after obtaining the actual signal probability that the lead is at a high level or a low level, the method further includes:

[0015] In ATPG decision making, a score of each alternative decision is calculated by the actual signal probability;

[0016] The decision corresponding to the highest score is selected as the decision to be executed.

[0017] Optionally, training a probability prediction model according to preset sample fan-in characteristics and sample signal probability includes:

[0018] Obtain multiple sub-sample features in the sample fan-in feature of the lead;

[0019] Convert each of the sub-sample features into a sub-sample vector;

[0020] splicing the sub-sample vectors to obtain a sample feature vector;

[0021] A probability prediction model is trained according to the sample feature vector and the sample signal probability to obtain a trained probability prediction model.

[0022] Optionally, training a probability prediction model according to the sample feature vector and the sample signal probability includes:

[0023] Inputting the sample feature vector into an initial prediction model to obtain a test signal probability output by the initial prediction model;

[0024] When the test signal probability is inconsistent with the sample signal probability, the model parameters of the initial prediction model are adjusted to obtain a trained probability prediction model, wherein the test signal probability output by the trained probability prediction model is consistent with the sample signal probability.

[0025] Optionally, inputting the actual fan-in feature of the lead into the trained probability prediction model includes:

[0026] Get multiple sub-actual features of the lead;

[0027] converting each of the sub-actual features into a sub-actual vector;

[0028] splicing the sub-actual vectors to obtain an actual feature vector;

[0029] The actual feature vector of the lead is input into the trained probability prediction model.

[0030] In a second aspect, the present application provides a signal probability estimation device based on ANN testing and diagnosis, the device comprising:

[0031] A generating module, used for generating an optimal diagnostic vector set in a circuit by using an automatic diagnostic vector generating method, wherein the diagnostic vector set includes a plurality of diagnostic vectors;

[0032] A simulation module, used to simulate the diagnostic vectors in sequence on the circuit through a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector;

[0033] A calculation module, for taking, for any lead, an average value of the test signal of the lead under different diagnostic vectors as the sample signal probability that the lead is at a high level or a low level;

[0034] A training module, used for training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include a circuit topology and a set of faults to be tested, and the probability prediction model is an artificial neural network;

[0035] The input-output module is used to input the actual fan-in characteristics of the lead into the trained probability prediction model to obtain the actual signal probability of the lead.

[0036] In a third aspect, the present application provides an electronic device comprising: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor connected to the at least one bus; and at least one memory connected to the at least one bus.

[0037] In a fourth aspect, the present application further provides a computer storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the signal probability estimation method based on ANN testing and diagnosis as described in any one of the above items of the present application.

[0038] The above technical solution provided by the embodiment of the present application has the following advantages over the prior art: the sample signal probability is obtained by simulating each lead under the diagnostic vector set, and then the probability prediction model is trained based on the circuit topology, the set of faults to be tested and the sample signal probability, so as to generate the signal probability of the lead based on the trained probability prediction model. The present application generates the signal probability of the lead based on the diagnostic vector set, and only requires simple model training to output accurate signal probability, thereby reducing the running time of ATPG in the circuit and improving the efficiency of diagnostic vector generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0042] Figure 1 A flow chart of a method for signal probability estimation based on ANN testing and diagnosis provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of signal probability provided in an embodiment of the present application;

[0044] Figure 3A schematic diagram of a circuit for calculating input feature dimension provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of a signal probability estimation process based on ANN testing and diagnosis provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a signal probability estimation device based on ANN testing and diagnosis provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0049] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0050] This application provides a signal probability estimation method based on ANN testing and diagnosis, which is applied to a server, such as Figure 1 As shown, the method includes:

[0051] Step 101: Generate an optimal diagnostic vector set in a circuit using an automatic diagnostic vector generation method, wherein the diagnostic vector set includes a plurality of diagnostic vectors.

[0052] Automatic diagnostic vector generation is a process in which diagnostic vectors used in semiconductor electrical device testing are automatically generated by a program. The server uses an ATPG tool to generate an optimal diagnostic vector set T, which includes multiple diagnostic vectors.

[0053] Step 102: Use a logic simulation tool to simulate diagnostic vectors in sequence on the circuit to obtain a set of simulation results.

[0054] The simulation result set is the test signal of each lead under each diagnostic vector.

[0055] The server uses a logic simulation tool to simulate the diagnostic vectors in the diagnostic vector set in sequence on the circuit to obtain a simulation result set sim, which includes a simulation test signal of each lead under each diagnostic vector. The leads mentioned in the embodiment of the present application refer to the input leads of the logic gate. The order of the simulated diagnostic vectors can be in accordance with the order of the diagnostic vectors, in a random order, or in other orders.

[0056] Step 103: For any lead, the average value of the test signal of the lead under different diagnostic vectors is used as the sample signal probability that the lead is at a high level or a low level.

[0057] The same lead has corresponding test signals under different diagnostic vectors. The average of the multiple test signals is taken to obtain the sample signal probability of the lead under the diagnostic vector set. The sample signal probability refers to the probability that the lead is high or low. The sample signal probability of each lead is obtained by the above method.

[0058] Among them, the formula for calculating the probability of sample signal is:

[0059] , where p is the sample signal probability, j is the jth diagnostic vector, is the simulation test set, sim is the result of logic simulation, and i is the i-th lead.

[0060] The meaning of this formula is that, starting from the first diagnostic vector j, the logic simulation result of the lead under each diagnostic vector is calculated, and then the average of multiple logic simulation results is taken to obtain the sample signal probability p of the lead, and the above calculation is performed for each lead i.

[0061] Figure 2 is a schematic diagram of signal probability, from Figure 2 As can be seen in the figure, ATPG generates a diagnostic vector set {001, 100, 011}, and the value of each logic gate is obtained through logic simulation, so that the signal probability of each logic gate can be calculated using the above formula. In the figure, sim represents the logic simulation result of the lead under three diagnostic vectors, and sig_pr represents the average signal probability.

[0062] Step 104: training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include the topological structure of the circuit and the set of faults to be tested.

[0063] The server uses the sample signal probability of the lead as the training label of the sample fan-in feature of the lead, and then uses the sample fan-in feature and the sample signal probability as a training sample, obtains a training sample set through the training samples of multiple leads, and then trains the probability prediction model through the training sample set. Among them, the probability prediction model is an artificial neural network (ANN).

[0064] The sample fan-in feature refers to the topological structure and the set of faults to be tested of the circuit corresponding to the lead. The diagnostic vector set T is generated to detect the fault set F in the circuit. Therefore, the fan-in features that affect the diagnostic vector set T include the circuit topological structure and the set of faults to be tested of the circuit.

[0065] Among them, the fan-in characteristics and signal probabilities mentioned in the embodiments of the present application can be applied to the netlist of the flattened logic unit, and can also be applied to the netlist at the library unit level.

[0066] Step 105: Input the actual fan-in feature of the lead into the trained probability prediction model to obtain the actual signal probability of the lead.

[0067] After the probability prediction model is trained, the actual signal probability of the lead can be predicted by the probability prediction model. Specifically, the actual fan-in feature of the lead is input into the trained probability prediction model, and the probability prediction model outputs the actual signal probability of the lead.

[0068] In this application, the simulation of each lead under the diagnostic vector set is used to obtain the sample signal probability, and then the probability prediction model is trained based on the circuit topology, the set of faults to be tested and the sample signal probability, so as to generate the signal probability of the lead through the trained probability prediction model. This application generates the signal probability of the lead based on the diagnostic vector set, and only requires simple model training to output accurate signal probabilities, reducing the running time of ATPG in the circuit and improving the efficiency of diagnostic vector generation.

[0069] In addition, the present application uses a diagnostic vector set in the process of generating sample signal probabilities, which makes the probability prediction model more accurate and subsequently generates actual signal probabilities that are more consistent with ATPG, thereby generating more compact diagnostic vectors based on the actual signal probabilities.

[0070] This application was applied to the circuits ISCAS89 and ITC99, and the indicator tests of diagnostic vector generation (total number of vectors and test generation time) achieved good results. The trained probability prediction model has certain generalization performance and can be applied in ATPG of similar structure circuits.

[0071] The sample fan-in feature or the actual fan-in feature in the embodiment of the present application includes multiple sub-features, which are:

[0072] 1. Gate type: The type of logic gate, including basic logic units AND, NAND, OR, NOR, XOR and XNOR, as well as high-level logic units such as MUX2 (data selector), Tri-State Buffer, etc.

[0073] 2. CC0: 0 controllability calculated by the SCOAP method, that is, the minimum number of input signals required to control the lead to a low level, 0 being a low level.

[0074] 3.CC1: 1 controllability calculated by SCOAP method, i.e. the minimum number of input signals required to control the lead to high level, 1 being high level.

[0075] 4.CO: The observability of the lead calculated by the SCOAP method, that is, the minimum number of input signals required to observe the minimum number of faults on the lead.

[0076] 5. Fanin_i_Reconv: Whether reconvergence occurs at the i-th fan-in.

[0077] 6. Fanin_i_SA0: Whether there is SA0 fault in the i-th fan-in.

[0078] 7. Fanin_i_SA1: Whether there is SA1 fault in the i-th fan-in.

[0079] These sub-features all contribute to the signal probability of the lead. Specifically, the change of Gate Type will directly change the generated diagnostic vector. CC0, CC1 and CO imply the topological relationship and circuit gate information of the circuit, Fanin_i_Reconv imply the topological relationship of the circuit, and Fanin_i_SA0 and Fanin_i_SA1 imply the set information of the faults to be tested in the circuit.

[0080] The number of sub-features depends on the process library used, such as SMIC18, TSMC40, etc. Generally speaking, the basic logic gates defined in the industrial library have a maximum fan-in limit, set to m. Gate type is represented by a one-hot vector. Assuming there are n types of logic gates, the vector is an n-dimensional one-hot vector. CC0, CC1, and CO are all represented by a value, and Fanin_i_Reconv, Fanin_i_SA0, and Fanin_i_SA1 are all Boolean variables. The dimension of the input feature is ,The dimension of the input features is used to determine the input scale of the probability prediction model.

[0081] Figure 3Circuit diagram for calculating the input feature dimension. It can be seen that the logic gate in the circuit has a maximum of 2 inputs and there are 3 types of logic gates, so the dimension of the input feature is 3+(2+1)*3=12.

[0082] As an optional implementation, after obtaining the actual signal probability of the lead being at a high level or a low level, the method further includes: in the ATPG decision, calculating the score of each alternative decision by the actual signal probability; and selecting the decision corresponding to the highest score as the decision to be executed.

[0083] In an embodiment of the present application, in the diagnostic vector generation stage, taking ATPG based on the D algorithm as an example, when the decision tree node of the D algorithm is making a decision, the actual signal probability is used to calculate the score of each decision, and the decision with the highest score is selected as the decision to be executed.

[0084] As an optional implementation, the specific process of training the probability prediction model according to the preset sample fan-in characteristics and sample signal probability includes:

[0085] The server obtains multiple sub-sample features in the sample fan-in feature of the lead, and the sub-sample features are the sub-features mentioned above, such as Gate type, CC0, CC1, CO, Fanin_i_Reconv, Fanin_i_SA0, and Fanin_i_SA1. The server converts each sub-sample feature into a sub-sample vector, and then concatenates the sub-sample vectors to obtain a sample feature vector. The present application can be applied to vector calculations in computers by converting sample fan-in features into sample feature vectors.

[0086] The server inputs the sample feature vector into the initial prediction model to obtain the test signal probability output by the initial prediction model. If the test signal probability is inconsistent with the sample signal probability, the server adjusts the model parameters of the initial prediction model until the test signal probability output by the probability prediction model is consistent with the sample signal probability, thus obtaining a trained probability prediction model.

[0087] Based on the generation process of the sample feature vector, the actual fan-in feature also needs to be converted into a feature vector. The process is as follows: the server obtains multiple sub-actual features of the lead. Here, the sub-actual features refer to the sub-features mentioned above, such as Gatetype, CC0, CC1, CO, Fanin_i_Reconv, Fanin_i_SA0, and Fanin_i_SA1. The server converts each sub-actual feature into a sub-actual vector, and then concatenates the sub-actual vectors to obtain an actual feature vector, and inputs the actual feature vector of the lead into the trained probability prediction model.

[0088] The present application provides a schematic diagram of a signal probability estimation process based on ANN testing and diagnosis, such as Figure 4 As shown, the following steps are included:

[0089] Step 401: In the preprocessing stage, an automatic diagnostic vector generation method is used to generate an optimal diagnostic vector set T in the circuit.

[0090] Step 402: Use a logic simulation tool to simulate diagnostic vectors in sequence on the circuit to obtain a simulation result set sim.

[0091] Step 403: Calculate the sample signal probability: .

[0092] Step 404: Train a probability prediction model according to preset sample fan-in characteristics and sample signal probabilities, and use the trained probability prediction model to output actual signal probability.

[0093] Step 405: In the diagnostic vector generation stage, the test signal probability is used to calculate the scores of possible decisions, and the decision with the highest score is selected as the decision to be executed.

[0094] This application abandons the assumption that the input signal probability is 0.5 in the traditional method, uses the optimal diagnostic vector set to generate sample signal probability, then uses the sample signal probability as the training label, and uses the topological information of the circuit netlist and the fault information to be tested as the feature input, and uses the sample signal probability and sample fan-in features to train the probability prediction model, thereby predicting the signal probability of the lead under the optimal diagnostic vector set. The present invention only requires model training to obtain the signal probability related to ATPR, thereby reducing the running time of ATPG on similar circuits and generating more compact diagnostic vectors. This method has certain generalization.

[0095] The present application provides a signal probability estimation device based on ANN testing and diagnosis, such as Figure 5 As shown, the device comprises:

[0096] A generating module 501, configured to generate an optimal diagnostic vector set in a circuit by using an automatic diagnostic vector generating method, wherein the diagnostic vector set includes a plurality of diagnostic vectors;

[0097] A simulation module 502 is used to simulate the diagnostic vectors in sequence on the circuit through a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector;

[0098] A calculation module 503 is used for taking, for any lead, the average value of the test signal of the lead under different diagnostic vectors as the sample signal probability that the lead is at a high level or a low level;

[0099] A training module 504 is used to train a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include the topological structure of the circuit and the set of faults to be tested, and the probability prediction model is an artificial neural network;

[0100] The input-output module 505 is used to input the actual fan-in characteristics of the lead into the trained probability prediction model to obtain the actual signal probability of the lead.

[0101] Optionally, the formula for calculating the sample signal probability is:

[0102] , where p is the sample signal probability, j is the jth diagnostic vector, is the simulation test set, sim is the result of logic simulation, and i is the i-th lead.

[0103] Optionally, the sample fan-in feature or the actual fan-in feature includes multiple sub-features, which are: the type of logic gate, the minimum number of input signals for the lead to be controlled to a low level, the minimum number of input signals for the lead to be controlled to a high level, the minimum number of input signals when the lead fails the least, whether reconvergence occurs, whether there is an SA0 fault, and whether there is an SA1 fault, wherein the logic gate uses leads for signal input.

[0104] Optionally, the device is also used for:

[0105] In ATPG decision making, the score of each alternative decision is calculated by the actual signal probability;

[0106] The decision corresponding to the highest score is selected as the decision to be executed.

[0107] Optionally, the training module 504 is used to:

[0108] Obtain multiple sub-sample features in the sample fan-in feature of the lead;

[0109] Convert each subsample feature into a subsample vector;

[0110] The sub-sample vectors are concatenated to obtain the sample feature vector;

[0111] The probability prediction model is trained according to the sample feature vector and the sample signal probability to obtain a trained probability prediction model.

[0112] Optionally, the training module 504 is used to:

[0113] Input the sample feature vector into the initial prediction model to obtain the test signal probability output by the initial prediction model;

[0114] When the test signal probability is inconsistent with the sample signal probability, the model parameters of the initial prediction model are adjusted to obtain a trained probability prediction model, wherein the test signal probability output by the trained probability prediction model is consistent with the sample signal probability.

[0115] Optionally, the input and output module 505 is used to:

[0116] Get multiple sub-actual features of the lead;

[0117] Convert each sub-actual feature into a sub-actual vector;

[0118] The actual feature vector is obtained by concatenating the sub-actual vectors;

[0119] The actual feature vector of the lead is input into the trained probability prediction model.

[0120] like Figure 6 As shown, an embodiment of the present application provides an electronic device, including a processor 601, a communication interface 602, a memory 603 and a communication bus 604, wherein the processor 601, the communication interface 602, and the memory 603 communicate with each other through the communication bus 604.

[0121] The memory 603 is used to store computer programs.

[0122] In one embodiment of the present application, the processor 601 is used to implement the signal probability estimation method based on ANN testing and diagnosis provided by any one of the aforementioned method embodiments when executing the program stored in the memory 603.

[0123] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the signal probability estimation method based on ANN testing and diagnosis provided in any of the aforementioned method embodiments are implemented.

[0124] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment.

[0126] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0127] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A signal probability estimation method based on ANN testing and diagnosis, characterized in that: The method comprises: An automatic diagnostic vector generation method is used to generate an optimal diagnostic vector set in a circuit, wherein the diagnostic vector set includes a plurality of diagnostic vectors; Simulating the diagnostic vectors in sequence on the circuit by a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector; For any lead, taking the average value of the test signal of the lead under different diagnostic vectors as the sample signal probability of the lead being at a high level or a low level; Training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include the topological structure of the circuit and the set of faults to be tested, and the probability prediction model is an artificial neural network; Input the actual fan-in feature of the lead into the trained probability prediction model to obtain the actual signal probability of the lead; Among them, the sample fan-in feature or the actual fan-in feature includes multiple sub-features, and the sub-features are: the type of logic gate, the minimum number of input signals for the lead to be controlled to a low level, the minimum number of input signals for the lead to be controlled to a high level, the minimum number of input signals when the lead fails at the least, whether reconvergence occurs, whether there is an SA0 fault, and whether there is an SA1 fault, wherein the logic gate uses the lead for signal input.

2. The method according to claim 1, characterized in that: The formula for calculating the probability of a sample signal is: , where p is the sample signal probability, j is the jth diagnostic vector, is the simulation test set, sim is the result of logic simulation, and i is the i-th lead.

3. The method according to claim 1, characterized in that: After obtaining the actual signal probability that the lead is at a high level or a low level, the method further includes: In ATPG decision making, a score of each alternative decision is calculated by the actual signal probability; The decision corresponding to the highest score is selected as the decision to be executed.

4. The method according to claim 1, characterized in that: The probability prediction model is trained based on the preset sample fan-in characteristics and sample signal probability, including: Obtain multiple sub-sample features in the sample fan-in feature of the lead; Convert each of the sub-sample features into a sub-sample vector; splicing the sub-sample vectors to obtain a sample feature vector; A probability prediction model is trained according to the sample feature vector and the sample signal probability to obtain a trained probability prediction model.

5. The method according to claim 4, characterized in that Training a probability prediction model according to the sample feature vector and the sample signal probability includes: Inputting the sample feature vector into an initial prediction model to obtain a test signal probability output by the initial prediction model; When the test signal probability is inconsistent with the sample signal probability, the model parameters of the initial prediction model are adjusted to obtain a trained probability prediction model, wherein the test signal probability output by the trained probability prediction model is consistent with the sample signal probability.

6. The method according to claim 1, characterized in that Inputting the actual fan-in characteristics of the leads into the trained probability prediction model includes: Get multiple sub-actual features of the lead; converting each of the sub-actual features into a sub-actual vector; splicing the sub-actual vectors to obtain an actual feature vector; The actual feature vector of the lead is input into the trained probability prediction model.

7. A signal probability estimation device based on ANN testing and diagnosis, characterized in that: The device comprises: A generating module, used for generating an optimal diagnostic vector set in a circuit by using an automatic diagnostic vector generating method, wherein the diagnostic vector set includes a plurality of diagnostic vectors; A simulation module, used to simulate the diagnostic vectors in sequence on the circuit through a logic simulation tool to obtain a simulation result set, wherein the simulation result set is a test signal of each lead under each diagnostic vector; A calculation module, for taking, for any lead, an average value of the test signal of the lead under different diagnostic vectors as the sample signal probability that the lead is at a high level or a low level; A training module, used for training a probability prediction model according to preset sample fan-in features and sample signal probabilities, wherein the sample fan-in features include a circuit topology and a set of faults to be tested, and the probability prediction model is an artificial neural network; An input-output module, used for inputting the actual fan-in feature of the lead into the trained probability prediction model to obtain the actual signal probability of the lead; Among them, the sample fan-in feature or the actual fan-in feature includes multiple sub-features, and the sub-features are: the type of logic gate, the minimum number of input signals for the lead to be controlled to a low level, the minimum number of input signals for the lead to be controlled to a high level, the minimum number of input signals when the lead fails at the least, whether reconvergence occurs, whether there is an SA0 fault, and whether there is an SA1 fault, wherein the logic gate uses the lead for signal input.

8. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-6 when executing a program stored in a memory.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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