Planar SGOI SiGe HBT device and manufacturing method thereof

Abstract

The present invention provides a planar SGOI SiGe HBT device and a manufacturing method thereof, wherein the HBT device can be used to be integrated with a CMOS unipolar device to form a Bi-CMOS device. In a typical CMOS structure, it includes a Si substrate, a SiGe buffer layer, an N / P channel structure with strained Si, and a gate oxide layer. In order to achieve consistency in materials and manufacturing processes between HBT and CMOS, the HBT device forms a SiGe collector region, a SiGe base region, and an emitter region on an insulating layer, and its material layer structure is similar to that of a CMOS unipolar device. This allows HBT bipolar devices and CMOS unipolar devices to be produced in synergy in the same manufacturing process, significantly reducing process complexity and budget.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a planar SGOI SiGe HBT device and a manufacturing method thereof. Background Art

[0002] In the modern electronics industry, especially in the development of integrated circuits, with the enhancement of chip functions and the improvement of integration, the further reduction of device feature size is facing many challenges. In this context, silicon-based circuits have begun to be widely used in microwave and millimeter wave fields, such as 77GHz automotive radar systems and 94GHz imaging systems. These applications have promoted the demand for high-performance, low-power SiGe BiCMOS (silicon germanium bipolar CMOS) technology.

[0003] Although silicon-based processes are suitable for large-scale high-integrated circuit applications due to their full compatibility with existing CMOS processes, the performance improvement of traditional silicon devices in terms of high speed and high frequency is limited by the physical properties of the material. While III-V compound semiconductor devices such as GaAs and InP have obvious advantages in high-speed and high-frequency performance, their high cost and incompatibility with silicon device processes limit their widespread application in the commercial field. In order to overcome these limitations, SiGe HBT (Heterojunction Bipolar Transistor) technology came into being. By introducing germanium elements into the SiGe base region of the silicon-based bipolar junction transistor, the performance of the device is significantly improved, making SiGe HBT the preferred technology in high-speed applications.

[0004] As a bipolar device, SiGe HBT devices are often integrated with CMOS unipolar devices as Bi-CMOS devices in high-speed digital and radio frequency integrated circuits. Therefore, it is urgent to provide a high-performance SiGe HBT device with process consistency and material layer structure similarity to Bi-CMOS devices to ensure the performance improvement of unipolar and bipolar devices without increasing process complexity and cost. Summary of the invention

[0005] The object of the present invention is to provide a planar SGOI SiGe HBT device and a manufacturing method thereof.

[0006] The present invention provides a planar SGOI SiGe HBT device, the HBT device comprising a substrate, an insulating layer formed on the substrate;

[0007] A SiGe collector region is formed on the insulating layer, the SiGe collector region includes a sub-collector region formed adjacent to the insulating layer, and a main collector region formed on the sub-collector region, and an N-type doping concentration of the sub-collector region is higher than an N-type doping concentration of the main collector region;

[0008] A SiGe base window region is defined on the surface of the SiGe collector region, and the SiGe base region is formed in the SiGe base window region;

[0009] A Si emitter window region is defined on the surface of the SiGe base region, and the Si emitter region is formed in the Si emitter window region;

[0010] The electrode lead-out window on the surface of the SiGe collector region forms a first electrode lead-out structure extending outward, the electrode lead-out window on the surface of the SiGe base region forms a second electrode lead-out structure extending outward, and the electrode lead-out window on the surface of the Si emitter region forms a third electrode lead-out structure extending outward.

[0011] As a further improvement of the present invention, the Ge component of the main collector region is 15%, and P element is used for doping. In the sub-collector region, the doping concentration is 4.5×10 19 ~5.5×10 19 cm -3 In the main collector region, the doping concentration is 4.5×10 17 ~5.5×10 17 cm -3 .

[0012] As a further improvement of the present invention, a high-concentration doping region is formed at a contact surface between the main collector region and the first electrode lead-out structure, and the doping concentration of the high-concentration doping region is higher than the doping concentration of the main collector region.

[0013] As a further improvement of the present invention, the SiGe base region includes an intrinsic base region and an extrinsic base region, the Si emitter region window region is located on the surface of the intrinsic base region, the extrinsic base region vectorally extends from the intrinsic base region, and an insulating isolation layer is formed between the extrinsic base region and the SiGe collector region.

[0014] As a further improvement of the present invention, a first intrinsic SiGe layer is formed between the intrinsic base region and the main collector region, and a second intrinsic SiGe layer is formed between the intrinsic base region and the Si emitter region, and the Ge component of the first intrinsic SiGe layer is higher than the Ge component of the second intrinsic SiGe layer.

[0015] As a further improvement of the present invention, in the SiGe base region, the Ge component first presents a uniform distribution of the Ge component from the SiGe collector region side to the Si emitter region side, and then presents a changing distribution from high to low.

[0016] As a further improvement of the present invention, in the intrinsic base region, the Ge component first presents a uniform distribution of 30% Ge component from the SiGe collector region side to the Si emitter region side, and then presents a linear change distribution of Ge component from 30% to 15%.

[0017] As a further improvement of the present invention, the ends of the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure are located in the same plane, the first electrode lead-out structure includes N-type doped polysilicon led outward from the main collector region and an electrode formed at the end of the N-type doped polysilicon, the second electrode lead-out structure includes P-type doped polysilicon led outward from the SiGe base region and an electrode formed at the end of the P-type doped polysilicon, the third electrode lead-out structure includes N-type doped polysilicon led outward from the Si emitter region and an electrode formed at the end of the N-type doped polysilicon, and an insulating isolation structure is formed between the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure.

[0018] As a further improvement of the present invention, the substrate is a Si substrate with a crystal orientation of (100) and is doped with a P-type element at a doping concentration of 0.5×10 15 ~1.5×10 15 cm -3 .

[0019] As a further improvement of the present invention, the insulating layer is a SiO2 buried oxide layer.

[0020] The present invention also provides a method for manufacturing a planar SGOI SiGe HBT device, which comprises the steps of:

[0021] providing a substrate on which an insulating layer is grown;

[0022] Growing a sub-collector region of SiGe material on the insulating layer and performing N-type doping, growing a main collector region of SiGe material on the sub-collector region and performing N-type doping to form a SiGe collector region, wherein the N-type doping concentration of the sub-collector region is higher than the N-type doping concentration of the main collector region;

[0023] Growing a SiGe base region at a SiGe base region window on the surface of the SiGe collector region;

[0024] Growing Si material at the Si emitter window on the surface of the SiGe base region to form the Si emitter region;

[0025] An electrode lead-out window is grown on the surface of the main collector region to form a first electrode lead-out structure extending outward, an electrode lead-out window is grown on the surface of the SiGe base region to form a second electrode lead-out structure extending outward, and a third electrode lead-out structure is formed on the surface of the Si emitter region to extend outward, wherein the ends of the first electrode lead-out structure, the second electrode lead-out structure and the third electrode lead-out structure are located in the same plane.

[0026] As a further improvement of the present invention, the step of growing a sub-collector region of SiGe material on the insulating layer and performing N-type doping, and growing a main collector region of SiGe material on the sub-collector region and performing N-type doping specifically includes:

[0027] The sub-collector region of SiGe material is grown, the Ge component of the main collector region is 15%, and P element is doped with a doping concentration of 4.5×10 19 ~5.5×10 19 cm -3 The main collector region of SiGe material is grown on the sub-collector region and doped with P element with a doping concentration of 4.5×10 17 ~5.5×10 17 cm -3 .

[0028] As a further improvement of the present invention, the growing of the SiGe base region at the SiGe base region window on the surface of the SiGe collector region specifically includes:

[0029] Depositing and growing a SiO2 layer on the surface of the SiGe collector region, and etching the SiO2 layer to form a SiGe base region window;

[0030] Growing a first intrinsic SiGe layer in the SiGe base window;

[0031] The compressively strained SiGe material is grown to form a working SiGe base region, and B element is used for doping with a doping concentration of 1.5×10 19 ~2.5×10 19 cm -3 In the working SiGe base region, the Ge component is first evenly distributed and then linearly reduced.

[0032] As a further improvement of the present invention, depositing Si material at the Si emitter window on the surface of the SiGe base region to form the Si emitter region specifically includes:

[0033] A tensile strained Si material is deposited on the surface of the SiGe base region and doped with P element at a doping concentration of 0.8×10 18 ~1.2×10 18 cm -3 , etching to form the Si emitter region.

[0034] As a further improvement of the present invention, after growing a sub-collector region of SiGe material on the insulating layer and performing an N-type doping step, the method further comprises:

[0035] Depositing an isolation layer, etching to expose the contact area between the surface of the SiGe collector region and the first electrode lead-out structure, and performing P ion implantation;

[0036] The deposited isolation layer is etched.

[0037] As a further improvement of the present invention, the electrode lead-out window on the surface of the main collector region grows to form a first electrode lead-out structure extending outward, the electrode lead-out window on the surface of the SiGe base region grows to form a second electrode lead-out structure extending outward, and the third electrode lead-out structure extending outward is formed on the surface of the Si emitter region, specifically comprising:

[0038] Depositing an isolation layer, and etching to expose electrode lead-out windows of the SiGe collector region and the Si emitter region;

[0039] Depositing N-type doped polysilicon, and etching away the N-type doped polysilicon except for the electrode lead-out windows of the SiGe collector region and the Si emitter region;

[0040] Depositing an isolation layer, and etching to expose electrode lead-out windows of the SiGe collector region and the Si emitter region;

[0041] Depositing P-type doped polysilicon, and etching away the P-type doped polysilicon except for the SiGe base electrode lead-out window;

[0042] Metal is sputtered on the surface of the N-type doped polysilicon and the P-type doped polysilicon to form the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure.

[0043] As a further improvement of the present invention, providing a substrate and growing an insulating layer on the substrate specifically includes:

[0044] Provide a Si substrate with a crystal orientation of (100) and dope it with P element at a doping concentration of 0.5×10 15 cm -3 ~1.5×10 15 cm -3 .

[0045] As a further improvement of the present invention, the growing of the insulating layer on the substrate specifically includes:

[0046] A SiO2 buried oxide layer is grown on the substrate to form an insulating layer.

[0047] The beneficial effects of the present invention are as follows: the present invention provides a planar SGOI SiGe HBT device and a manufacturing method thereof, and the HBT device can be used to be integrated with a CMOS unipolar device to form a Bi-CMOS device. In a typical CMOS device, the structure includes a Si substrate, a SiGe buffer layer, an N / P channel structure with strained Si, and a gate oxide layer. In order to achieve consistency in materials and manufacturing processes between HBT and CMOS, the HBT device forms a SiGe collector region, a SiGe base region, and an emitter region on the insulating layer, and its material layer structure is similar to that of a CMOS unipolar device. This allows HBT bipolar devices and CMOS unipolar devices to be produced in synergy in the same manufacturing process, significantly reducing process complexity and budget.

[0048] In addition, the SiGe base region of the HBT shares similar materials and epitaxial growth processes with the SiGe buffer layer in CMOS, ensuring process compatibility, and utilizing the biaxial stress provided by the SiGe material in the main collector region to optimize carrier mobility, thereby improving the current gain and response speed of the base region. The entire design introduces stress and changes the band structure of the Si / SiGe material, optimizing the injection and extraction efficiency of electrons and holes, and significantly improving the frequency response and gain of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 FIG. 1 is a schematic diagram of the structure of a planar SGOI SiGe HBT device in one embodiment of the present invention.

[0050] Figure 2 Schematic diagram of the steps of a method for manufacturing a planar SGOI SiGe HBT device in one embodiment of the present invention.

[0051] Figure 3~Figure 11 It is a schematic structural diagram of each step in a method for manufacturing a planar SGOI SiGe HBT device in one embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in combination with the specific implementation methods of the present invention and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of the present invention, not all implementation methods. Based on the implementation methods of the present invention, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0053] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0054] This embodiment provides a planar SGOI (Silicon-Germanium-On-Insulator) SiGe HBT device, which is used to be integrated with a CMOS unipolar device into a Bi-CMOS device. In a common CMOS unipolar device, it includes a Si substrate, a SiGe buffer layer, a relaxed SiGe layer, an N and P channel structure with strained Si, and a gate oxide layer in sequence. The HBT device in this embodiment forms a material layer structure similar to that of a CMOS unipolar device during the manufacturing process by adopting a structure in which a SiGe collector region 3, a SiGe base region 4, and a Si emitter region 5 are formed on an insulating layer 2, thereby realizing a manufacturing collaborative process of a bipolar SiGe HBT device and a CMOS unipolar device, significantly reducing process complexity and budget.

[0055] like Figure 1 As shown, a planar SGOI SiGe HBT device comprises a substrate 1 and an insulating layer 2 formed on the substrate 1 .

[0056] A SiGe collector region 3 is formed on the insulating layer 2 , and the SiGe collector region 3 includes a sub-collector region 31 formed adjacent to the insulating layer 2 , and a main collector region 32 formed on the sub-collector region 31 , wherein the N-type doping concentration of the sub-collector region 31 is higher than the N-type doping concentration of the main collector region 32 .

[0057] A base window region is defined on the surface of the SiGe collector region 3, and the SiGe base region 4 is formed in the base window region. An emitter window region is defined on the surface of the SiGe base region 4, and the Si emitter region 5 is formed in the base window region.

[0058] Specifically, the substrate 1 is a Si substrate with a crystal orientation of (100) and is doped with a P-type element with a doping concentration of 0.5×10 15 ~1.5×10 15 cm -3 , for example, in this embodiment, the doping concentration is 1×10 15 cm -3 Substrate 1 is lightly doped P-type Si. P-type Si forms excess holes by introducing acceptor impurities in Si. Light doping helps maintain the semiconductor properties of the material and allows charge carriers to be more easily controlled by an external electric field.

[0059] The insulating layer 2 is a SiO2 buried oxide layer, which can effectively isolate the substrate 1 from the active layer thereon, reduce unnecessary charge leakage from the active layer to the substrate 1, thereby significantly reducing parasitic capacitance and improving the switching performance and dynamic response speed of the HBT device. In addition, the insulating layer 2 can play a role in physical isolation, reducing the impact of impurities and defects in the substrate 1 on the active area of ​​the device, especially in silicon germanium materials, which can significantly reduce leakage current and electromagnetic interference, and enhance the overall performance of the device and signal clarity.

[0060] The first formed insulating layer 2 provides a solid basic platform for the growth of the SiGe collector region 3 thereon, which not only makes the growth of the upper SiGe more stable and uniform, but also makes the entire SGOI structure compatible with the standard CMOS manufacturing process, providing convenience for further device integration.

[0061] Furthermore, the SiGe collector region 3 is made of SiGe material, which corresponds to the SiGe buffer layer in the CMOS unipolar device in terms of structure and manufacturing process. When the HBT device and the CMOS device are integrated on the same wafer, the HBT device and the CMOS device can share similar manufacturing processes for the epitaxial growth and doping control of the SiGe layer, ensuring process compatibility. Using the same SiGe material and process helps to reduce manufacturing steps and improve production efficiency.

[0062] Compared with using pure Si as the material of the collector region, in this embodiment, the main collector region 32 uses SiGe material to provide higher carrier mobility to improve the performance of the device. The SiGe collector region 3 can act as a stress source, which provides biaxial stress to other regions. The SiGe base region 4 is subjected to biaxial compressive stress, and the compressive stress can increase the hole mobility, thereby improving the current gain and response speed of the base region. The Si emitter region 5 is subjected to biaxial tensile stress, and the tensile stress can increase the electron mobility, improve the switching speed and high-frequency characteristics of the device.

[0063] By introducing stress, the energy band structure of Si / SiGe materials is changed, so that the band gap of the base region and the emitter region can be optimized through stress adjustment, the injection and extraction of electrons and holes are more efficient, the probability of charge recombination is reduced, and the frequency response and gain of the device are improved. Stress improves the mobility of carriers. High mobility directly leads to a reduction in the transit time of electrons in the base region. The reduction in the transit time of the base region can increase the cutoff frequency and maximum oscillation frequency of the transistor, so that the device can process higher-speed signals, improve the switching speed of the device and reduce signal transmission delay.

[0064] Furthermore, the SiGe collector region 3 includes a sub-collector region 31 and a main collector region 32. The Ge components in the sub-collector region 31 and the main collector region 32 are both 15%, and both are N-type doped, with the doping element being P. In the sub-collector region 31, the doping concentration is 4.5×10 19 ~5.5×10 19 cm -3 , for example, in this embodiment, the doping concentration is 5×10 19 cm -3 In the main collector region 32, the doping concentration is 4.5×10 17 ~5.5×10 17 cm -3 , for example, in this embodiment, the doping concentration is 5×10 17 cm -3 Exemplarily, the thickness of the sub-collector region 31 is 180 nm, and the thickness of the main collector region 32 is 120 nm.

[0065] The sub-collector region 31 has a high doping concentration, which can significantly reduce the resistance of the main collector region 32, forming a low resistance path, and ensuring that electrons can be quickly and efficiently transferred from the base region to the main collector region 32. There is a doping concentration gradient between the sub-collector region 31 and the main collector region 32, and the gradient forms a built-in electric field that helps control and guide the movement of electrons. At the interface between the highly doped sub-collector region 31 and the low-doped main collector region 32, the electric field distribution helps accelerate the electrons to enter the main collector region 32, thereby improving the device's collection efficiency.

[0066] Furthermore, the SiGe base region 4 includes an intrinsic base region 41 and an extrinsic base region 42 , the emitter region window region is located on the surface of the intrinsic base region 41 , the extrinsic base region 42 vectorially extends from the intrinsic base region 41 , and an insulating isolation layer 6 is formed between the extrinsic base region 42 and the SiGe collector region 3 .

[0067] The intrinsic base region 41 is directly in contact with the Si emitter region 5 and the SiGe collector region 3, and is the region where the carriers mainly pass through and the main flow path of the current. The extrinsic base region 42 is a portion drawn out from the intrinsic base region 41, and is used to connect the intrinsic base region 41 and the external electrode. The extrinsic base region 42 is formed on the insulating isolation layer 6 to ensure electrical isolation between the SiGe base region 4 and the SiGe collector region 3, thereby reducing parasitic capacitance and leakage current.

[0068] Furthermore, a first intrinsic SiGe layer 43 is formed between the intrinsic base region 41 and the main collector region 32 , and a second intrinsic SiGe layer 44 is formed between the intrinsic base region 41 and the emitter region, and the Ge component of the first intrinsic SiGe layer 43 is higher than the Ge component of the second intrinsic SiGe layer 44 .

[0069] In the base region, the Ge component first presents a uniform distribution of the Ge component from the SiGe collector region 3 side to the Si emitter region 5 side, and then presents a changing distribution from high to low.

[0070] Specifically, in the intrinsic base region 41, the Ge component first presents a uniform distribution of 30% Ge component from the side of the SiGe collector region 3 to the side of the Si emitter region 5, and then presents a linear distribution of Ge component from 30% to 15%. Exemplarily, the thickness of the intrinsic base region 41 is 15nm, wherein the thickness of the intrinsic base region 41 with uniform Ge component distribution is 8nm, and the thickness of the intrinsic base region 41 with linear Ge component distribution is 7nm.

[0071] In the intrinsic base region 41, the Ge component near the side of the SiGe collector region 3 is 30% and evenly distributed, forming a stable and efficient carrier injection region. Increasing the Ge component will cause the band gap of the SiGe alloy to decrease. The Ge trapezoidal distribution in the base region that gradually decreases from 30% to 15% creates a continuously changing band gap gradient. This gradient helps to form a built-in electric field, which naturally guides the migration of holes from the emission region to the collector region. As the holes move to the emission region, the gradually decreasing Ge component helps to effectively collect these carriers because the energy band gradually increases, forming an energy "trap" to reduce the reverse flow of carriers.

[0072] From the SiGe collector region 3 side to the Si emitter region 5 side, the Ge component gradually decreases from 30% to 15%. The linear change design smoothes the energy band transition, avoids the sudden energy band step effect at the material interface, reduces the probability of carrier recombination in the transition zone, optimizes the carrier migration path, reduces the carrier transit time, and improves the injection efficiency and device gain. In addition, the smooth Ge component change reduces the influence of parasitic capacitance and parasitic resistance, and improves the signal integrity in high-frequency operation. The uniform distribution of high Ge components combined with the linear change ensures the rapid migration and effective injection of carriers in the base region, making the HBT device perform well in high-frequency applications.

[0073] Growing undoped intrinsic SiGe material on the side close to the collector region can prevent the boron impurities in the base region from diffusing into the collector region, reduce the parasitic barrier effect, and ensure the efficient and stable operation of the device. The Ge component is controlled to 30% to achieve a trapezoidal distribution of the Ge component in the base region. Similarly, growing an undoped intrinsic SiGe material with a Ge component of 15% on the side close to the emitter region can reduce the diffusion of boron impurities into the emitter region. The Ge component is controlled to 15% to achieve a trapezoidal distribution of the Ge component in the base region.

[0074] The SiGe base region 4 in the HBT device and the relaxed SiGe layer in the CMOS unipolar device both use SiGe materials and are realized through epitaxial growth technology, and can be applied to the manufacture of different devices on the same production line. By controlling the Ge content and doping concentration, the different electrical and physical requirements of HBT and CMOS devices can be met. During the manufacturing process, common material growth steps and doping processes can be designed so that the two devices can be optimized in the same process flow. The SiGe base region 4 of the HBT device and the relaxed SiGe layer of the CMOS device can be compatible in terms of materials and manufacturing processes.

[0075] Furthermore, the Si emitter region 5 is made of tensile strained Si material, and the P doping concentration is 0.8×10 18 ~1.2×10 18 cm -3 , for example, in this embodiment, the doping concentration is 1×10 18 cm -3 .

[0076] A thin layer of Si is epitaxially grown on the SiGe base region 4. The lattice constant of the SiGe layer is greater than that of Si, so the Si layer grown thereon will be stretched to produce tensile strain. The tensile strain changes the crystal structure of silicon, reduces the effective mass of electrons, and thus improves the mobility of electrons.

[0077] The epitaxial growth technology and doping method of tensile strained Si materials are compatible with the strained Si in the existing CMOS unipolar device structure, and existing equipment and processes can be used in the manufacturing process to reduce production costs and complexity.

[0078] Furthermore, the electrode lead-out window on the surface of the SiGe collector region 3 forms a first electrode lead-out structure 71 extending outward, the electrode lead-out window on the surface of the SiGe base region 4 forms a second electrode lead-out structure 72 extending outward, and the electrode lead-out window on the surface of the Si emitter region 5 forms a third electrode lead-out structure 73 extending outward, and the ends of the first electrode lead-out structure 71, the second electrode lead-out structure 72, and the third electrode lead-out structure 73 are located in the same plane.

[0079] Specifically, the first electrode lead-out structure 71 includes N-type doped polysilicon led outward from the main collector region 32 and an electrode formed at the end of the N-type doped polysilicon, the second electrode lead-out structure 72 includes P-type doped polysilicon led outward from the base region and an electrode formed at the end of the P-type doped polysilicon, the third electrode lead-out structure 73 includes N-type doped polysilicon led outward from the emitter region and an electrode formed at the end of the N-type doped polysilicon, and an insulating isolation structure 8 is formed between the first electrode lead-out structure 71, the second electrode lead-out structure 72, and the third electrode lead-out structure 73.

[0080] An electrode lead-out window is provided on the surface of the SiGe collector region 3 to connect the collector region to an external circuit. A high-concentration doping region 33 is formed at the contact surface between the main collector region 32 and the first electrode lead-out structure 71 , and its doping concentration is higher than that of the main collector region 32 .

[0081] Electrode lead-out windows are provided on the surface of the SiGe collector region 3. These windows are used to connect the collector region and the external circuit to ensure the effective transmission of current. In order to further optimize the current transmission efficiency and reduce the contact resistance, a high-concentration doping region 33 is designed at the contact surface between the main collector region 32 and the first electrode lead-out structure 71. The high-concentration doping region 33 significantly reduces the contact resistance between the main collector region 32 and the first electrode lead-out structure 71. The low contact resistance ensures that the current can be efficiently transmitted from the collector region to the electrode lead-out structure, reducing power loss.

[0082] N-type doped polysilicon is used in the collector and emitter electrode lead structures to improve conductivity and carrier mobility. N-type doped polysilicon provides a low resistance path to ensure efficient current transmission and reduce power loss. Similarly, P-type doped polysilicon is used in the base electrode lead structure to ensure good electrical contact with the base region, improve the carrier injection efficiency, and enhance the current gain of the device.

[0083] The ends of all electrode lead-out structures are located in the same plane, which simplifies the packaging process and improves the electrical performance and mechanical stability of the device.

[0084] like Figure 2 As shown, this embodiment also provides a method for manufacturing a planar SGOI SiGe HBT device, which includes the steps of:

[0085] S1: providing a substrate 1 , and growing an insulating layer 2 on the substrate 1 .

[0086] S2: A sub-collector region 31 of SiGe material is grown on the insulating layer 2 and N-type doped, and a main collector region 32 of SiGe material is grown on the sub-collector region 31 and N-type doped to form a SiGe collector region 3. The N-type doping concentration of the sub-collector region 31 is higher than the N-type doping concentration of the main collector region 32.

[0087] S3: growing a SiGe base region 4 at the base region window on the surface of the SiGe collector region 3 .

[0088] S4: growing Si material at the emission region window on the surface of the SiGe base region 4 to form the Si emission region 5.

[0089] S5: An electrode lead-out window is grown on the surface of the main collector region 32 to form a first electrode lead-out structure 71 extending outward, an electrode lead-out window is grown on the surface of the base region to form a second electrode lead-out structure 72 extending outward, and a third electrode lead-out structure 73 extending outward is formed on the surface of the emitter region, wherein the ends of the first electrode lead-out structure 71, the second electrode lead-out structure 72, and the third electrode lead-out structure 73 are located in the same plane.

[0090] Specifically, step S1 includes:

[0091] like Figure 3 As shown, a Si substrate with a crystal orientation of (100) is provided, and P element is doped with a doping concentration of 1×10 15 cm -3 Then, a SiO2 buried oxide layer is grown on the substrate 1 to form an insulating layer 2.

[0092] Specifically, step S2 includes:

[0093] like Figure 4 As shown, a sub-collector region 31 of SiGe material is grown, the main collector region 32 has a Ge component of 15%, and is doped with P element at a doping concentration of 4.5×10 19 ~5.5×10 19 cm -3 A main collector region 32 of SiGe material is grown on the sub-collector region 31, and P element is used for doping, and the doping concentration is 4.5×10 17 ~5.5×10 17 cm -3 .

[0094] Furthermore, step S2 further includes:

[0095] like Figure 5 As shown, an isolation layer is deposited, and etching is performed to expose the contact area between the surface of the SiGe collector region 3 and the first electrode lead-out structure 71 , and P ion implantation is performed to etch the deposited isolation layer.

[0096] Specifically, step S3 includes:

[0097] like Figure 6 As shown, a SiO2 layer is deposited and grown on the surface of the SiGe collector region 3, and the SiO2 layer is etched to form a base region window;

[0098] Growing a first intrinsic SiGe layer 43 in the base window;

[0099] The compressively strained SiGe material is grown to form the working base region, and the B element is doped with a doping concentration of 1.5×10 19 ~2.5×10 19 cm-3 In the working base region, the Ge component is first evenly distributed and then linearly reduced.

[0100] Specifically, step S4 includes:

[0101] like Figure 7 As shown, tensile strained Si material is deposited on the surface of the SiGe base region 4 and doped with P element with a doping concentration of 0.8×10 18 ~1.2×10 18 cm -3 , etching to form the Si emitter region 5.

[0102] Specifically, step S5 includes:

[0103] like Figure 8 As shown, an isolation layer is deposited, and electrode lead-out windows of the SiGe collector region 3 and the Si emitter region 5 are exposed by etching.

[0104] like Fig. 9 As shown, N-type doped polysilicon is deposited, and the N-type doped polysilicon except for the electrode lead-out windows of the SiGe collector region 3 and the Si emitter region 5 is etched away.

[0105] like Fig.10 As shown, an isolation layer is deposited, and electrode lead-out windows of the SiGe collector region 3 and the Si emitter region 5 are exposed by etching.

[0106] like Fig.11 As shown, P-type doped polysilicon is deposited, and the P-type doped polysilicon except for the electrode lead-out window of the SiGe base region 4 is etched away.

[0107] like Figure 1 As shown, metal is sputtered on the surface of the N-type doped polysilicon and the P-type doped polysilicon to form the first electrode lead-out structure 71 , the second electrode lead-out structure 72 , and the third electrode lead-out structure 73 .

[0108] In summary, this embodiment provides a planar SGOI SiGe HBT device and a manufacturing method thereof, which are used to be integrated with a CMOS unipolar device to form a Bi-CMOS device. In a typical CMOS device, the structure includes a Si substrate, a SiGe buffer layer, an N / P channel structure with strained Si, and a gate oxide layer. In order to achieve consistency in materials and manufacturing processes between HBT and CMOS, the HBT device forms a SiGe collector region 3, a SiGe base region 4, and an emitter region on the insulating layer 2, and its material layer structure is similar to that of a CMOS unipolar device. This allows HBT bipolar devices and CMOS unipolar devices to be produced in synergy in the same manufacturing process, significantly reducing process complexity and budget.

[0109] In addition, the SiGe base region 4 of the HBT shares similar materials and epitaxial growth processes with the SiGe buffer layer in the CMOS, ensuring process compatibility, and utilizing the biaxial stress provided by the SiGe material in the main collector region 32 to optimize the carrier mobility, thereby improving the current gain and response speed of the base region. The entire design introduces stress and changes the band structure of the Si / SiGe material, optimizes the injection and extraction efficiency of electrons and holes, and significantly improves the frequency response and gain of the device.

[0110] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0111] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A planar SGOI SiGe HBT device, characterized in that: The HBT device includes a substrate and an insulating layer formed on the substrate; A SiGe collector region is formed on the insulating layer, the SiGe collector region includes a sub-collector region formed adjacent to the insulating layer, and a main collector region formed on the sub-collector region, and an N-type doping concentration of the sub-collector region is higher than an N-type doping concentration of the main collector region; A SiGe base window region is defined on the surface of the SiGe collector region, and the SiGe base region is formed in the SiGe base window region; The surface of the SiGe base region is defined with a Si emitter region window region, and the Si emitter region is formed in the Si emitter region window region; The SiGe base region includes an intrinsic base region and an extrinsic base region, the Si emitter region window region is located on the surface of the intrinsic base region, the extrinsic base region vectorially extends from the intrinsic base region, and an insulating isolation layer is formed between the extrinsic base region and the SiGe collector region; A first intrinsic SiGe layer is formed between the intrinsic base region and the main collector region, and a second intrinsic SiGe layer is formed between the intrinsic base region and the Si emitter region, wherein the Ge component of the first intrinsic SiGe layer is higher than the Ge component of the second intrinsic SiGe layer; In the SiGe base region, the Ge component first presents a uniform distribution of the Ge component from the SiGe collector region side to the Si emitter region side, and then presents a linear distribution from high to low; The electrode lead-out window on the surface of the SiGe collector region forms a first electrode lead-out structure extending outward, the electrode lead-out window on the surface of the SiGe base region forms a second electrode lead-out structure extending outward, and the electrode lead-out window on the surface of the Si emitter region forms a third electrode lead-out structure extending outward.

2. The planar SGOI SiGe HBT device according to claim 1, characterized in that: The Ge component of the main collector region is 15%, and P element is used for doping. In the sub-collector region, the doping concentration is 4.5×10 19 ~5.5×10 19 cm -3 In the main collector region, the doping concentration is 4.5×10 17 ~5.5×10 17 cm -3 .

3. The planar SGOI SiGe HBT device according to claim 1, characterized in that: A high-concentration doping region is formed at a contact surface between the main collector region and the first electrode lead-out structure, and the doping concentration of the high-concentration doping region is higher than the doping concentration of the main collector region.

4. The planar SGOI SiGe HBT device according to claim 1, characterized in that: In the intrinsic base region, the Ge component first presents a uniform distribution of 30% Ge component from the SiGe collector region side to the Si emitter region side, and then presents a linear distribution of Ge component changing from 30% to 15%.

5. The planar SGOI SiGe HBT device according to claim 1, characterized in that: The ends of the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure are located in the same plane, the first electrode lead-out structure includes N-type doped polysilicon led outward from the main collector region and an electrode formed at the end of the N-type doped polysilicon, the second electrode lead-out structure includes P-type doped polysilicon led outward from the SiGe base region and an electrode formed at the end of the P-type doped polysilicon, the third electrode lead-out structure includes N-type doped polysilicon led outward from the Si emitter region and an electrode formed at the end of the N-type doped polysilicon, and an insulating isolation structure is formed between the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure.

6. The planar SGOI SiGe HBT device according to claim 1, characterized in that: The substrate is a Si substrate with a crystal orientation of (100) and is doped with a P-type element with a doping concentration of 0.5×10 15 ~1.5×10 15 cm -3 .

7. The planar SGOI SiGe HBT device according to claim 1, characterized in that: The insulating layer is a SiO2 buried oxide layer.

8. A method for manufacturing a planar SGOI SiGe HBT device, characterized in that: Includes steps: providing a substrate on which an insulating layer is grown; Growing a sub-collector region of SiGe material on the insulating layer and performing N-type doping, growing a main collector region of SiGe material on the sub-collector region and performing N-type doping to form a SiGe collector region, wherein the N-type doping concentration of the sub-collector region is higher than the N-type doping concentration of the main collector region; Growing a SiGe base region at a SiGe base region window on the surface of the SiGe collector region; Growing Si material at the Si emitter window on the surface of the SiGe base region to form the Si emitter region; growing a first intrinsic SiGe layer and growing a compressively strained SiGe material in the SiGe base window to form a working SiGe base region; in the working SiGe base region, the Ge component is first uniformly distributed and then linearly reduced; forming a second intrinsic SiGe layer between the working SiGe base region and the Si emitter region, the Ge component of the first intrinsic SiGe layer being higher than the Ge component of the second intrinsic SiGe layer; An electrode lead-out window is grown on the surface of the main collector region to form a first electrode lead-out structure extending outward, an electrode lead-out window is grown on the surface of the SiGe base region to form a second electrode lead-out structure extending outward, and a third electrode lead-out structure is formed on the surface of the Si emitter region to extend outward, wherein the ends of the first electrode lead-out structure, the second electrode lead-out structure and the third electrode lead-out structure are located in the same plane.

9. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The step of growing a sub-collector region of SiGe material on the insulating layer and performing N-type doping, and growing a main collector region of SiGe material on the sub-collector region and performing N-type doping specifically includes: The sub-collector region of SiGe material is grown, the Ge component of the main collector region is 15%, and P element is doped with a doping concentration of 4.5×10 19 ~5.5×10 19 cm -3 The main collector region of SiGe material is grown on the sub-collector region and doped with P element with a doping concentration of 4.5×10 17 ~5.5×10 17 cm -3 .

10. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The step of growing a SiGe base region at a SiGe base region window on the surface of the SiGe collector region specifically includes: Depositing and growing a SiO2 layer on the surface of the SiGe collector region, and etching the SiO2 layer to form a SiGe base region window; The compressively strained SiGe material is grown to form a working SiGe base region, and B element is used for doping with a doping concentration of 1.5×10 19 ~2.5×10 19 cm -3 .

11. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The step of depositing Si material at the Si emitter window on the surface of the SiGe base region to form the Si emitter region specifically includes: A tensile strained Si material is deposited on the surface of the SiGe base region and doped with P element at a doping concentration of 0.8×10 18 ~1.2×10 18 cm -3 , etching to form the Si emitter region.

12. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: After growing a sub-collector region of SiGe material on the insulating layer and performing an N-type doping step, the method further includes: Depositing an isolation layer, etching to expose the contact area between the surface of the SiGe collector region and the first electrode lead-out structure, and performing P ion implantation; The deposited isolation layer is etched.

13. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The electrode lead-out window on the surface of the main collector region is grown to form a first electrode lead-out structure extending outward, the electrode lead-out window on the surface of the SiGe base region is grown to form a second electrode lead-out structure extending outward, and the third electrode lead-out structure extending outward is formed on the surface of the Si emitter region, specifically comprising: Depositing an isolation layer, and etching to expose electrode lead-out windows of the SiGe collector region and the Si emitter region; Depositing N-type doped polysilicon, and etching away the N-type doped polysilicon except for the electrode lead-out windows of the SiGe collector region and the Si emitter region; Depositing an isolation layer, and etching to expose electrode lead-out windows of the SiGe collector region and the Si emitter region; Depositing P-type doped polysilicon, and etching away the P-type doped polysilicon except for the SiGe base electrode lead-out window; Metal is sputtered on the surface of the N-type doped polysilicon and the P-type doped polysilicon to form the first electrode lead-out structure, the second electrode lead-out structure, and the third electrode lead-out structure.

14. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The providing of a substrate and growing an insulating layer on the substrate specifically includes: Provide a Si substrate with a crystal orientation of (100) and dope it with P element at a doping concentration of 0.5×10 15 cm -3 ~1.5×10 15 cm -3 .

15. The method for manufacturing a planar SGOI SiGe HBT device according to claim 8, characterized in that: The growing of the insulating layer on the substrate specifically comprises: A SiO2 buried oxide layer is grown on the substrate to form an insulating layer.

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