Parallel interface signal transmission method based on configurable state signal and related equipment

Abstract

The present invention provides a parallel interface signal transmission method based on configurable state signals and related equipment, the method comprising: determining the read and write operation timings of multiple protocols based on timing specification information in preset multiple protocol technical documents, and determining the level switching state of each protocol signal in the read and write operation timings based on the logic function information of multiple protocol signals in the corresponding protocol technical documents; setting the clock lengths of multiple protocol signals when they are in the corresponding configuration states according to the read and write operation timings; setting the level of multiple protocol signals when they are in the corresponding configuration states according to the level switching state; determining the target protocol type corresponding to the target device accessed by the parallel interface; sending a parallel bus signal based on the clock length and level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface, thereby being able to support a variety of different protocol standards and achieve effective compatibility and support for different devices.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of information technology, and in particular to a parallel interface signal transmission method based on a configurable state signal and related equipment. Background Art

[0002] With the rapid development of information technology, the communication methods between embedded systems and computer hardware are becoming more and more diverse. As a traditional data transmission method, parallel interface still plays an irreplaceable role in many application scenarios due to its simple and direct characteristics. However, the signal transmission method of traditional parallel interface is often limited to specific protocol standards, which leads to the need to customize different hardware interfaces when facing different types of devices, increasing development costs and complexity.

[0003] Existing parallel interface signal transmission methods usually only support one or several fixed protocols, such as Intel8080 (I8080) and Motorola6800 (6800) standard protocols. These protocols specify signal timing and level switching characteristics, but in actual applications, different devices may require different timing configurations and level switching strategies to adapt to specific working environments. In addition, when the system needs to support new devices or protocols, it is often necessary to modify the hardware design, which not only increases costs, but also prolongs the time to market for the product. Summary of the invention

[0004] The embodiment of the present invention provides a parallel interface signal transmission method based on configurable state signals and related devices. The method can support a variety of different protocol standards by flexibly configuring the timing and level switching state of the signal, thereby achieving effective compatibility and support for different devices.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present invention provides a parallel interface signal transmission method based on a configurable state signal, the method is applied to a control unit, the control unit is connected to a parallel interface, the method includes: determining the read and write operation timing of multiple protocols based on the timing specification information in a preset plurality of protocol technical documents, and determining the level switching state of each of the protocol signals in the read and write operation timing based on the logical function information of the plurality of protocol signals in the corresponding protocol technical documents; setting the clock length of the plurality of protocol signals when they are in the corresponding configuration state according to the read and write operation timing; setting the level of the plurality of protocol signals when they are in the corresponding configuration state according to the level switching state; determining the target protocol type corresponding to the target device connected to the parallel interface; sending a parallel bus signal based on the clock length and the level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface; wherein the configuration state includes a preprocessing state, a first state, a waiting state and a second state.

[0006] In some embodiments, the preprocessing state is used for initialization preparation of the signal; the first state is used for one level switching of the signal; the waiting state is used for the waiting period of the signal between two level switchings; and the second state is used for another level switching of the signal.

[0007] In some embodiments, the parallel bus signal includes multiple target protocol signals corresponding to the target protocol type, and the sending of the parallel bus signal based on the clock length and the level corresponding to the target protocol type includes: controlling the multiple target protocol signals to switch between the multiple configuration states based on the clock length and the level corresponding to each configuration state to send the parallel bus signal.

[0008] In some embodiments, the control of the multiple target protocol signals to switch between the multiple configuration states based on the clock length and the level corresponding to each configuration state also includes: in the case of triggering a burst access, based on a preset access configuration length, controlling the multiple target protocol signals to switch between the waiting state and the second state until the access length corresponding to the target protocol signal reaches the access configuration length to exit the burst access state.

[0009] In some embodiments, the plurality of target protocol signals include a chip select signal, an address valid signal, a write valid signal, a read valid signal, an address / data signal, and an address signal, and the parallel bus signal further includes a clock signal.

[0010] In some embodiments, when the target protocol type is an I8080 parallel interface, the control of the multiple target protocol signals to switch between the multiple configuration states based on the clock length and the level corresponding to each configuration state includes: the clock length of the chip select signal in the preprocessing state is set to 0, the clock length of the first state is set to 9, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0; the levels are set to 1-0-1-1 respectively; the clock length of the address valid signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 5 ; The levels are set to 1-0-1-1 respectively; the clock length of the write valid signal in the preprocessing state is set to 1, the clock length of the first state is set to 2, the clock length of the waiting state is set to 2, and the clock length of the second state is set to 2; the levels are set to 1-0-1-0 respectively; the clock length of the address signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 1; the clock length of the address / data signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0.

[0011] In some embodiments, when the target protocol type is a 6800 parallel interface, the target protocol signals are switched between the multiple configuration states based on the clock length and the level corresponding to each configuration state, including: the clock length of the chip select signal in the preprocessing state is set to 0, the clock length of the first state is set to 11, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0; the levels are set to 1-0-1-1 respectively; the clock length of the address valid signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 7; the levels are set to 1-0-1-1 respectively; the clock length of the write valid signal in the preprocessing state is set to 1, the clock length of the first state is set to 1 ... The clock length of the state is set to 10, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0; the levels are set to 1-0-1-1 respectively; the clock length of the read valid signal in the preprocessing state is set to 1, the clock length of the first state is set to 2, the clock length of the waiting state is set to 2, and the clock length of the second state is set to 2; the levels are set to 0-1-0-1 respectively; the clock length of the address signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 1; the clock length of the address / data signal in the preprocessing state is set to 1, the clock length of the first state is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0.

[0012] To achieve the above-mentioned purpose, the second aspect of an embodiment of the present invention proposes a parallel interface module based on a configurable state signal, the parallel interface module comprising: a controller, used to determine the read and write operation timing of multiple protocols based on the timing specification information in a preset plurality of protocol technical documents, and determine the level switching state of each of the protocol signals in the read and write operation timing based on the logical function information of the plurality of protocol signals in the corresponding protocol technical documents; set the clock length of the plurality of protocol signals when they are in the corresponding configuration state according to the read and write operation timing; set the level of the plurality of protocol signals when they are in the corresponding configuration state according to the level switching state; determine the target protocol type corresponding to the target device connected to the parallel interface; send a parallel bus signal based on the clock length and the level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface; a parallel interface, used to connect to the target device; wherein the configuration state includes a preprocessing state, a first state, a waiting state and a second state.

[0013] To achieve the above-mentioned purpose, the third aspect of an embodiment of the present invention proposes a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are used to execute the parallel interface signal transmission method based on configurable status signals as described in any embodiment of the first aspect.

[0014] To achieve the above-mentioned purpose, a fourth aspect of an embodiment of the present invention provides a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the parallel interface signal transmission method based on a configurable state signal as described in any one of the embodiments of the first aspect.

[0015] The parallel interface signal transmission method based on configurable status signals and related devices provided by the embodiment of the present invention, when applied to embedded systems or other scenarios requiring flexible parallel interfaces, can highly customize the configuration status of the signal through a controller to ensure effective compatibility with different devices and protocols. Specifically, the scheme of the present invention determines the read and write operation timings of multiple protocols based on the timing specification information in multiple preset protocol technical documents through a controller, and determines the level switching state of each protocol signal in the read and write operation timings based on the logical function information of multiple protocol signals in the corresponding protocol technical documents; sets the clock length of multiple protocol signals when they are in the corresponding configuration state according to the read and write operation timing; sets the level of multiple protocol signals when they are in the corresponding configuration state according to the level switching state; determines the target protocol type corresponding to the target device accessed by the parallel interface, and based on the target protocol type Corresponding clock lengths and levels are used to send parallel bus signals to manage the states of the signals, which include but are not limited to a preprocessing state, a first state, a waiting state, and a second state. Each state corresponds to a different level configuration of the signal, such as a high level or a low level, and a signal flip, etc. The controller can dynamically change the state of the signal according to the requirements of the external device or the internal configuration of the system to adapt to different communication environments; in summary, it can be understood that due to the high configurability of the configuration state of the signal, the scheme of the present invention can customize the configuration state of the signal, and can flexibly control the level flipping of the signal according to the requirements of different hardware protocols, thereby adapting to different communication environments and equipment requirements. By defining four states of the signal and switching these states as needed, the transmission timing of the signal can be more accurately controlled, the generation of erroneous signals can be reduced, and the accuracy of data transmission can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a parallel interface signal transmission method based on a configurable state signal provided by an embodiment of the present invention;

[0017] Figure 2 Another flow chart of a parallel interface signal transmission method based on a configurable state signal provided by an embodiment of the present invention;

[0018] Figure 3 Another flow chart of a parallel interface signal transmission method based on a configurable state signal provided by an embodiment of the present invention;

[0019] Figure 4 A signal diagram is provided for an embodiment of the present invention when the target protocol type is an I8080 parallel interface;

[0020] Figure 5 An example is provided for an embodiment of the present invention in which the target protocol type is a 6800 parallel interface. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] In some embodiments, although the functional modules are divided in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms first, second, etc. in the specification, claims and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0023] In addition, unless otherwise clearly specified and limited, the term "connected" should be understood in a broad sense. For example, it can be a fixed connection or a movable connection, a detachable connection or a non-detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or the two can communicate with each other; it can be a direct connection or an indirect connection through an intermediate medium.

[0024] In the description of the embodiments of the present invention, the description with reference to the terms "one embodiment / implementation", "another embodiment / implementation" or "certain embodiments / implementations", "in the above embodiments / implementations", etc. means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least two embodiments or implementations disclosed in the present invention. In the disclosure of the present invention, the schematic representation of the above terms does not necessarily refer to the same embodiment or implementation. It should be noted that although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that in the flowchart.

[0025] With the rapid development of information technology, the communication methods between embedded systems and computer hardware are becoming more and more diverse. As a traditional data transmission method, parallel interface still plays an irreplaceable role in many application scenarios due to its simple and direct characteristics. However, the signal transmission method of traditional parallel interface is often limited to specific protocol standards, which leads to the need to customize different hardware interfaces when facing different types of devices, increasing development costs and complexity. Existing parallel interface signal transmission methods usually only support one or several fixed protocols, such as standard protocols such as Intel8080 (I8080) and Motorola6800 (6800). These protocols specify characteristics such as signal timing and level switching, but in actual applications, different devices may require different timing configurations and level switching strategies to adapt to specific working environments. In addition, when the system needs to support new devices or protocols, it is often necessary to modify the hardware design, which not only increases costs but also prolongs the time to market of the product.

[0026] Based on this, an embodiment of the present invention provides a parallel interface signal transmission method and related equipment based on a configurable status signal. The method can support a variety of different protocol standards by flexibly configuring the timing and level switching status of the signal, thereby achieving effective compatibility and support for different devices.

[0027] The scheme of the present invention will be further described below in conjunction with the accompanying drawings.

[0028] refer to Figure 1 The embodiment of the present invention provides a parallel interface signal transmission method based on a configurable state signal, the method is applied to a control unit, the control unit is connected to a parallel interface, and the method includes the following steps:

[0029] Step S110, determining the read and write operation timings of multiple protocols based on the timing specification information in the preset multiple protocol technical documents, and determining the level switching state of each protocol signal in the read and write operation timings based on the logic function information of multiple protocol signals in the corresponding protocol technical documents;

[0030] Step S120, setting the clock lengths of the multiple protocol signals when they are in corresponding configuration states according to the read and write operation timings;

[0031] Step S130, setting the levels of the plurality of protocol signals when they are in corresponding configuration states according to the level switching state;

[0032] Step S140, determining the target protocol type corresponding to the target device accessed by the parallel interface;

[0033] Step S150, sending a parallel bus signal based on the clock length and level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface;

[0034] Among them, the configuration state includes a preprocessing state, a first state, a waiting state and a second state. When applied to embedded systems or other scenarios requiring a flexible parallel interface, the configuration state of the signal can be highly customized through the controller to ensure effective compatibility with different devices and protocols. It can be understood that due to the high configurability of the configuration state of the signal, the scheme of the present invention can customize the configuration state of the signal, and can flexibly control the level flipping of the signal according to the requirements of different hardware protocols, thereby adapting to different communication environments and equipment requirements. By defining four states of the signal and switching these states as needed, the transmission timing of the signal can be more accurately controlled, the generation of error signals can be reduced, and the accuracy of data transmission can be improved.

[0035] In some embodiments, program specification information refers to the timing of signal read and write operations specified in different protocols, including when to perform read and write operations and the duration of the signal; logical function information refers to the role and function of each signal during read and write operations. For example, a signal may represent that the address is valid during a read operation and that the data is valid during a write operation. Based on the above information, the level switching state of the signal under different read and write operation timings is determined, such as switching from a high level to a low level; clock length refers to the duration of a signal in a certain configuration state, that is, the length of time the signal is maintained in a specific state.

[0036] In some embodiments, the level refers to the level value of the signal when it is in a specific configuration state, such as a high level (1) or a low level (0). The target protocol type refers to the communication protocol type used by the target device connected to the parallel interface, such as I8080 or 6800, etc. The parallel bus signal refers to the signal set according to the target protocol type and configuration state. After the clock length and level values ​​are determined in steps S120 and S130, these signals are transmitted to the target device through the parallel interface.

[0037] In some embodiments, the pre-processing state is used for initialization preparation of the signal; the first state is used for a level switch of the signal; the waiting state is used for the waiting period between two level switches of the signal; the second state is used for another level switch of the signal. Specifically, the pre-processing state (PRE) is used for the initialization preparation stage of the signal to ensure that the signal is in an appropriate initial state, the first state (PHA0) is used for a level switch of the signal, which can occur at the beginning of a read or write operation, the waiting state (WAIT) is used for the waiting period between two level switches of the signal to ensure that the signal has enough stable time, and the second state (PHA1) is used for another level switch of the signal, which can occur at the end of a read or write operation. By defining these four states and switching these states as needed, the transmission timing of the signal can be more accurately controlled, the generation of error signals can be reduced, and the accuracy of data transmission can be improved. For example, under the I8080 protocol, the clock length and level of different signals in different states are precisely configured to ensure compatibility with the protocol, thereby achieving effective adaptation to different communication environments and equipment requirements.

[0038] refer to Figure 2 In some embodiments, the parallel bus signal includes a plurality of target protocol signals corresponding to the target protocol type, and sending the parallel bus signal based on the clock length and level corresponding to the target protocol type includes the following steps:

[0039] Step S210 , controlling a plurality of target protocol signals to switch between a plurality of configuration states based on the clock length and level corresponding to each configuration state, so as to send a parallel bus signal.

[0040] In some embodiments, the target protocol signal refers to a signal corresponding to the target protocol type (for example, I8080 or 6800). Multiple target protocol signals include a chip select signal (NCS), an address valid signal (NADV), a write valid signal (NWE), a read valid signal (NOE), an address / data signal (A / D[15:0]), and an address signal (ADDR[9:0]). The parallel bus signal also includes a clock signal (CLK). The pre-processing state (PRE), the first state (PHA0), the wait state (WAIT), and the second state (PHA1) define the behavior of the signal under different read and write operation sequences. The clock length refers to the duration of the signal in a certain configuration state, that is, the length of time the signal is maintained in a specific state.

[0041] It can be understood that by defining four states of the signal (pre-processing state, first state, waiting state and second state), and controlling the clock length and level of the signal according to these states, effective adaptation to different communication environments and equipment requirements is achieved. Specifically, by dynamically adjusting the state of the signal, the transmission timing of the signal can be more accurately controlled, the generation of error signals can be reduced, and the accuracy of data transmission can be improved. For example, under different protocols, the clock length and level of different signals in different states have different configurations to ensure the compatibility of the scheme of the present invention with different protocols.

[0042] refer to Figure 3 In some embodiments, multiple target protocol signals are controlled to switch between multiple configuration states based on the clock length and level corresponding to each configuration state, and further include:

[0043] Step S310, when a burst access is triggered, based on a preset access configuration length, multiple target protocol signals are controlled to switch between a waiting state and a second state until the access length corresponding to the target protocol signal reaches the access configuration length to exit the burst access state.

[0044] Among them, before entering the burst access, it is necessary to complete the pre-processing state, which is the initialization preparation stage of signal transmission to ensure that all signals are in the correct initial state. In the pre-processing state, each signal will be configured according to the preset clock length and level to ensure the correct start of signal transmission; further, when burst access is required, the system will trigger this special access mode according to the preset access configuration length (burstlength). The access configuration length refers to the number of times or amount of data transmitted continuously. During the burst access, the control system will control multiple target protocol signals to switch between the waiting state (WAIT) and the second state (PHA1) according to the preset access configuration length. The target protocol signals include but are not limited to the chip select signal (NCS), the address valid signal (NADV), the write valid signal (NWE), the read valid signal (NOE), the address / data signal (A / D[15:0]), and the address signal (ADDR[9:0]). At each switch, the signal will switch from the waiting state (WAIT) to the second state (PHA1), and then return to the waiting state (WAIT) again until the predetermined access length is completed. When the access length corresponding to the target protocol signal reaches the preset access configuration length, the system will exit the burst access state. After exiting the burst access state, the system will return to the normal signal transmission mode and continue to transmit signals according to the preset timing specification information and level switching state.

[0045] It can be understood that the scheme of the present invention provides a highly configurable signal state management mechanism by defining four states of the signal. The clock length and level of the signal are controlled according to these states, so that effective adaptation to different communication environments and equipment requirements can be achieved. Therefore, in the burst access mode, the system can efficiently and continuously transmit multiple groups of data, and the continuity and accuracy of data transmission are ensured by controlling the switching of the signal between the waiting state (WAIT) and the second state (PHA1).

[0046] refer to Figure 4 In some embodiments, when the target protocol type is an I8080 parallel interface, multiple target protocol signals are controlled to switch between multiple configuration states based on the clock length and level of each configuration state, including: the clock length of the chip select signal in the preprocessing state is set to 0, the clock length of the first state CS_PHA0 is set to 9, the clock length of the waiting state is set to 0, the clock length of the second state is set to 0, and the levels are set to 1-0-1-1 respectively; the clock length of the address valid signal in the preprocessing state NADV_PRE is set to 1, the clock length of the first state NADV_PHA0 is set to 3, the clock length of the waiting state is set to 0, the clock length of the second state NADV_PHA1 is set to 5, and the levels are set to 1-0-1-1 respectively; the clock length of the write valid signal in the preprocessing state NWE_PRE is set to 1, the clock length of the first state NADV_PHA0 is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state NADV_PHA1 is set to 5, and the levels are set to 1-0-1-1 respectively. The clock length of NWE_PHA0 is set to 2, the clock length of the waiting state NADV_WAIT is set to 2, the clock length of the second state NADV_PHA1 is set to 2, and the levels are set to 1-0-1-0 respectively; in the address / data signal, ADDR represents the address access stage, WDAT represents the write data stage, and when performing an address access operation, the clock length in the preprocessing state ADDR_PRE is set to 1, the clock length of the first state ADDR_PHA0 is set to 3, the clock length of the wait state is set to 0, and the clock length of the second state ADDR_PHA1 is set to 1. When the address / data signal performs a write data operation, the clock length in the preprocessing state DATA_PRE is set to 1, the clock length of the first state DATA_PHA0 is set to 3, the clock length of the wait state is set to 0, and the clock length of the second state is set to 0.

[0047] Among them, the levels of the address signal (ADDR[9:0]) and the address / data signal (A / D[15:0]) in the first state are set to 0 or 1 depending on the address valid signals NADV and NADV. In addition, it is worth noting that the parallel interface in the present application is a parallel bus interface, and the parallel bus interface is provided with address signal lines and address / data signal lines at the same time, so that when transmitting parallel bus signals, the target device can choose to use the A / D[15:0] or ADDR[9:0] address bus according to needs, so as to be compatible with devices using different address buses.

[0048] In some embodiments, the clock length of the address valid signal (NADV) in the first state (PHA0) is set to 3, which helps to ensure the correct transmission of address information, and the clock length of the write valid signal (NWE) in the first state (PHA0) is set to 2, while the clock lengths in the wait state (WAIT) and the second state (PHA1) are both 2, which helps to speed up the write operation and improve data transmission efficiency.

[0049] It can be understood that, through the above configuration, the scheme of the present invention can effectively control the state of the signal, ensure compatibility with the I8080 parallel interface standard, improve the accuracy and efficiency of data transmission, reduce the generation of error signals, and improve the flexibility and compatibility of the system.

[0050] refer to Figure 5In some embodiments, when the target protocol type is a 6800 parallel interface, multiple target protocol signals are controlled to switch between multiple configuration states based on the clock length and level of each configuration state, including: the clock length of the chip select signal in the preprocessing state is set to 0, the clock length of the first state CS_PHA0 is set to 11, the clock length of the waiting state is set to 0, the clock length of the second state is set to 0, and the levels are set to 1-0-1-1 respectively; the clock length of the address valid signal in the preprocessing state NADV_PRE is set to 1, the clock length of the first state NADV_PHA0 is set to 3, the clock length of the waiting state is set to 0, the clock length of the second state NADV_PHA1 is set to 7, and the levels are set to 1-0-1-1 respectively; the clock length of the write valid signal in the preprocessing state NWE_PRE is set to 1, the clock length of the first state NWE_PHA0 is set to 10, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0, the levels are set to 1-0-1-1 respectively; the clock length of the read valid signal in the preprocessing state NOE_PRE is set to 1, the clock length of the first state NOE_PHA0 is set to 2, the clock length of the waiting state NOE_WAIT is set to 2, and the clock length of the second state NOE_PHA1 is set to 2, and the levels are set to 0-1-0-1 respectively; in the address / data signal, ADDR represents the address access stage, WDAT represents the write data stage, when performing the address access operation, the clock length in the preprocessing state ADDR_PRE is set to 1, the clock length of the first state ADDR_PHA0 is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state ADDR_PHA1 is set to 1, when the address / data signal performs the write data operation, the clock length in the preprocessing state DATA_PRE is set to 1, the clock length of the first state DATA_PHA0 is set to 3, the clock length of the waiting state is set to 0, and the clock length of the second state is set to 0.

[0051] In some embodiments, the clock length of the address valid signal (NADV) in the first state (PHA0) is set to 3, which helps to ensure the correct transmission of address information, and the clock length of the write valid signal (NWE) in the first state (PHA0) is set to 10. Such a setting helps to speed up the write operation and improve the data transmission efficiency. It can be understood that through the above configuration, the scheme of the present invention can effectively control the state of the signal, ensure compatibility with the 6800 parallel interface standard, improve the accuracy and efficiency of data transmission, reduce the generation of error signals, and improve the flexibility and compatibility of the system.

[0052] It is worth noting that the parallel interface signal transmission method based on configurable status signals and related devices provided by the embodiment of the present invention, when applied to embedded systems or other scenarios requiring flexible parallel interfaces, can dynamically change the state of the signal according to the requirements of external devices or the internal configuration of the system to adapt to different communication environments. That is, through software-level configuration, the signal level flipping can be flexibly controlled according to the requirements of different hardware protocols, thereby adapting to different communication environments and equipment requirements, avoiding the need to modify the hardware design when supporting new devices or protocols, thereby simplifying the system integration process.

[0053] An embodiment of the present invention also provides a parallel interface module based on a configurable state signal, the parallel interface module comprising: a controller, used to determine the read and write operation timing of multiple protocols based on the timing specification information in multiple preset protocol technical documents, and determine the level switching state of each protocol signal in the read and write operation timing based on the logical function information of multiple protocol signals in the corresponding protocol technical documents; set the clock length of multiple protocol signals when they are in the corresponding configuration state according to the read and write operation timing; set the level of multiple protocol signals when they are in the corresponding configuration state according to the level switching state; determine the target protocol type corresponding to the target device connected to the parallel interface; send a parallel bus signal based on the clock length and level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface; a parallel interface, used to connect to the target device; wherein the configuration state includes a preprocessing state, a first state, a waiting state, and a second state.

[0054] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the above-mentioned parallel interface signal transmission method based on configurable status signals, so that the above-mentioned one or more processors can execute the parallel interface signal transmission method based on configurable status signals of any one of the above-mentioned embodiments.

[0055] The embodiment of the present invention further provides a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the parallel interface signal transmission method based on a configurable state signal according to any one of the above embodiments.

[0056] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network nodes. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0057] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer-readable storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD to ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0058] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A parallel interface signal transmission method based on a configurable state signal, characterized in that: The method is applied to a control unit, the control unit is connected to a parallel interface, and the method comprises: Determine the read and write operation timings of multiple protocols based on the timing specification information in the preset multiple protocol technical documents, and determine the level switching state of each of the protocol signals in the read and write operation timings based on the logic function information of multiple protocol signals in the corresponding protocol technical documents; According to the read and write operation timing, set the clock lengths when the plurality of protocol signals are in corresponding configuration states; According to the level switching state, the levels of the plurality of protocol signals when in the corresponding configuration state are set; Determine the target protocol type corresponding to the target device accessed by the parallel interface; Sending a parallel bus signal based on the clock length and the level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface; Wherein, the configuration state includes a pre-processing state, a first state, a waiting state, and a second state; The parallel bus signal includes the multiple target protocol signals corresponding to the target protocol type, and the sending of the parallel bus signal based on the clock length and the level corresponding to the target protocol type includes: Based on the clock length and the level corresponding to each of the configuration states, the target protocol signals are controlled to switch between the configuration states respectively, so as to send the parallel bus signal; Wherein, the controlling of the plurality of target protocol signals to switch between the plurality of configuration states respectively based on the clock length and the level corresponding to each configuration state further includes: In the case of triggering a burst access, based on a preset access configuration length, a plurality of the target protocol signals are controlled to switch between the waiting state and the second state until the access length corresponding to the target protocol signal reaches the access configuration length to exit the burst access state.

2. The parallel interface signal transmission method according to claim 1, characterized in that: The pre-processing state is used for initialization preparation of the signal; the first state is used for one level switching of the signal; the waiting state is used for the waiting period of the signal between two level switchings; and the second state is used for another level switching of the signal.

3. The parallel interface signal transmission method according to claim 1, characterized in that: The plurality of target protocol signals include a chip select signal, an address valid signal, a write valid signal, a read valid signal, an address / data signal, and an address signal, and the parallel bus signal also includes a clock signal.

4. The parallel interface signal transmission method according to claim 3, characterized in that: In the case where the target protocol type is an I8080 parallel interface, the controlling of the plurality of target protocol signals to switch between the plurality of configuration states based on the clock length and the level corresponding to each configuration state includes: The clock length of the chip select signal in the pre-processing state is set to 0, the clock length in the first state is set to 9, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 0; the levels are set to 1-0-1-1 respectively; The clock length of the address valid signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 5; the levels are set to 1-0-1-1 respectively; The clock length of the write valid signal in the pre-processing state is set to 1, the clock length in the first state is set to 2, the clock length in the waiting state is set to 2, and the clock length in the second state is set to 2; the levels are set to 1-0-1-0 respectively; The clock length of the address signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 1; The clock length of the address / data signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 0.

5. The parallel interface signal transmission method according to claim 3, characterized in that: In the case where the target protocol type is a 6800 parallel interface, the controlling of the plurality of target protocol signals to switch between the plurality of configuration states based on the clock length and the level corresponding to each configuration state includes: The clock length of the chip select signal in the pre-processing state is set to 0, the clock length in the first state is set to 11, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 0; the levels are set to 1-0-1-1 respectively; The clock length of the address valid signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 7; the levels are set to 1-0-1-1 respectively; The clock length of the write valid signal in the pre-processing state is set to 1, the clock length in the first state is set to 10, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 0; the levels are set to 1-0-1-1 respectively; The clock length of the read valid signal in the pre-processing state is set to 1, the clock length in the first state is set to 2, the clock length in the waiting state is set to 2, and the clock length in the second state is set to 2; the levels are set to 0-1-0-1 respectively; The clock length of the address signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 1; The clock length of the address / data signal in the pre-processing state is set to 1, the clock length in the first state is set to 3, the clock length in the waiting state is set to 0, and the clock length in the second state is set to 0.

6. A parallel interface module based on configurable status signals, characterized in that: The parallel interface module comprises: A controller, used to determine the read and write operation timings of multiple protocols based on the timing specification information in the preset multiple protocol technical documents, and determine the level switching state of each of the protocol signals in the read and write operation timings based on the logic function information of the multiple protocol signals in the corresponding protocol technical documents; set the clock lengths of the multiple protocol signals when they are in the corresponding configuration states according to the read and write operation timings; set the level of the multiple protocol signals when they are in the corresponding configuration states according to the level switching state; determine the target protocol type corresponding to the target device connected to the parallel interface; send a parallel bus signal based on the clock length and the level corresponding to the target protocol type, so that the parallel bus signal is transmitted to the target device through the parallel interface; A parallel interface for connecting to the target device; wherein the configuration state includes a pre-processing state, a first state, a waiting state and a second state; The parallel bus signal includes the multiple target protocol signals corresponding to the target protocol type, and the sending of the parallel bus signal based on the clock length and the level corresponding to the target protocol type includes: Based on the clock length and the level corresponding to each of the configuration states, the target protocol signals are controlled to switch between the configuration states respectively, so as to send the parallel bus signal; Wherein, the controlling of the plurality of target protocol signals to switch between the plurality of configuration states respectively based on the clock length and the level corresponding to each configuration state further includes: In the case of triggering a burst access, based on a preset access configuration length, a plurality of the target protocol signals are controlled to switch between the waiting state and the second state until the access length corresponding to the target protocol signal reaches the access configuration length to exit the burst access state.

7. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the parallel interface signal transmission method based on configurable status signals according to any one of claims 1 to 5.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the parallel interface signal transmission method based on a configurable state signal according to any one of claims 1 to 5 is implemented.

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