LDMOSFET device and manufacturing method

Abstract

The present invention relates to the field of semiconductor technology, and provides an LDMOSFET device and a manufacturing method. The device comprises: a substrate, and a body region, a drift region, a source region, a drain region and a gate structure formed on the substrate. The source region comprises a lateral source region and a longitudinal source region, the lateral source region is buried at the bottom of the body region, and the longitudinal source region extends to the bottom of the body region and connects with the lateral source region. The gate structure comprises a lateral gate, a longitudinal gate, a first oxide layer and a second oxide layer, the lateral gate and the second oxide layer are located above the body region and the drift region, the lateral gate and the second oxide layer are connected to form a lateral gate structure, and the lateral gate structure also serves as a field plate structure; the longitudinal gate is connected to the lateral gate, the longitudinal gate and the first oxide layer are embedded in the body region, the first oxide layer is connected to the longitudinal source region, and the longitudinal gate and the first oxide layer are connected to form a longitudinal gate structure. The LDMOSFET device of the present invention improves the breakdown voltage and reduces the on-resistance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an LDMOSFET device and a manufacturing method thereof. Background Art

[0002] LDMOSFET (Lateral Double-diffused MOSFET) is a typical power MOS device with the characteristics of high input impedance, simple driving, fast switching speed, etc. LDMOSFET is a high-voltage and high-current device, which is widely used in various electronic products as part of the power management circuit.

[0003] The breakdown voltage (Breakdown Voltage, BV) and specific on-resistance (Specific on-resistance, Rsp) of LDMOSFET devices are important indicators. In practical applications, LDMOSFET devices with high breakdown voltage and low on-resistance are required. In the prior art, the source region of the LDMOSFET device is designed on the surface of the body region, the gate is above the source region, and the field plate is below the gate. The field plate is used to reduce the surface electric field of the device, thereby increasing the breakdown voltage. The field plate structure is usually formed by using the Local Oxidation of Silicon (LOCOS) technology and the Shallow Trench Isolation (STI) technology.

[0004] In the prior art, in order to increase the breakdown voltage, the thickness of the field plate needs to be increased. However, when the device is working, the current flows from the source end to the drain along the lower surface of the field plate. The thicker the field plate, the longer the outflow path of the current from the source to the drain, and the greater the on-resistance, making it difficult to obtain a lower on-resistance at a higher breakdown voltage. Summary of the invention

[0005] In order to improve the above technical defects, the present invention provides an LDMOSFET device and a manufacturing method.

[0006] In one aspect, the present invention provides an LDMOSFET device, comprising: a substrate and a body region, a drift region, a source region, a drain region and a gate structure formed on the substrate, wherein the source region comprises a lateral source region and a longitudinal source region, the lateral source region is buried at the bottom of the body region, and the longitudinal source region extends to the bottom of the body region and connects to the lateral source region;

[0007] The gate structure includes a transverse gate, a longitudinal gate, a first oxide layer and a second oxide layer;

[0008] The lateral gate and the second oxide layer are located above the body region and the drift region, the lateral gate and the second oxide layer are connected to form a lateral gate structure, and the lateral gate structure also serves as a field plate structure;

[0009] The longitudinal gate is connected to the transverse gate, the longitudinal gate and the first oxide layer are embedded in the body region, the first oxide layer is connected to the longitudinal source region, and the longitudinal gate and the first oxide layer are connected to form a longitudinal gate structure.

[0010] In the embodiment of the present invention, both sides of the longitudinal source region are provided with a first oxide layer and a longitudinal gate, and the longitudinal gates on both sides share the longitudinal source region and the transverse source region.

[0011] In an embodiment of the present invention, the drain region is located on a surface of an end of the drift region away from the source region.

[0012] In the embodiment of the present invention, the lower end of the longitudinal source region is connected to the lateral source region, and the upper end of the longitudinal source region is connected to the metal electrode of the source.

[0013] In an embodiment of the present invention, the LDMOSFET device further includes: a well region formed on the substrate, the well region is longitudinally connected to the drift region, and the well region is transversely connected to the body region.

[0014] Another aspect of the present invention provides a method for manufacturing an LDMOSFET device, comprising:

[0015] S201, performing ion implantation on the substrate surface to form a lateral source region;

[0016] S202, forming an epitaxial layer on the surface of the substrate having the lateral source region;

[0017] S203, performing ion implantation on the surface of the substrate having the epitaxial layer to form a body region and a drift region, so that the lateral source region is buried at the bottom of the body region;

[0018] S204, performing high energy ion implantation in the body region to form a longitudinal source region connected to the lateral source region;

[0019] S205, forming a second oxide layer on the surface of the substrate having the lateral source region and the longitudinal source region;

[0020] S206, etching the body region to form deep trenches on both sides of the longitudinal source region, wherein the deep trenches expose a portion of the surface of the lateral source region;

[0021] S207, forming a first oxide layer on the inner wall of the deep trench, depositing polysilicon on the substrate surface and in the deep trench, forming a lateral gate and a longitudinal gate connected to the lateral gate.

[0022] In an embodiment of the present invention, the step of performing ion implantation on the surface of the substrate having the epitaxial layer to form the body region and the drift region includes:

[0023] Perform photolithography on the surface of the epitaxial layer to form pattern windows of the well region, body region and drift region;

[0024] Ion implantation is performed in the graphic windows to form a well region, a body region and a drift region.

[0025] In an embodiment of the present invention, the step of performing high energy ion implantation in the body region to form a longitudinal source region connected to the lateral source region includes:

[0026] A thick layer of SiO2 is thermally oxidized on the surface of the substrate having the body region and the drift region, and a photoresist is coated on the surface of the SiO2. An ion implantation window is formed by photolithography, and a large-dose, high-energy ion implantation method is used to implant N-type ions into the window and then push the junction to form a vertical source region connected to the lateral source region.

[0027] In an embodiment of the present invention, the step of forming a second oxide layer on the surface of the substrate having the lateral source region and the longitudinal source region includes:

[0028] A thin SiO2 layer is thermally oxidized on the surface of the substrate having the lateral source region and the longitudinal source region, and then a thick SiO2 layer is deposited, and the thick SiO2 is dry-etched to form a second oxide layer.

[0029] In an embodiment of the present invention, etching the body region to form deep trenches on both sides of the vertical source region includes:

[0030] A dry etching method is adopted to perform deep etching from the surface of the body region along the two sides of the longitudinal source region, so as to form two deep trenches on the two sides of the longitudinal source region.

[0031] In an embodiment of the present invention, the step of forming a first oxide layer on the inner wall of the deep trench, depositing polysilicon on the substrate surface and in the deep trench, and forming a lateral gate and a vertical gate includes:

[0032] Thermal oxidation is performed on the inner wall of the deep trench to form a first oxide layer, and low-pressure chemical vapor deposition is used to deposit N-type heavily doped polysilicon on the substrate surface and in the deep trench. The polysilicon on the substrate surface is dry-etched to form lateral gates and vertical gates.

[0033] In an embodiment of the present invention, the method further includes:

[0034] N-type heavily doped ions are implanted into the surface of one end of the drift region away from the source region, followed by annealing to form a drain region.

[0035] In an embodiment of the present invention, the method further includes:

[0036] A thick layer of SiO2 is deposited on the surface of the substrate with the lateral gate and the vertical gate as an insulating layer, and the insulating layer is dry-etched to form a plurality of contact holes. Metal is deposited in the contact holes and on the surface of the substrate, and the metal is dry-etched to form metal electrodes connected to the vertical source region, the lateral gate, and the drain region, respectively.

[0037] In the above technical solution, the lateral gate structure composed of the lateral gate and the second oxide layer is also used as a field plate structure, which can improve the breakdown voltage. The source region is buried at the bottom of the body region, and the vertical gate and the first oxide layer are embedded in the body region and connected to the source region to form a vertical gate structure. The present invention uses a horizontal and vertical dual-gate structure, and a conduction channel can be formed between the lateral gate and the drift region, and a conduction channel can also be formed between the vertical gate and the drift region, which further improves the breakdown voltage and reduces the on-resistance.

[0038] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0040] Figure 1 is a schematic structural diagram of an LDMOSFET device provided by an embodiment of the present invention;

[0041] Figure 2 is a flow chart of a method for manufacturing an LDMOSFET device provided by an embodiment of the present invention;

[0042] Figure 3a It is a schematic structural diagram of a lateral source region formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0043] Figure 3b It is a schematic structural diagram of an epitaxial layer formed in the LDMOSFET device manufacturing method provided in an embodiment of the present invention;

[0044] Figure 3c It is a structural schematic diagram of a well region, a body region and a drift region formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0045] Figure 3d It is a schematic structural diagram of a longitudinal source region formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0046] Figure 3e is a schematic structural diagram of a second oxide layer formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0047] Figure 3f It is a schematic structural diagram of a deep trench formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0048] Figure 3g is a schematic structural diagram of a first oxide layer formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0049] Figure 3h It is a schematic structural diagram of a lateral gate and a longitudinal gate formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention;

[0050] Figure 3i It is a schematic structural diagram of a drain region and a metal electrode formed in a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention.

[0051] Description of Reference Numerals

[0052] 101-substrate, 102-well region, 103-body region, 104-drift region,

[0053] 105a-lateral source region, 105b-vertical source region, 106a-lateral gate, 106b-vertical gate,

[0054] 107a-first oxide layer, 107b-second oxide layer, 108-drain region, 109-metal electrode,

[0055] 110 - insulating layer, 111 - epitaxial layer. DETAILED DESCRIPTION

[0056] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0057] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0058] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0059] In the process of realizing the present invention, the inventors found that the source region of the LDMOSFET device is designed on the surface of the body region, the gate is above the source region, and the field plate is below the gate. In order to increase the breakdown voltage, it is necessary to increase the thickness of the field plate. However, when the device is working, the current flows from the source end along the lower surface of the field plate to the drain. The thicker the field plate, the longer the outflow path of the current from the source to the drain, and the larger the on-resistance, making it difficult to obtain a lower on-resistance at a higher breakdown voltage.

[0060] In view of the above problems, an embodiment of the present invention provides an LDMOSFET device, including: a substrate and a body region, a drift region, a source region, a drain region and a gate structure formed on the substrate. The source region includes a lateral source region and a longitudinal source region, the lateral source region is buried at the bottom of the body region, and the longitudinal source region extends to the bottom of the body region and connects with the lateral source region. The gate structure includes a lateral gate, a longitudinal gate, a first oxide layer and a second oxide layer, the lateral gate and the second oxide layer are located above the body region and the drift region, the lateral gate and the second oxide layer are connected to form a lateral gate structure, and the lateral gate structure also serves as a field plate structure; the longitudinal gate is connected to the lateral gate, the longitudinal gate and the first oxide layer are embedded in the body region, the first oxide layer is connected to the longitudinal source region, and the longitudinal gate is connected to the first oxide layer to form a longitudinal gate structure.

[0061] The lateral gate structure composed of the lateral gate and the second oxide layer in the present invention is also used as a field plate structure, which can improve the breakdown voltage. The source region of the present invention is buried at the bottom of the body region, and the vertical gate and the first oxide layer are embedded in the body region and connected to the source region to form a vertical gate structure. Through the horizontal and vertical double gate structure, a conduction channel can be formed between the lateral gate and the drift region, and a conduction channel can also be formed between the vertical gate and the drift region, further improving the breakdown voltage and reducing the on-resistance.

[0062] Figure 1 Schematic diagram of the structure of the LDMOSFET device provided by the embodiment of the present invention. Figure 1 As shown, the LDMOSFET device provided in this embodiment includes: a substrate 101 and a well region 102, a body region 103, a drift region 104, a source region, a drain region 108 and a gate structure formed on the substrate 101. The well region 102 is connected to the drift region 104 vertically, the well region 102 is connected to the body region 103 horizontally, and the body region 103 is connected to the drift region 104 vertically. The drain region 108 is located on the surface of the end of the drift region 104 away from the source region. The source region includes a lateral source region 105a and a longitudinal source region 105b, the lateral source region 105a is buried in the bottom of the body region 103, and the longitudinal source region 105b extends to the bottom of the body region 103 and connects to the lateral source region 105a. The gate structure includes a lateral gate 106a, a longitudinal gate 106b, a first oxide layer 107a and a second oxide layer 107b. The lateral gate 106a and the second oxide layer 107b are located above the body region 103 and the drift region 104. The lateral gate 106a and the second oxide layer 107b are connected to form a lateral gate structure, and the lateral gate structure also serves as a field plate structure; the longitudinal gate 106b is connected to the lateral gate 106a, and the longitudinal gate 106b and the first oxide layer 107a are embedded in the body region 103, the first oxide layer 107a is connected to the longitudinal source region 105b, and the longitudinal gate 106b and the first oxide layer 107a are connected to form a longitudinal gate structure.

[0063] In this embodiment, there are first oxide layers 107a and longitudinal gates 106b on both sides of the longitudinal source region 105b, and the longitudinal gates 106b on both sides share the longitudinal source region 105b and the transverse source region 105a, and the longitudinal source region 105b and the transverse source region 105a serve as a whole source region. Figure 1 The left and right sides of the source region are divided into an LDMOSFET structure, the right side is a complete LDMOSFET structure, and the left side shows only a part of the LDMOSFET structure. The LDMOSFET structure on the left and the LDMOSFET structure on the right share the source region.

[0064] In this embodiment, the lower end of the longitudinal source region 105b is connected to the lateral source region 105a, and the upper end of the longitudinal source region 105b is connected to the metal electrode 109 of the source. The lateral gates 106a on both sides of the longitudinal source region 105b are respectively connected to the metal electrodes 109 of the gate, and the drain region 108 is connected to the metal electrode 109 of the drain. Different metal electrodes 109 are separated by an insulating layer 110.

[0065] In this embodiment, the longitudinal gate is inserted into the body region to form a longitudinal gate connection structure, and the transverse gate and the oxide layer below it serve as a transverse gate structure and also as a field plate structure, which can increase the breakdown voltage. The transverse gate and the longitudinal gate are connected, and a conduction channel can be formed between the transverse gate and the drift region, and a conduction channel can also be formed between the longitudinal gate and the drift region, further increasing the breakdown voltage. Since the threshold voltages of the transverse gate and the longitudinal gate can be made different (different ion implantation concentrations result in different threshold voltages), there can be two different threshold voltages when the device is turned on, the transverse threshold voltage is higher, and the longitudinal threshold voltage is lower, which can make the longitudinal direction turn on first, and the longitudinal on-resistance is very low; since the transverse conduction channel length is shorter, the on-resistance is also relatively low. Although the overall channel length of the device has become longer, the longitudinal on-resistance is very low, and the transverse conduction channel is short and the on-resistance is also low, so the overall on-resistance of the device is reduced.

[0066] Figure 2 FIG. 1 is a flow chart of a method for manufacturing an LDMOSFET device according to an embodiment of the present invention. Figure 2 As shown, the manufacturing method of the LDMOSFET device provided in this embodiment includes the following steps:

[0067] S201, performing ion implantation on the substrate surface to form a lateral source region;

[0068] S202, forming an epitaxial layer on the surface of the substrate having the lateral source region;

[0069] S203, performing ion implantation on the surface of the substrate having the epitaxial layer to form a body region and a drift region, so that the lateral source region is buried at the bottom of the body region;

[0070] S204, performing high energy ion implantation in the body region to form a longitudinal source region connected to the lateral source region;

[0071] S205, forming a second oxide layer on the surface of the substrate having the lateral source region and the longitudinal source region;

[0072] S206, etching the body region to form deep trenches on both sides of the longitudinal source region, wherein the deep trenches expose a portion of the surface of the lateral source region;

[0073] S207, forming a first oxide layer on the inner wall of the deep trench, depositing polysilicon on the substrate surface and in the deep trench, forming a lateral gate and a longitudinal gate connected to the lateral gate.

[0074] The following combination Figures 3a to 3i , taking an N-type LDMOSFET device as an example, the above manufacturing method is explained in detail.

[0075] In the above step S201, a P-type doped silicon wafer is selected as a substrate, a thick layer of SiO2 is thermally oxidized on the surface of the substrate, and then a photoresist is coated and an etching window is formed by photolithography, SiO2 is dry-etched, and then heavily doped N-type ions are implanted to form a lateral source region 105a; after removing the photoresist, annealing is performed, and SiO2 is wet-removed to form a lateral source region 105a. Figure 3a The structure shown.

[0076] In the above step S202, a P-type doped epitaxial layer 111 is formed on the surface of the substrate having the lateral source region 105a, forming Figure 3b The structure shown.

[0077] In the above step S203, a thick layer of SiO2 is thermally oxidized on the surface of the epitaxial layer, and pattern windows of the well region, body region and drift region are formed by photolithography. N-type ion implantation, P-type ion implantation and N-type ion implantation are performed in the pattern windows of the well region, body region and drift region respectively to form the following: Figure 3c The N-type well region 102 , the P-type body region 103 and the N-type drift region 104 are shown.

[0078] In the above step S204, Figure 3c The surface of the structure shown in the figure is thermally oxidized by CVD (chemical vapor deposition) to form a thick layer of SiO2, and then coated with photoresist. The ion implantation window is formed by photolithography. N-type ions are implanted into the window by high-dose, high-energy ion implantation. The photoresist is removed, and the junction (including N-type well region 102, P-type body region 103, and N-type drift region 104) is pushed together. Then, the surface SiO2 is removed to form the structure shown in the figure. Figure 3d The longitudinal source region 105b is shown.

[0079] In the above step S205, Figure 3d The structure shown in the figure is thermally oxidized with a thin layer of SiO2, and then CVD (Chemical Vapor Deposition) is used to deposit a thick layer of SiO2. Then, photolithography and dry etching of the thick SiO2 are performed to form a structure as shown in the figure. Figure 3e The second oxide layer 107b is shown.

[0080] In the above step S206, a dry etching method is used to perform deep etching from the surface of the P-type body region 103 along both sides of the longitudinal source region 105b to form two deep trenches on both sides of the longitudinal source region. Figure 3f The structure shown.

[0081] In the above step S207, thermal oxidation is performed on the inner walls of the two deep trenches to form Figure 3g The first oxide layer 107a is shown. Then, low-pressure chemical vapor deposition (LPCVD) is used to deposit N-type heavily doped polysilicon on the substrate surface and in the deep trench. The polysilicon on the substrate surface is chemically mechanically polished, and then the polysilicon on the substrate surface is dry-etched to form Figure 3h The transverse grid 106a and the longitudinal grid 106b are shown.

[0082] After step S207, N-type heavily doped ions are implanted on the surface of the end of the N-type drift region 104 away from the source region, and annealing is performed to form a Figure 3i Next, a layer of SiO2 is deposited by CVD (chemical vapor deposition) to form a plurality of contact holes as an insulating layer 110, and metal is deposited by PVD (physical vapor deposition) and dry-etched to form metal electrodes 109 connected to the vertical source region 105b, the horizontal gate 106a, and the drain region 108, respectively, as shown in FIG. Figure 3i The structure shown.

[0083] The lateral gate structure formed by the lateral gate and the second oxide layer formed in the method can also serve as a field plate structure to increase the breakdown voltage. The lateral source region and the longitudinal source region are buried at the bottom of the body region, and the longitudinal gate and the first oxide layer are embedded in the body region and connected to the source region to form a longitudinal gate structure. The method forms a lateral and longitudinal dual-gate structure, a longitudinal conduction channel can be formed between the lateral gate and the drift region, and a lateral conduction channel can be formed between the longitudinal gate and the drift region, thereby increasing the overall length of the channel and reducing the on-resistance.

[0084] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An LDMOSFET device, comprising: A substrate and a body region, a drift region, a source region, a drain region and a gate structure formed on the substrate, characterized in that the source region includes a lateral source region and a longitudinal source region, the lateral source region is buried at the bottom of the body region, and the longitudinal source region extends to the bottom of the body region and connects with the lateral source region; The gate structure includes a transverse gate, a longitudinal gate, a first oxide layer and a second oxide layer; The lateral gate and the second oxide layer are located above the body region and the drift region, the lateral gate and the second oxide layer are connected to form a lateral gate structure, and the lateral gate structure also serves as a field plate structure; The vertical gate is connected to the horizontal gate, the vertical gate and the first oxide layer are embedded in the body region, the first oxide layer is connected to the vertical source region, and the vertical gate is connected to the first oxide layer to form a vertical gate structure; There are first oxide layers and longitudinal gates on both sides of the longitudinal source region, and the longitudinal gates on both sides share the longitudinal source region and the transverse source region; the drain region is located on the surface of the drift region away from the source region; the lower end of the longitudinal source region is connected to the transverse source region, and the upper end of the longitudinal source region is connected to the metal electrode of the source.

2. The LDMOSFET device according to claim 1, characterized in that: Also includes: a well region formed on the substrate; The well region is connected to the drift region in a longitudinal direction, and the well region is connected to the body region in a transverse direction.

3. A method for manufacturing an LDMOSFET device, characterized in that: include: Ion implantation is performed on the substrate surface to form a lateral source region; forming an epitaxial layer on a surface of a substrate having a lateral source region; Ion implantation is performed on the surface of the substrate having the epitaxial layer to form a body region and a drift region, so that the lateral source region is buried at the bottom of the body region; High energy ion implantation is performed in the body region to form a longitudinal source region connected to the lateral source region; forming a second oxide layer on the surface of the substrate having the lateral source region and the longitudinal source region; Etching the body region to form deep trenches on both sides of the longitudinal source region, wherein the deep trenches expose a portion of the surface of the lateral source region; A first oxide layer is formed on the inner wall of the deep trench, and polysilicon is deposited on the substrate surface and in the deep trench to form a lateral gate and a longitudinal gate connected to the lateral gate.

4. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The step of performing ion implantation on the surface of the substrate having the epitaxial layer to form a body region and a drift region comprises: Perform photolithography on the surface of the epitaxial layer to form pattern windows of the well region, body region and drift region; Ion implantation is performed in the graphic windows to form a well region, a body region and a drift region.

5. The method for manufacturing an LDMOSFET device according to claim 4, characterized in that: The high energy ion implantation is performed in the body region to form a longitudinal source region connected to the lateral source region, including: A layer of silicon oxide is formed by thermal oxidation on the surface of the substrate having the body region and the drift region, and a photoresist is coated on the silicon oxide surface. An ion implantation window is formed by photolithography, and N-type ions are injected into the window and then a junction is pushed to form a vertical source region connected to the lateral source region.

6. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The forming of a second oxide layer on the surface of the substrate having the lateral source region and the longitudinal source region comprises: A layer of silicon oxide is formed by thermal oxidation on the surface of the substrate having the lateral source region and the longitudinal source region, and then another layer of silicon oxide is deposited. The deposited silicon oxide is etched to form a second oxide layer.

7. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The etching of the body region to form deep trenches on both sides of the vertical source region includes: A dry etching method is adopted to perform deep etching from the surface of the body region along the two sides of the longitudinal source region, so as to form two deep trenches on the two sides of the longitudinal source region.

8. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The method comprises forming a first oxide layer on the inner wall of the deep trench, depositing polysilicon on the substrate surface and in the deep trench, and forming a lateral gate and a vertical gate, including: Thermal oxidation is performed on the inner wall of the deep trench to form a first oxide layer, and low-pressure chemical vapor deposition is used to deposit N-type heavily doped polysilicon on the substrate surface and in the deep trench. The polysilicon on the substrate surface is dry-etched to form lateral gates and vertical gates.

9. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The method further comprises: N-type heavily doped ions are implanted into the surface of one end of the drift region away from the source region, followed by annealing to form a drain region.

10. The method for manufacturing an LDMOSFET device according to claim 3, characterized in that: The method further comprises: A layer of silicon oxide is deposited on the surface of the substrate with the lateral gate and the vertical gate as an insulating layer, and the insulating layer is dry-etched to form a plurality of contact holes. Metal is deposited in the contact holes and on the surface of the substrate, and the metal is dry-etched to form metal electrodes connected to the vertical source region, the lateral gate, and the drain region, respectively.

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