Extended drain MOS (Metal Oxide Semiconductor) device, manufacturing method and chip

Abstract

The invention relates to the field of semiconductors, and provides an extended drain MOS (Metal Oxide Semiconductor) device, a manufacturing method and a chip. The extended drain MOS device comprises a substrate, a P-type well region, an N-type deep well region, shallow trench isolation regions, a source region, a drain region and a grid electrode, the shallow trench isolation regions comprise a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region, the first shallow trench isolation region is located between the grid electrode and the drain region, the second shallow trench isolation region is located between the drain region and a substrate interface, and the third shallow trench isolation region is located between the source region and the drain region. The third shallow slot isolation region is located between the source region and the substrate interface; the N-type deep well region is located below the first shallow trench isolation region and the drain region, a second P-type well region is arranged in the N-type deep well region, and the second P-type well region is longitudinally connected with the first shallow trench isolation region. The N-type deep well region internally provided with the P-type well region is used as a drift region structure, the breakdown voltage and the safe working region of the device are improved, the manufacturing method of the device is completely compatible with the CMOS technology, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an extended drain MOS device and a manufacturing method and a chip. Background Art

[0002] EDMOS (Extended Drain Metal Oxide Semiconductor) devices have high breakdown voltage and driving capability and are widely used in power management, DC / AC converters and other chips. The important performance indicators of high-voltage EDMOS devices mainly include breakdown voltage and reliability. Reliability mainly includes indicators such as safe operating area and performance degradation caused by hot carrier injection (HCI).

[0003] In practical applications, many chips will use EDMOS, CMOS (Complementary Metal Oxide Semiconductor), LDMOS (Lateral Doublediffused MOSFET) and other devices at the same time. In the manufacturing process, the doping layer of EDMOS is usually common to that of CMOS and LDMOS to save costs. For chips that use NEDMOS (N-type EDMOS) and LDMOS at the same time, in the existing manufacturing technology, NDRF (N-drift) is used as the drift region of NEDMOS and NLDMOS, PW (P-well) or PDRF (P-drift) is used as the body region, and STI (shallow trench isolation) is used as the field plate. The drift region and field plate are used to increase the breakdown voltage of the device.

[0004] The existing NEDMOS uses NDRF as the drift region, and for chips that use high-voltage DMOS devices that use both EDMOS and LDMOS, the number of masking will not increase. However, for chips that use only high-voltage DMOS devices that use EDMOS, the NDRF mask must be added compared to the CMOS process, which wastes costs. Moreover, the NDRF drift region has a shallow injection depth and a high concentration, making it difficult to achieve a high breakdown voltage and a wide safe operating area. Therefore, it is necessary to separately design a NEDMOS device and manufacturing method that is fully compatible with the CMOS process. Summary of the invention

[0005] The present invention provides an extended drain MOS device structure to improve the breakdown voltage and safe operating area of ​​a NEDMOS device, and the manufacturing method corresponding to the structure is fully compatible with the CMOS process.

[0006] In one aspect, the present invention provides an extended drain MOS device, comprising: a substrate, a first P-type well region, an N-type deep well region, a shallow trench isolation region, a source region, a drain region and a gate, wherein the first P-type well region and the N-type deep well region are formed in the substrate, the source region and the drain region are formed on the surface of the substrate, the gate is formed above the substrate, and the substrate is provided with a substrate interface;

[0007] The shallow trench isolation region includes a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region;

[0008] The first shallow trench isolation region is located between the gate and the drain region;

[0009] The second shallow trench isolation region is located between the drain region and the substrate interface;

[0010] The third shallow trench isolation region is located between the source region and the substrate interface;

[0011] The N-type deep well region is located below the first shallow trench isolation region and the drain region, a second P-type well region is provided in the N-type deep well region, and the second P-type well region is longitudinally connected to the first shallow trench isolation region;

[0012] When current is applied to the gate, a depletion layer is formed at the interface between the second P-type well region and the N-type deep well region to extend the conduction path in the N-type deep well region.

[0013] In an embodiment of the present invention, the second P-type well region includes a plurality of mutually separated sub-segments;

[0014] When current is applied to the gate, a depletion layer is formed at the interface between each sub-segment of the second P-type well region and the N-type deep well region.

[0015] In the embodiment of the present invention, the length of the second shallow trench isolation region is greater than the length of the first shallow trench isolation region, and the length of the first shallow trench isolation region is greater than the length of the third shallow trench isolation region.

[0016] In the embodiment of the present invention, an N-type lightly doped diffusion region is disposed in the first P-type well region, and the N-type lightly doped diffusion region is laterally connected to the source region.

[0017] In the embodiment of the present invention, the two extended drain MOS devices share a same drain region, and the first shallow trench isolation region of one extended drain MOS device and the first shallow trench isolation region of the other extended drain MOS device are both connected to the drain region.

[0018] Another aspect of the present invention provides a method for manufacturing an extended drain MOS device, comprising:

[0019] forming an N-type deep well region in the substrate;

[0020] Forming a shallow trench isolation region on the surface of the substrate having the N-type deep well region, the shallow trench isolation region including a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region, the N-type deep well region being connected to the first shallow trench isolation region;

[0021] forming a first P-type well region below the third shallow trench isolation region, and forming a second P-type well region in the N-type deep well region below the first shallow trench isolation region;

[0022] forming a gate above the first P-type well region and the first shallow trench isolation region;

[0023] A source region and a substrate interface are formed on the surface of the first P-type well region, and a drain region is formed in the area between the first shallow trench isolation region and the second shallow trench isolation region, so that the source region is laterally connected to the substrate interface through the third shallow trench isolation region, the drain region is laterally connected to the substrate interface through the second shallow trench isolation region, and the drain region is vertically connected to the N-type deep well region.

[0024] In an embodiment of the present invention, forming an N-type deep well region in a substrate includes:

[0025] A photolithography process is used to form a pattern area of ​​an N-type deep well region on the surface of a P-type substrate, N-type ions are injected into the pattern area, and annealing is performed to form an N-type deep well region.

[0026] In an embodiment of the present invention, a shallow trench isolation region is formed on a substrate surface having an N-type deep well region, including:

[0027] A bottom oxide layer and silicon nitride are sequentially grown on the surface of a P-type substrate having an N-type deep well region;

[0028] Forming grooves by photolithography and etching processes;

[0029] The trench is filled with silicon dioxide, and the filled silicon dioxide is polished to form a shallow trench isolation region.

[0030] In an embodiment of the present invention, a first P-type well region is formed below the third shallow trench isolation region, and a second P-type well region is formed in the N-type deep well region below the first shallow trench isolation region, including: using a photolithography process to define the graphic areas of the first P-type well region and the second P-type well region, injecting P-type ions into the graphic areas, and performing annealing to form the first P-type well region and the second P-type well region.

[0031] In an embodiment of the present invention, a gate is formed above the first P-type well region and the first shallow trench isolation region, including: forming a gate oxide layer on the surface of the substrate having the first P-type well region and the first shallow trench isolation region, depositing a layer of polysilicon on the surface of the gate oxide layer, and etching to form a gate.

[0032] In the embodiment of the present invention, a source region and a substrate interface are formed on the surface of the first P-type well region, and a drain region is formed in the region between the first shallow trench isolation region and the second shallow trench isolation region, including:

[0033] Depositing a layer of oxide and a layer of silicon nitride on the substrate with the gate, and etching to form sidewalls on both sides of the gate;

[0034] By photolithography and development processing, the source region, drain region and substrate interface pattern area are defined;

[0035] Implanting N-type ions into the patterned regions of the source region and the drain region to form the source region and the drain region;

[0036] P-type ions are implanted into the graphic region of the substrate interface to form a substrate interface.

[0037] In an embodiment of the present invention, the method further includes:

[0038] After forming the first P-type well region, a pattern region of an N-type lightly doped diffusion region is defined on the surface of the first P-type well region by using a photolithography process, and N-type ions are implanted into the pattern region to form an N-type lightly doped diffusion region.

[0039] In the embodiment of the present invention, the N-type ion doping concentration in the N-type deep well region is 1×10 12 cm -2 ~8×10 12 cm -2 , the depth of the N-type deep well region is 3-8μm;

[0040] The P-type ion doping concentration of the first P-type well region and the second P-type well region is 2×10 12 cm -2 ~1×10 13 cm -2 , the depth of the first P-type well region and the second P-type well region is 0.7-1 μm.

[0041] The present invention also provides a chip, which includes the extended drain MOS device.

[0042] The N-type extended drain MOS device of the present invention forms an N-type deep well region below the shallow trench isolation region, forms a P-type well region in the N-type deep well region, and uses the N-type deep well region with the P-type well region inside as a new drift region structure. When a current is applied to the gate, a depletion layer is formed at the interface between the P-type well region and the N-type deep well region, which can extend the conduction path in the N-type deep well region, thereby improving the breakdown voltage and safe operating area of ​​the device. For a chip that only uses NEDMOS, the manufacturing of the chip adopts a CMOS process. The manufacturing method corresponding to the NEDMOS of the present invention with a new structure is fully compatible with the CMOS process, does not require an additional mask, and reduces the manufacturing cost.

[0043] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0045] Figure 1 is a schematic structural diagram of an extended drain MOS device provided in Embodiment 1 of the present invention;

[0046] Figure 2 is a schematic structural diagram of an extended drain MOS device provided in Embodiment 2 of the present invention;

[0047] Figure 3 is a schematic structural diagram of an extended drain MOS device provided in Embodiment 3 of the present invention;

[0048] Figure 4 is a flow chart of a method for manufacturing an extended drain MOS device provided by an embodiment of the present invention;

[0049] Figure 5a is a schematic structural diagram of an N-type deep well region formed in a manufacturing method provided in an embodiment of the present invention;

[0050] Figure 5b is a schematic structural diagram of a shallow trench isolation region formed in a manufacturing method provided in an embodiment of the present invention;

[0051] Figure 5c is a schematic structural diagram of a P-type well region formed in a manufacturing method provided in an embodiment of the present invention;

[0052] Figure 5d is a schematic structural diagram of a gate formed in a manufacturing method provided in an embodiment of the present invention;

[0053] Figure 5e It is a schematic structural diagram of a source region, a drain region and a substrate interface formed in a manufacturing method provided in an embodiment of the present invention.

[0054] Description of Reference Numerals

[0055] 10-substrate, 11a-first P-type well region, 11b-second P-type well region, 12-N-type deep well region,

[0056] 13-first shallow trench isolation region, 14-second shallow trench isolation region, 15-third shallow trench isolation region,

[0057] 16-source region, 17-drain region, 18-substrate interface, 19-N-type lightly doped diffusion region,

[0058] 20-gate, 21-gate oxide layer, 22-sidewall. DETAILED DESCRIPTION

[0059] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0060] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0061] In the present invention, unless otherwise clearly specified and limited, the terms such as "connected", "connected", "connected" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium, they can be the internal connection of two functional structural regions or the interaction relationship between two functional structural regions. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0062] As introduced in the background technology, the existing EDMOS (extended drain MOS device) uses NDRF (N-drift) as the drift region. For chips that use high-voltage DMOS devices that use both EDMOS and LDMOS, the number of masking will not increase. However, for chips that use only EDMOS high-voltage DMOS devices, the NDRF mask must be added compared to the CMOS process, which wastes costs. Moreover, the NDRF drift region has a shallow injection depth and a high concentration, making it difficult to achieve a higher breakdown voltage and a wider safe operating area.

[0063] In view of the above problems, an embodiment of the present invention provides an N-type extended drain MOS device (NEDMOS), which forms an N-type deep well region under a shallow trench isolation region (STI), forms a P-type well region inside the N-type deep well region, and uses the N-type deep well region with the P-type well region inside as a new drift region structure to improve the breakdown voltage and safe operating area of ​​the device. For a chip that only uses NEDMOS, the chip is manufactured using a CMOS process. The manufacturing method corresponding to the NEDMOS of the present invention with a new structure is fully compatible with the CMOS process, does not require an additional mask, and reduces the manufacturing cost.

[0064] Embodiment 1

[0065] Figure 1 Schematic diagram of the structure of the extended drain MOS device provided in the first embodiment of the present invention. Figure 1 As shown, the extended drain MOS device of this embodiment includes: a substrate 10, a first P-type well region 11a, an N-type deep well region 12, a shallow trench isolation region, a source region 16, a drain region 17 and a gate 20. The first P-type well region 11a and the N-type deep well region 12 are formed in the substrate 10, the source region 16 and the drain region 17 are formed on the surface of the substrate 10, the gate 20 is formed above the substrate 10, and the substrate is provided with a substrate interface 18. The shallow trench isolation region includes a first shallow trench isolation region 13, a second shallow trench isolation region 14 and a third shallow trench isolation region 15. The first shallow trench isolation region 13 is located between the gate 20 and the drain region 17, the second shallow trench isolation region 14 is located between the drain region 17 and the substrate interface 18, and the third shallow trench isolation region 15 is located between the source region 16 and the substrate interface 18. The substrate interface 18 on the right and the substrate interface 18 on the left are a ring, that is, an interface. The N-type deep well region 12 is located below the first shallow trench isolation region 13 and the drain region 17 . A second P-type well region 11 b is disposed in the N-type deep well region 12 . The second P-type well region 11 b is longitudinally connected to the first shallow trench isolation region 13 .

[0066] HNW (High voltage N-type well) is an ion implantation process that can be used to make floating CMOS (floating gate MOS) devices. The HNW implantation depth is deep, and after a long period of high temperature annealing, the concentration is lower and the diffusion is more uniform.

[0067] This embodiment adopts the HNW process to form an N-type deep well region (ie, a high-voltage N-well region). The N-type deep well region serves as a drift region of NEDMOS and is fully compatible with the CMOS process. NEDMOS can be formed without adding a mask.

[0068] This embodiment adopts the HNW process to implant high-energy, high-dose N-type ions into the segmented N-well area, and then activates the ions through a high-temperature annealing process and diffuses the ion concentration evenly. Therefore, the formed N-type deep well area has a deeper depth, a lighter concentration, and a more uniform distribution, which can significantly improve the performance of the NEDMOS device such as the breakdown voltage and the safe operating area, and improve reliability.

[0069] Due to the HNW process, a long annealing process is required to form an N-type deep well region. During the annealing process, the ion concentration in the middle of the N-type deep well region 12 (the area below the first shallow trench isolation area 13) will be relatively high, and the ion concentration around it will be relatively low. The withstand voltage of the middle area with high ion concentration is relatively poor, and the main pressure-bearing area of ​​the device is the central area of ​​the well area below the first shallow trench isolation area 13. If the ion concentration in this area is high, the conductivity is strong, and the withstand voltage performance is reduced. Therefore, in order to reduce the ion concentration in the middle area of ​​the N-type deep well region and improve the withstand voltage performance, a second P-type well region 11b is designed in the N-type deep well region 12. On the one hand, the ion concentration in the middle area of ​​the N-type deep well region can be reduced, and on the other hand, an inversion can be formed in the N-type deep well region to extend the conduction path. When current is applied to the gate, inversion electrons are generated in the second P-type well region 11b below the first shallow trench isolation region 13. The inversion electrons gather at the interface between the second P-type well region 11b and the N-type deep well region to form a depletion layer, extending the conduction path in the N-type deep well region 12 (carriers pass along the bottom of the second P-type well region 11b), reducing the conduction capability, and thus achieving the purpose of increasing the breakdown voltage.

[0070] In this embodiment, the length of the second shallow trench isolation region 14 is greater than the length of the first shallow trench isolation region 13, and the length of the first shallow trench isolation region 13 is greater than the length of the third shallow trench isolation region 15. Generally, LDMOS requires a lower on-resistance and does not increase the area occupied by the device, so the withstand voltage (breakdown voltage in the on state) is not high enough. However, EDMOS is based on the COMS process and improves the withstand voltage by extending the drain end. Since the performance requirements of EDMOS are different from those of LDMOS, EDMOS requires higher withstand voltage performance, so the withstand voltage is improved by the longer second shallow trench isolation region 14 between the drain region 17 and the substrate interface 18 (extending the drain end), and the third shallow trench isolation region 15 between the source region 16 and the substrate interface 18, thereby improving the breakdown voltage of the device.

[0071] In this embodiment, an N-type lightly doped drain (NLDD) is provided in the P-type well region 11, and the N-type lightly doped diffusion region 19 is laterally connected to the source region 16. The N-type lightly doped diffusion region 19 and the N-type heavily doped ions in the drain region 17 form a certain concentration gradient, which reduces the lateral electric field, thereby weakening the hot carrier HCI effect.

[0072] Embodiment 2

[0073] Figure 2 Schematic diagram of the structure of the extended drain MOS device provided by the second embodiment of the present invention. Figure 2 As shown, the extended drain MOS device of this embodiment includes: a substrate 10, a first P-type well region 11a, an N-type deep well region 12, a shallow trench isolation region, a source region 16, a drain region 17 and a gate 20. The first P-type well region 11a and the N-type deep well region 12 are formed in the substrate 10, the source region 16 and the drain region 17 are formed on the surface of the substrate 10, the gate 20 is formed above the substrate 10, and the substrate is provided with a substrate interface 18. The shallow trench isolation region includes a first shallow trench isolation region 13, a second shallow trench isolation region 14 and a third shallow trench isolation region 15. The first shallow trench isolation region 13 is located between the gate 20 and the drain region 17, the second shallow trench isolation region 14 is located between the drain region 17 and the substrate interface 18, and the third shallow trench isolation region 15 is located between the source region 16 and the substrate interface 18. The substrate interface 18 on the right and the substrate interface 18 on the left are a ring, that is, an interface. The N-type deep well region 12 is located below the first shallow trench isolation region 13 and the drain region 17 . A second P-type well region 11 b is disposed in the N-type deep well region 12 . The second P-type well region 11 b is longitudinally connected to the first shallow trench isolation region 13 .

[0074] This embodiment adopts the HNW process to form an N-type deep well region (ie, a high-voltage N-well region). The N-type deep well region serves as a drift region of NEDMOS and is fully compatible with the CMOS process. NEDMOS can be formed without adding a mask.

[0075] Due to the HNW process, a long annealing process is required to form an N-type deep well region. During the annealing process, the ion concentration in the middle of the N-type deep well region 12 (the area below the first shallow trench isolation area 13) will be relatively high, and the ion concentration around it will be relatively low. The withstand voltage of the middle area with high ion concentration is relatively poor, and the main pressure-bearing area of ​​the device is the central area of ​​the well area below the first shallow trench isolation area 13. If the ion concentration in this area is high, the conductivity is strong, and the withstand voltage performance is reduced. Therefore, in order to reduce the ion concentration in the middle area of ​​the N-type deep well region and improve the withstand voltage performance, a second P-type well region 11b is designed in the N-type deep well region 12. On the one hand, the ion concentration in the middle area of ​​the N-type deep well region can be reduced, and on the other hand, an inversion can be formed in the N-type deep well region to extend the conduction path. When current is applied to the gate, inversion electrons are generated in the second P-type well region 11b below the first shallow trench isolation region 13. The inversion electrons gather at the interface between the second P-type well region 11b and the N-type deep well region to form a depletion layer, extending the conduction path in the N-type deep well region 12 (carriers pass along the bottom of the second P-type well region 11b), reducing the conduction capability, and thus achieving the purpose of increasing the breakdown voltage.

[0076] Furthermore, the second P-type well region 11b includes a plurality of mutually separated sub-segments. After high-energy, high-dose P-type ions are implanted into the regions of each sub-segment and then subjected to a long period of high-temperature annealing, the gap regions between the sub-segments will also have diffused P-type doped ions, making the ion concentration distribution of the P-type well region uniform. In addition, when current is applied to the gate, each sub-segment of the second P-type well region forms a small area of ​​inversion at the interface with the N-type deep well region, avoiding the large P-type well region from forming a large area of ​​inversion, which would cause device failure.

[0077] In this embodiment, the length of the second shallow trench isolation region 14 is greater than that of the first shallow trench isolation region 13, and the length of the first shallow trench isolation region 13 is greater than that of the third shallow trench isolation region 15. Since EDMOS requires higher withstand voltage performance, the longer second shallow trench isolation region 14 between the drain region 17 and the substrate interface 18 (to extend the drain end) and the third shallow trench isolation region 15 between the source region 16 and the substrate interface 18 are used to increase the withstand voltage, thereby increasing the breakdown voltage of the device.

[0078] In this embodiment, an N-type lightly doped diffusion region is provided in the P-type well region 11, and the N-type lightly doped diffusion region 19 is laterally connected to the source region 16. The N-type lightly doped diffusion region 19 and the N-type heavily doped ions in the drain region 17 form a certain concentration gradient, which reduces the lateral electric field, thereby weakening the hot carrier HCI effect.

[0079] Embodiment 3

[0080] Figure 3 Schematic diagram of the structure of the extended drain MOS device provided by the third embodiment of the present invention. Figure 3 As shown, the extended drain MOS device of this embodiment includes: a substrate 10, a first P-type well region 11a, an N-type deep well region 12, a shallow trench isolation region, a source region 16, a drain region 17 and a gate 20. The P-type well region 11 and the N-type deep well region are formed in the substrate 10, the source region 16 and the drain region 17 are formed on the surface of the substrate 10, the gate 20 is formed above the substrate 10, and the substrate is provided with a substrate interface 18. The shallow trench isolation region includes a first shallow trench isolation region 13, a second shallow trench isolation region (not shown in the drawings) and a third shallow trench isolation region 15. The first shallow trench isolation region 13 is located between the gate 20 and the drain region 17, and the third shallow trench isolation region 15 is located between the source region 16 and the substrate interface 18. The substrate interface 18 on the right and the substrate interface 18 on the left are a ring, that is, an interface. The N-type deep well region 12 is located below the first shallow trench isolation region 13 and the drain region 17 . A second P-type well region 11 b is disposed in the N-type deep well region 12 . The second P-type well region 11 b is longitudinally connected to the first shallow trench isolation region 13 .

[0081] This embodiment adopts the HNW process to form an N-type deep well region (ie, a high-voltage N-well region). The N-type deep well region serves as a drift region of NEDMOS and is fully compatible with the CMOS process. NEDMOS can be formed without adding a mask.

[0082] Due to the HNW process, a long annealing process is required to form an N-type deep well region. During the annealing process, the ion concentration in the middle of the N-type deep well region 12 (the area below the first shallow trench isolation area 13) will be relatively high, and the ion concentration around it will be relatively low. The withstand voltage of the middle area with high ion concentration is relatively poor, and the main pressure-bearing area of ​​the device is the central area of ​​the well area below the first shallow trench isolation area 13. If the ion concentration in this area is high, the conductivity is strong, and the withstand voltage performance is reduced. Therefore, in order to reduce the ion concentration in the middle area of ​​the N-type deep well region and improve the withstand voltage performance, a second P-type well region 11b is designed in the N-type deep well region 12. On the one hand, the ion concentration in the middle area of ​​the N-type deep well region can be reduced, and on the other hand, an inversion can be formed in the N-type deep well region to extend the conduction path. When current is applied to the gate, inversion electrons are generated in the second P-type well region 11b below the first shallow trench isolation region 13. The inversion electrons gather at the interface between the second P-type well region 11b and the N-type deep well region to form a depletion layer, extending the conduction path in the N-type deep well region 12 (carriers pass along the bottom of the second P-type well region 11b), reducing the conduction capability, and thus achieving the purpose of increasing the breakdown voltage.

[0083] Since EDMOS devices are used for large drive and high load, multi-finger devices are required, that is, many single-finger EDMOS are connected in parallel. In order to save area, two adjacent EDMOS devices in the multi-finger structure share the same drain terminal. In this embodiment, two extended drain MOS devices share the same drain region 17, and the first shallow trench isolation region 13 of one extended drain MOS device and the first shallow trench isolation region 13 of the other extended drain MOS device are connected to the drain region 17. The two EDMOS share an N-type deep well region 12, and the two second P-type well regions 11b in the N-type deep well region 12 are respectively connected to the first shallow trench isolation regions 13 of the two EDMOS in a longitudinal direction.

[0084] Furthermore, in order to ensure the consistency of performance between single-finger devices and multi-finger devices, continue to improve the breakdown voltage and safe operating area of ​​multi-finger devices, and avoid the performance difference caused by different concentrations during the annealing process due to the different ion distribution environment around the deep well region at the drain end of the single-finger and multi-finger EDMOS, the second P-type well region 11b in the N-type deep well region 12 is divided into a plurality of mutually separated sub-segments. After high-energy, high-dose P-type ions are implanted into the regions of each sub-segment, and then after a long period of high-temperature annealing treatment, the gap regions between each sub-segment will also have diffused P-type doped ions, so that the ion concentration distribution of the P-type well region is uniform. In addition, when current is applied to the gate, each sub-segment of the second P-type well region forms a smaller area of ​​inversion at the interface with the N-type deep well region, avoiding the large P-type well region from forming too large an area of ​​inversion, which leads to device failure.

[0085] In this embodiment, an N-type lightly doped diffusion region is provided in the P-type well region 11, and the N-type lightly doped diffusion region 19 is laterally connected to the source region 16. The N-type lightly doped diffusion region 19 and the N-type heavily doped ions in the drain region 17 form a certain concentration gradient, which reduces the lateral electric field, thereby weakening the hot carrier HCI effect.

[0086] The embodiment of the present invention also provides a method for manufacturing the extended drain MOS device corresponding to the first embodiment. Figure 4 As shown, the method for manufacturing an extended drain MOS device according to an embodiment of the present invention comprises the following steps:

[0087] S401, forming an N-type deep well region in the substrate;

[0088] S402, forming a shallow trench isolation region on the surface of the substrate having the N-type deep well region, the shallow trench isolation region including a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region;

[0089] S403, forming a first P-type well region below the third shallow trench isolation region, and forming a second P-type well region in the N-type deep well region below the first shallow trench isolation region;

[0090] S404, forming a gate above the first P-type well region and the first shallow trench isolation region;

[0091] S405, forming a source region and a substrate interface on the surface of the first P-type well region, and forming a drain region in the region between the first shallow trench isolation region and the second shallow trench isolation region.

[0092] In a specific embodiment, in the above step S401, a P-type substrate is used, a sacrificial oxide layer is grown on the surface of the P-type substrate 10, and then a photolithography process is used to expose a pattern area of ​​an N-type deep well region on the surface of the P-type substrate 10, and high-energy, high-dose N-type ions are injected into the pattern area of ​​the N-type deep well region, and a long-term high-temperature annealing treatment is performed to make the ion concentration diffuse uniformly, and at the same time activate the doped N-type ions to form Figure 5a The N-type deep well region 12 is shown. The N-type ion doping concentration of the N-type deep well region is 1×10 12 cm -2 ~8×10 12 cm -2 , the maximum depth of the N-type deep well region (after annealing) is 3-8 μm. The length of the N-type deep well region is 2-3 μm. In the process of forming the N-type deep well region, the high temperature annealing process includes but is not limited to a high temperature furnace, a high temperature rapid thermal annealing (RTA), or a process combining a high temperature furnace and a high temperature rapid thermal annealing.

[0093] In a specific embodiment, in the above step S402, the sacrificial oxide layer on the surface of the P-type substrate is removed, and a bottom oxide layer and silicon nitride are sequentially grown on the surface of the P-type substrate, and then the trench and active area of ​​the shallow trench isolation (STI) are formed through photolithography and etching processes. The corners at the bottom and top of the STI are made smoother through the SiN pull back process and lining OX (not shown in the figure) to reduce the accumulation of sharp corner charges and reduce the tip electric field strength, thereby improving device reliability; then silicon dioxide is filled in the trench, and a high-temperature annealing treatment is performed to densify the silicon dioxide, and the filled silicon dioxide is polished using a chemical mechanical polishing process, and the height from the top of the shallow trench isolation area to the substrate surface is adjusted through a back etching process, and then the silicon nitride and bottom oxide layer are removed in turn to form a device such as Figure 5b The shallow trench isolation regions 13, 14, and 15 are shown. The N-type deep well region 12 is connected to the first shallow trench isolation region 13, and the gap region between the first shallow trench isolation region 13 and the second shallow trench isolation region 14 is used to form a subsequent drain region. In other embodiments, the above step S402 can be exchanged with the above step S401, that is, the shallow trench isolation region (STI) is first formed and then the N-type deep well region is formed.

[0094] In a specific embodiment, in the above step S403, a sacrificial oxide layer is grown on the surface of the P-type substrate to reduce the ion tunneling effect in the subsequent ion implantation process. The first P-type well region and the second P-type well region are defined by a photolithography process, and P-type ions are implanted in the graphic region. Several P-type ions with different energies and doses can be implanted into the region, and then a rapid annealing process is performed to activate the implanted ions, diffuse them evenly, and repair the damage, and then annealing is performed to form a structure such as Figure 5c The first P-type well region 11a and the second P-type well region 11b are shown. The first P-type well region 11a is connected to the third shallow trench isolation region 15. The second P-type well region 11b is located inside the N-type deep well region 12 and is connected to the bottom of the first shallow trench isolation region 13. The P-type ion doping concentration of the first P-type well region and the second P-type well region is 2×10 12 cm -2 ~1×10 13 cm -2 , the maximum depth of the first P-type well region and the second P-type well region is 0.7-1 μm.

[0095] In other embodiments, the second P-type well region 11 b in the N-type deep well region 12 can be divided into 2-10 sub-segments, the interval between two adjacent sub-segments is 0.3-1 μm, and the length of each sub-segment is greater than 0.3-1 μm.

[0096] After forming the P-type well region, a photolithography process is used to define a pattern region of an N-type lightly doped diffusion region on the surface of the first P-type well region 11a, and lightly doped N-type ions are injected into the pattern region. The concentration of the N-type ions is 1×10 13 cm -2 ~4×10 13 cm -2 , forming an N-type lightly doped diffusion region 19. The N-type lightly doped diffusion region and the subsequent drain end N-type heavy doping form a certain concentration gradient, and the lightly doped ions in the N-type lightly doped diffusion region reduce the lateral electric field, thereby weakening the hot carrier HCI effect.

[0097] In the above step S404, a gate oxide layer is grown on the surface of the substrate, the sacrificial oxide layer is removed by wet etching, and then a gate oxide layer of about 70-150 angstroms is grown in the furnace tube; then the double gate oxide area is defined by photolithography, and the first grown part of the gate oxide layer is removed by etching process; then a second gate oxide layer is grown in the furnace tube, with a thickness of about 20-50 angstroms, and the final gate oxide layer 21 is formed by two growths. A layer of polysilicon is deposited on the surface of the gate oxide layer 21 by chemical vapor deposition method, and then etched to form a gate oxide layer 21 as shown in FIG. Figure 5d The gate 20 is shown.

[0098] In a specific embodiment, in the above step S405, a layer of oxide and a layer of silicon nitride are respectively deposited on the substrate forming the gate by CVD method, and then etched to form sidewalls 22 on both sides of the gate 20. Then, photolithography and development are performed at the positions corresponding to the source region and the drain region to define the pattern areas of the source region, the drain region and the substrate interface (bulk); heavily doped N-type ions are implanted in the pattern areas of the source region and the drain region to form the following: Figure 5eThe source region 16 and the drain region 17 shown in FIG. 1 are formed by injecting heavily doped P-type ions into the graphic region of the substrate interface to form a Figure 5e The substrate interface 18 is shown. The source region 16 is laterally connected to the substrate interface 18 through the third shallow trench isolation region 15, and the third shallow trench isolation region 15 separates the source region 16 from the substrate interface 18; the drain region 17 is laterally connected to the substrate interface 18 through the second shallow trench isolation region 14, and the second shallow trench isolation region 14 separates the drain region 17 from the substrate interface 18; the drain region 17 is longitudinally connected to the N-type deep well region 12. The substrate interface (Bulk) is a ring, which is used to improve the grounding effect, enhance the isolation performance, reduce the influence of other devices on the device, reduce noise, etc.

[0099] An embodiment of the present invention further provides a chip, which includes the extended drain MOS device of the above embodiment.

[0100] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An extended drain MOS device, characterized in that: include: A substrate, a first P-type well region, an N-type deep well region, a shallow trench isolation region, a source region, a drain region and a gate, wherein the first P-type well region and the N-type deep well region are formed in the substrate, the source region and the drain region are formed on the surface of the substrate, the gate is formed above the substrate, and the substrate is provided with a substrate interface; The shallow trench isolation region includes a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region; The first shallow trench isolation region is located between the gate and the drain region; The second shallow trench isolation region is located between the drain region and the substrate interface; The third shallow trench isolation region is located between the source region and the substrate interface; The N-type deep well region is located below the first shallow trench isolation region and the drain region, a second P-type well region is provided in the N-type deep well region, and the second P-type well region is longitudinally connected to the first shallow trench isolation region; When current is applied to the gate, a depletion layer is formed at the interface between the second P-type well region and the N-type deep well region to extend the conduction path in the N-type deep well region.

2. The extended drain MOS device according to claim 1, characterized in that: The second P-type well region includes a plurality of mutually separated sub-segments; When current is applied to the gate, a depletion layer is formed at the interface between each sub-segment of the second P-type well region and the N-type deep well region.

3. The extended drain MOS device according to claim 1, characterized in that: The length of the second shallow trench isolation region is greater than that of the first shallow trench isolation region, and the length of the first shallow trench isolation region is greater than that of the third shallow trench isolation region.

4. The extended drain MOS device according to claim 1, characterized in that: An N-type lightly doped diffusion region is disposed in the first P-type well region, and the N-type lightly doped diffusion region is laterally connected to the source region.

5. The extended drain MOS device according to claim 1, characterized in that: The two extended drain MOS devices share a same drain region, and the first shallow trench isolation region of one extended drain MOS device and the first shallow trench isolation region of the other extended drain MOS device are both connected to the drain region.

6. A method for manufacturing an extended drain MOS device, characterized in that: include: forming an N-type deep well region in the substrate; Forming a shallow trench isolation region on the surface of the substrate having the N-type deep well region, the shallow trench isolation region including a first shallow trench isolation region, a second shallow trench isolation region and a third shallow trench isolation region, the N-type deep well region being connected to the first shallow trench isolation region; forming a first P-type well region below the third shallow trench isolation region, and forming a second P-type well region in the N-type deep well region below the first shallow trench isolation region; forming a gate above the first P-type well region and the first shallow trench isolation region; A source region and a substrate interface are formed on the surface of the first P-type well region, and a drain region is formed in the area between the first shallow trench isolation region and the second shallow trench isolation region, so that the source region is laterally connected to the substrate interface through the third shallow trench isolation region, the drain region is laterally connected to the substrate interface through the second shallow trench isolation region, and the drain region is vertically connected to the N-type deep well region.

7. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The method of forming a shallow trench isolation region on the surface of the substrate having the N-type deep well region comprises: A bottom oxide layer and silicon nitride are sequentially grown on the surface of a P-type substrate having an N-type deep well region; Forming grooves by photolithography and etching processes; The trench is filled with silicon dioxide, and the filled silicon dioxide is polished to form a shallow trench isolation region.

8. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The method of forming a first P-type well region below the third shallow trench isolation region and forming a second P-type well region in the N-type deep well region below the first shallow trench isolation region comprises: The first P-type well region and the second P-type well region are defined by photolithography, P-type ions are implanted into the graphic regions, and annealing is performed to form the first P-type well region and the second P-type well region.

9. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The step of forming a gate above the first P-type well region and the first shallow trench isolation region comprises: A gate oxide layer is formed on the surface of the substrate having the first P-type well region and the first shallow trench isolation region, and a layer of polysilicon is deposited on the surface of the gate oxide layer and etched to form a gate.

10. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The source region and the substrate interface are formed on the surface of the first P-type well region, and the drain region is formed in the region between the first shallow trench isolation region and the second shallow trench isolation region, including: Depositing a layer of oxide and a layer of silicon nitride on the substrate with the gate, and etching to form sidewalls on both sides of the gate; By photolithography and development processing, the source region, drain region and substrate interface pattern area are defined; Implanting N-type ions into the patterned regions of the source region and the drain region to form the source region and the drain region; P-type ions are implanted into the graphic region of the substrate interface to form a substrate interface.

11. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The method further comprises: After forming the first P-type well region, a pattern region of an N-type lightly doped diffusion region is defined on the surface of the first P-type well region by using a photolithography process, and N-type ions are implanted into the pattern region to form an N-type lightly doped diffusion region.

12. The method for manufacturing an extended drain MOS device according to claim 6, characterized in that: The N-type ion doping concentration of the N-type deep well region is 1×10 12 cm -2 ~8×10 12 cm -2 ; The depth of the N-type deep well region is 3-8 μm; The P-type ion doping concentration of the first P-type well region and the second P-type well region is 2×10 12 cm -2 ~1×10 13 cm -2 ; The depths of the first P-type well region and the second P-type well region are 0.7-1 μm.

13. A chip, characterized in that: The chip comprises the extended drain MOS device according to any one of claims 1-5.

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