MOSFET terminal structure and preparation method thereof

Abstract

The invention discloses a MOSFET terminal structure and a preparation method thereof, and relates to the field of semiconductor technology. The source trench of the invention intersects with the first cut-off trench, and the inner circle sidewall of the first cut-off trench contacts the P+ channel layer and the N+ layer. Without adding additional process steps, the inner circle sidewall of the first cut-off trench and the sidewall of the source trench simultaneously play the role of forming a conductive channel inversion layer, thereby reducing the on-resistance of the device in the on state.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOSFET terminal structure and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, MOSFET, as a commonly used power semiconductor, has replaced triode and become one of the most commonly used switching devices in the power semiconductor field.

[0003] During the decades of iteration of MOSFET, MOSFET terminal technology has always been a hot topic of research. Traditional MOSFET terminal technologies include field plates, field limiting rings, cut-off trenches, etc. Trench-type MOSFETs often use cut-off trenches as device terminals. The MOSFET terminal area often serves to increase the device's withstand voltage and has no contribution to the device's conduction capability. Summary of the invention

[0004] Aiming at the research and development direction of the MOSFET terminal area, the present invention provides a MOSFET terminal structure and a preparation method thereof, which can effectively play the role of improving the withstand voltage of the device while reducing the on-resistance of the device.

[0005] The technical solution of the present invention is:

[0006] The method for preparing a MOSFET terminal structure comprises the following steps:

[0007] Step S100, preparing a plurality of P+ channel layers and a plurality of N+ layers in the epitaxial wafer;

[0008] Step S200, preparing a plurality of source trenches and a plurality of stop trenches in the epitaxial wafer; the source trenches intersect with the inner stop trenches along the y-axis direction, and the inner circle sidewalls of the inner stop trenches are in contact with the P+ channel layer and the N+ layer respectively;

[0009] Step S300, preparing a gate dielectric and polysilicon in the source trench and the cut-off trench respectively;

[0010] Step S400, depositing an isolation layer on the epitaxial wafer, and opening windows at the N+ layer and the polysilicon in the source trench to prepare an S-pole electrode and a G-pole electrode respectively;

[0011] Step S500, preparing a D-pole electrode at the bottom of the epitaxial wafer, and the entire device is completed.

[0012] Specifically, step S100 includes:

[0013] Step S110, using a mask to protect the outer area of ​​the P+ channel layer through a photolithography process; using a diffusion process or an ion implantation process to form a plurality of P+ channel layers;

[0014] Step S120: Protect the outer area of ​​the N+ layer by using a mask through a photolithography process; and form a plurality of N+ layers by using a diffusion process or an ion implantation process.

[0015] Specifically, step S200 includes:

[0016] Step S210, using a mask to protect the source trench and the outer area of ​​the cut-off trench through a photolithography process;

[0017] Step S220, forming a source trench and a stop trench by etching process, wherein the source trench intersects with the stop trench along the y-axis direction, and the inner sidewall of the stop trench contacts the P+ channel layer and the N+ layer.

[0018] Specifically, step S300 includes:

[0019] Step S310, using a mask to protect the source trench and the outer region of the cutoff trench by a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric in the trench;

[0020] Step S320 , preparing polysilicon in the trench by chemical vapor deposition.

[0021] Specifically, the gate dielectric material is SiO2, and the thickness is set to 40-500nm.

[0022] Specifically, step S400 includes:

[0023] Step S410, preparing an isolation layer by chemical vapor deposition; and using a photolithography process, using a mask to protect the N+ layer and the polysilicon outside the source trench, and opening windows at the N+ layer and the polysilicon in the source trench by an etching process;

[0024] Step S420, preparing corresponding S-pole electrodes and G-pole electrodes at the polysilicon windows in the N+ layer and the source trench by a stripping process or an etching process.

[0025] Specifically, the isolation layer is made of SiO2 or Si3N4, and its thickness is set to 10-5000nm.

[0026] Specifically, step S500 includes:

[0027] Step S510, preparing a D-pole electrode at the bottom of the epitaxial wafer through a thinning process and a back-gold process, and the entire device is prepared.

[0028] The MOSFET terminal structure includes a D-pole electrode, an epitaxial wafer and an isolation layer arranged in sequence from bottom to top;

[0029] The epitaxial wafer is provided with:

[0030] There are several P+ channel layers, each extending downward from the top surface of the epitaxial wafer, and having a bottom surface higher than the bottom surface of the N-voltage-resistant layer;

[0031] The N+ layer is provided with a plurality of N+ layers, each extending downward from the top surface of the P+ channel layer and having a spacing with the bottom surface of the P+ channel layer;

[0032] A plurality of source trenches are provided, each extending downward from the top surface of the epitaxial wafer into the N-voltage-resistant layer, and the bottom surface of the source trenches is located between the bottom surface of the N-voltage-resistant layer and the bottom surface of the P+ channel layer;

[0033] There are several stop grooves, which are respectively located outside the source groove, extending downward from the top surface of the epitaxial wafer to the N-voltage-resistant layer, and the bottom surface of which is located between the bottom surface of the N-voltage-resistant layer and the bottom surface of the P+ channel layer; the source groove intersects with the inner stop groove along the y-axis direction, and the inner circle sidewalls of the inner stop groove are in contact with the P+ channel layer and the N+ layer respectively;

[0034] A plurality of gate dielectrics are provided, which are respectively arranged along the inner sidewalls of the corresponding stop trench and the inner sidewalls of the source trench; the gate dielectric in the source trench and the gate dielectric on the inner sidewall of the stop trench are respectively connected to the N+ layer, the P+ channel layer and the N-voltage-resistant layer;

[0035] There are several polysilicon layers, each of which is filled in the gate dielectric.

[0036] The isolation layer is provided with:

[0037] An S-pole electrode extending downward from the top surface of the isolation layer into the P+ channel layer;

[0038] The G-pole electrode extends downward from the top surface of the isolation layer into the polysilicon.

[0039] The epitaxial wafer includes an N+ substrate layer and an N-voltage-resistant layer connected from bottom to top;

[0040] The D-pole electrode extends downward from the bottom surface of the N+ substrate layer.

[0041] Beneficial effects of the present invention:

[0042] The present invention intersects the source trench with the first cut-off trench along the y-axis direction, and the inner sidewall of the first cut-off trench contacts the P+ channel layer and the N+ layer. Without adding additional process steps, the inner sidewall of the first cut-off trench and the sidewall of the source trench simultaneously play the role of forming a conductive channel inversion layer, thereby reducing the on-resistance of the device in the on state. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a process flow chart of the present invention;

[0044] Figure 2is a schematic diagram of the surface structure of the device of the present invention after step S200;

[0045] Figure 3 is a schematic diagram of the surface structure of the device of the present invention after step S400;

[0046] Figure 4 is a schematic diagram of the cross-sectional structure of the device of the present invention along x1 within the range of y1-y2 after step S400;

[0047] Figure 5 is a schematic diagram of the cross-sectional structure of the device of the present invention along y3 within the range of x1-x2 after step S400;

[0048] Figure 6 is a schematic diagram of the cross-sectional structure of the device of the present invention along y4 within the range of x1-x2 after step S400;

[0049] In the figure, 1 is the epitaxial wafer, 2 is the P+ channel layer, 3 is the N+ layer, 4 is the source trench, 5 is the first cutoff trench, 6 is the gate dielectric, 7 is polysilicon, 8 is the isolation layer, 9 is the S pole electrode, 10 is the G pole electrode, 11 is the D electrode, 12 is the N+ substrate layer, and 13 is the N- voltage-resistant layer. DETAILED DESCRIPTION

[0050] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0051] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] Reference below Figure 1-6 describe the invention;

[0053] MOSFET terminal structure and preparation method thereof, comprising the following steps:

[0054] Step S100, preparing a plurality of P+ channel layers 2 and a plurality of N+ layers 3 in the epitaxial wafer 1;

[0055] Step S110, using a mask to protect the outer area of ​​the P+ channel layer 2 through a photolithography process; using a diffusion process or an ion implantation process to form a plurality of P+ channel layers 2;

[0056] Step S120, using a mask to protect the outer area of ​​the N+ layer 3 through a photolithography process; using a diffusion process or an ion implantation process to form a plurality of N+ layers 3;

[0057] Correspondingly, the epitaxial wafer 1 is an N-type epitaxial wafer, which is composed of an N+ substrate layer 12 and an N-voltage-resistant layer 13 from bottom to top. The thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the N+ substrate layer 12 is 90-1500um, the thickness of the N-voltage-resistant layer 13 is 10-500um, the thickness of the P+ channel layer 2 is 1-5um, the thickness of the N+ layer 3 is 0.5-3um, and the doping concentration range of the N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device;

[0058] In this embodiment, the thickness of the epitaxial wafer 1 is 350um, the thickness of the N+ substrate layer 12 is 330um, and the doping concentration is 1e 19 .cm -3 , the thickness of N-voltage-resistant layer 13 is 20um, and the doping concentration is 1e 16 .cm -3 , the thickness of P+ channel layer 2 is 2um, and the doping concentration is 3e 18 .cm -3 , the thickness of N+ layer 3 is 1um, and the doping concentration is 1e 19. cm -3 , a P+ channel layer 2 and an N+ layer 3 are prepared using an ion implantation process.

[0059] Step S200, preparing a plurality of source trenches 4 and a plurality of stop trenches 5 in the epitaxial wafer 1; the source trenches 4 intersect with the inner stop trenches 5 along the y-axis direction, and the inner sidewalls of the inner stop trenches 5 are in contact with the P+ channel layer 2 and the N+ layer 3 respectively;

[0060] Step S210, using a mask to protect the outer regions of the source trench 4 and the cut-off trench 5 through a photolithography process;

[0061] Step S220, forming a source trench 4 and a stop trench 5 by etching, wherein the source trench 4 intersects with the inner stop trench 5 along the y-axis direction, and the inner sidewalls of the inner stop trench 5 are in contact with the P+ channel layer 2 and the N+ layer 3 respectively;

[0062] Correspondingly, the source groove 4 and the cut-off groove 5 extend downward from the top surface of the epitaxial wafer 1 respectively, and their bottom surfaces are lower than the bottom surface of the P+ channel layer 2 and higher than the bottom surface of the N-voltage-resistant layer 13. The width range is set to 1-10um. The source groove 4 intersects with the inner cut-off groove 5 along the y-axis direction, and the inner circle side wall of the inner cut-off groove 5 contacts the P+ channel layer 2 and the N+ layer 3. The relevant parameter settings are related to the electrical design of the device.

[0063] In this embodiment, the source trench 4 and the stop trench 5 have a depth of 4 um and a width of 2 um, and the corresponding trenches are prepared using an ICP dry etching process.

[0064] Step S300, preparing a gate dielectric 6 and polysilicon 7 in the source trench 4 and the stop trench 5 respectively;

[0065] Step S310, using a mask to protect the outer regions of the source trench 4 and the cut-off trench 5 through a photolithography process, and using a thermal oxidation technique to prepare a gate dielectric 6 in the trench;

[0066] Step S320, preparing polysilicon 7 in the trench by chemical vapor deposition;

[0067] Correspondingly, the gate dielectric 6 is located in the source trench 4 and the cut-off trench 5, and is in contact with the N+ layer 3, the P+ channel layer 2, and the N-voltage-resistant layer 13; the polysilicon 7 is located in the source trench 4 and the cut-off trench 5, filling the trenches, and the upper surface of the polysilicon 7 is level with the upper surface of the trenches. The gate dielectric 6 is made of SiO2, and the thickness is set to 40-500nm;

[0068] In this embodiment, 80 nm SiO2 is prepared as the gate dielectric 6 by using thermal oxidation technology, and polysilicon 7 is prepared by using chemical vapor deposition.

[0069] Step S400, depositing an isolation layer 8 on the epitaxial wafer, and opening windows at the N+ layer 3 and the polysilicon 7 in the source trench 4, to prepare an S-pole electrode 9 and a G-pole electrode 10 respectively;

[0070] Step S410, preparing an isolation layer 8 by chemical vapor deposition; and using a photolithography process, using a mask to protect the N+ layer 3 and the outer area of ​​the polysilicon 7 in the source trench 4, and opening windows at the N+ layer 3 and the polysilicon 7 in the source trench 4 by an etching process;

[0071] Step S420, preparing corresponding S-pole electrode 9 and G-pole electrode 10 at the openings of the polysilicon 7 in the N+ layer 3 and the source trench 4 by a stripping process or an etching process;

[0072] Correspondingly, the isolation layer 8 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. ICP dry etching is used to open windows, and the window opening depth is greater than the sum of the thicknesses of the isolation layer 8 and the N+ layer 3. The S-pole electrode 9 extends downward from the top surface of the isolation layer 8, and is connected to the N+ layer 3, the P+ channel layer 2 and the N-voltage-resistant layer 13 to form an ohmic contact. The G-pole electrode 10 extends downward from the top surface of the isolation layer 8, and is connected to the polysilicon 7 to form an ohmic contact.

[0073] In this embodiment, Si3N4 is used as the isolation layer 8, the thickness is set to 200nm, ICP dry etching is used for window opening, the window opening depth is 1.3um, and Al / Ti two-layer metal is used to prepare the S-pole electrode 9 and the G-pole electrode 10.

[0074] Step S500, preparing a D-pole electrode 11 at the bottom of the epitaxial wafer 1, and the entire device is prepared;

[0075] Step S510, preparing a D-pole electrode 11 at the bottom of the epitaxial wafer 1 through a thinning process and a back-gold process, and the entire device is prepared;

[0076] Accordingly, the epitaxial wafer 1 is thinned using a thinning process, and a D-pole electrode 11 is prepared using a back-gold process. The D-pole electrode 11 is connected to the N+ substrate layer 12 to form an ohmic contact.

[0077] In this embodiment, a 350um thick epitaxial wafer 1 is thinned to 180um using a thinning process, and a D-pole electrode 11 is prepared using two layers of Al / Ti metal, and the entire device is prepared.

[0078] The MOSFET terminal structure includes a D-pole electrode 11, an epitaxial wafer 1 and an isolation layer 8 arranged in sequence from bottom to top;

[0079] The epitaxial wafer 1 is provided with:

[0080] There are several P+ channel layers 2, each extending downward from the top surface of the epitaxial wafer 1, and having a bottom surface higher than the bottom surface of the N- withstand voltage layer 13;

[0081] The N+ layer 3 is provided with a plurality of N+ layers, each extending downward from the top surface of the P+ channel layer 2 and having a spacing with the bottom surface of the P+ channel layer 2;

[0082] There are several source trenches 4, which extend downward from the top surface of the epitaxial wafer 1 to the N-voltage-resistant layer 13, and the bottom surface of the source trenches 4 is located between the bottom surface of the N-voltage-resistant layer 13 and the bottom surface of the P+ channel layer 2;

[0083] There are several stop grooves 5, which are respectively located outside the source groove 4, extending downward from the top surface of the epitaxial wafer 1 to the N-voltage-resistant layer 13, and the bottom surface of which is located between the bottom surface of the N-voltage-resistant layer 13 and the bottom surface of the P+ channel layer 2;

[0084] The source trench 4 intersects with the inner stop trench 5 along the y-axis direction, and the inner sidewalls of the inner stop trench 5 are in contact with the P+ channel layer 2 and the N+ layer 3 respectively;

[0085] A plurality of gate dielectrics 6 are provided, which are respectively arranged along the sidewalls of the corresponding stop trench 5 and the sidewalls of the source trench 4; the gate dielectric 6 in the source trench 4 and the gate dielectric 6 on the inner sidewall of the stop trench 5 are respectively connected to the N+ layer 3, the P+ channel layer 2 and the N-voltage-resistant layer 13;

[0086] There are several polysilicon 7, each of which is filled in the gate dielectric 6;

[0087] The isolation layer 8 is provided with:

[0088] An S-pole electrode 9 extends downward from the top surface of the isolation layer 8 into the P+ channel layer 2;

[0089] The G-pole electrode 10 extends downward from the top surface of the isolation layer 8 into the polysilicon 7 .

[0090] The epitaxial wafer 1 includes an N+ substrate layer 12 and an N-voltage-resistant layer 13 connected from bottom to top;

[0091] The D-pole electrode 11 extends downward from the bottom surface of the N+ substrate layer 12 .

[0092] The present invention has the following advantages:

[0093] Traditional MOSFET terminal technology includes field plates, field limiting rings, cut-off trenches, etc. Trench-type MOSFETs often use cut-off trenches as device terminals. The MOSFET terminal area often plays the role of improving the device's withstand voltage, but does not contribute to the device's conduction capability. The present invention innovatively intersects the source trench with the first cut-off trench along the y-axis direction, and the inner circle sidewall of the first cut-off trench contacts the P+ channel layer and the N+ layer. Without adding additional process steps, the inner circle sidewall of the first cut-off trench and the source trench sidewall simultaneously play the role of forming a conductive channel inversion layer, reducing the on-resistance of the device in the on state. Compared with the traditional terminal structure MOSFET, under the same process conditions, the MOSFET terminal structure prepared by the present invention has the same withstand voltage capability and a 5%-10% reduction in on-resistance.

[0094] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0095] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;

[0096] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;

[0097] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a MOSFET terminal structure, characterized in that: The following steps are involved: Step S100, preparing a plurality of P+ channel layers (2) and a plurality of N+ layers (3) in the epitaxial wafer (1); Step S110, using a mask to protect the outer area of ​​the P+ channel layer (2) through a photolithography process; using a diffusion process or an ion implantation process to form a plurality of P+ channel layers (2); Step S120, using a mask to protect the outer area of ​​the N+ layer (3) through a photolithography process; using a diffusion process or an ion implantation process to form a plurality of N+ layers (3); Step S200, preparing a plurality of source trenches (4) and a plurality of stop trenches (5) in the epitaxial wafer (1); the source trenches (4) intersect with the inner stop trenches (5), and the inner side walls of the inner stop trenches (5) are in contact with the P+ channel layer (2) and the N+ layer (3) respectively; Step S210, using a mask to protect the outer regions of the source trench (4) and the stop trench (5) through a photolithography process; Step S220, forming a source trench (4) and a stop trench (5) by an etching process, wherein the source trench (4) intersects with the inner stop trench (5), and the inner sidewall of the trench (5) contacts the P+ channel layer (2) and the N+ layer (3); Step S300, preparing a gate dielectric (6) and polysilicon (7) in the source trench (4) and the stop trench (5) respectively; Step S310, using a photolithography process to protect the outer regions of the source trench (4) and the cut-off trench (5) using a mask, and preparing a gate dielectric (6) in the trench using a thermal oxidation technique; Step S320, preparing polysilicon (7) in the trench by chemical vapor deposition; Step S400, depositing an isolation layer (8) on the epitaxial wafer, and opening windows at the polysilicon (7) in the N+ layer (3) and the source trench (4), and preparing an S-pole electrode (9) and a G-pole electrode (10) respectively; Step S410, preparing an isolation layer (8) by chemical vapor deposition; and using a photolithography process, using a mask to protect the N+ layer (3) and the polysilicon (7) outside the source trench (4), and opening windows at the N+ layer (3) and the polysilicon (7) inside the source trench (4) by an etching process; Step S420, preparing corresponding S-pole electrodes (9) and G-pole electrodes (10) at the openings of the polysilicon (7) in the N+ layer (3) and the source trench (4) by means of a stripping process or an etching process; Step S500, preparing a D-pole electrode (11) at the bottom of the epitaxial wafer (1), and the entire device is prepared.

2. The method for preparing a MOSFET terminal structure according to claim 1, characterized in that: The gate dielectric (6) is made of SiO2 and has a thickness of 40-500 nm.

3. The method for preparing a MOSFET terminal structure according to claim 1, characterized in that: The isolation layer (8) is made of SiO2 or Si3N4 and has a thickness of 10-5000 nm.

4. The method for preparing a MOSFET terminal structure according to claim 1, characterized in that: Step S510, preparing a D-pole electrode (11) at the bottom of the epitaxial wafer (1) through a thinning process and a back-gold process, and the entire device is prepared.

5. A MOSFET terminal structure, prepared by the method for preparing a MOSFET terminal structure according to claim 1, comprising a D-pole electrode (11), an epitaxial wafer (1) and an isolation layer (8) arranged in sequence from bottom to top; The epitaxial wafer (1) is provided with: A plurality of P+ channel layers (2) are provided, each extending downward from the top surface of the epitaxial wafer (1), and having a bottom surface higher than the bottom surface of the N-voltage-resistant layer (13); The N+ layer (3) is provided with a plurality of N+ layers, each extending downward from the top surface of the P+ channel layer (2) and having a spacing with the bottom surface of the P+ channel layer (2); A plurality of source trenches (4) are provided, each extending downward from the top surface of the epitaxial wafer (1) into the N-voltage-resistant layer (13), and the bottom surface of each source trench (4) is located between the bottom surface of the N-voltage-resistant layer (13) and the bottom surface of the P+ channel layer (2); A plurality of stop grooves (5) are provided, each of which is located outside the source groove (4), extends downward from the top surface of the epitaxial wafer (1) to the inside of the N-voltage-resistant layer (13), and has a bottom surface located between the bottom surface of the N-voltage-resistant layer (13) and the bottom surface of the P+ channel layer (2); the source groove (4) intersects with the inner stop groove (5), and the inner circle sidewalls of the inner stop groove (5) are in contact with the P+ channel layer (2) and the N+ layer (3); A plurality of gate dielectrics (6) are provided, and are respectively arranged along the side walls of the corresponding stop trench (5) and the side walls of the source trench (4); the gate dielectric (6) in the source trench (4) and the gate dielectric (6) on the inner side wall of the inner stop trench (5) are respectively connected to the N+ layer (3), the P+ channel layer (2) and the N-voltage-resistant layer (13); A plurality of polysilicon (7) are provided and are respectively filled in the gate dielectric (6); The isolation layer (8) is provided with: An S-pole electrode (9) extending downward from the top surface of the isolation layer (8) into the P+ channel layer (2); A G-pole electrode (10) extends downward from the top surface of the isolation layer (8) into the polysilicon (7).

6. The MOSFET terminal structure according to claim 5, characterized in that: The epitaxial wafer (1) comprises an N+ substrate layer (12) and an N-voltage-resistant layer (13) connected from bottom to top; The D-pole electrode (11) extends downward from the bottom surface of the N+ substrate layer (12).

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