Power amplification circuit, electronic circuit and electronic equipment

Abstract

The invention provides a power amplification circuit, an electronic circuit and electronic equipment. The power amplification circuit is used for performing power amplification on a first input signal and a second input signal which are input. Wherein the phase difference between the first input signal and the second input signal is 180. According to the power amplification circuit, a second MOS tube and a first MOS tube in a first Cascode unit are turned on and turned off at the same time through a first input signal, and a fourth MOS tube and a third MOS tube in a second Cascode unit are turned on and turned off at the same time through a second input signal, so that the on-resistance is reduced, the loss of direct-current power is reduced, and the power amplification efficiency is improved; the resonance unit generates resonance with the parasitic capacitance of the second MOS tube and the parasitic capacitance of the first MOS tube and generates resonance with the parasitic capacitance of the fourth MOS tube and the parasitic capacitance of the third MOS tube, so that the influence generated by the parasitic capacitance is eliminated, and the power amplification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of power amplification, and in particular to a power amplification circuit, an electronic circuit and an electronic device. Background Art

[0002] In the existing field of digital modulation polarity transmitters ， The structure of the Class D amplifier contains PMOS, which has a higher on-resistance than NMOS. In order to achieve an on-resistance similar to that of the NMOS switch, the size of the PMOS switch needs to be increased by 2-3 times, which will significantly increase the input capacitance. Class E amplifiers require more passive components, which will reduce output efficiency. Therefore, there is an urgent need for a power amplifier that can achieve low loss, few components and high efficiency. Summary of the invention

[0003] The present invention provides a power amplifier circuit, an electronic circuit and an electronic device, so as to realize high-efficiency and low-loss power amplification of an input signal with fewer components.

[0004] According to a first aspect of the present invention, a power amplifier circuit is provided for performing power amplification on a first input signal and a second input signal; wherein the phase difference between the first input signal and the second input signal is 180. The circuit comprises:

[0005] A first power amplification unit, comprising a first cascode unit consisting of a second MOS tube and a first MOS tube, and a first signal input sub-unit;

[0006] The output end of the first signal input subunit is connected to the input end of the first Cascode unit, and the first signal input subunit is used to receive the first input signal and output it to the first Cascode unit; the first Cascode unit is used to simultaneously turn on and off the second MOS transistor and the first MOS transistor according to the first input signal, so as to power amplify the first input signal and output a first power amplifier signal;

[0007] The second power amplification unit includes a second cascode unit composed of a fourth MOS tube and a third MOS tube and a second signal input subunit;

[0008] The output end of the second signal input subunit is connected to the input end of the second Cascode unit, and the second signal input subunit is used to receive the second input signal and output it to the second Cascode unit; the second Cascode unit is used to turn on and off the fourth MOS tube and the third MOS tube at the same time according to the second input signal, so as to power amplify the second input signal and output a second power amplifier signal;

[0009] A resonance unit, coupled to the drain of the first MOS tube and the drain of the fourth MOS tube respectively; the resonance unit is used to resonate with the parasitic capacitance of the second MOS tube and the parasitic capacitance of the first MOS tube; the resonance unit is also used to resonate with the parasitic capacitance of the fourth MOS tube and the parasitic capacitance of the third MOS tube;

[0010] A filter unit; a first end of which is coupled to the output end of the first Cascode unit, and a second end of which is coupled to the output end of the second Cascode unit; the filter unit is used to receive the first power amplifier signal and the second power amplifier signal, filter the first power amplifier signal and the second power amplifier signal respectively, and output them;

[0011] The power supply terminal is coupled to the third terminal of the filter unit; the power supply terminal is used to provide a power supply voltage.

[0012] Optionally, the specific structure of the first Cascode unit is: the second end of the second MOS tube serves as the output end of the first Cascode unit, the first end of the second MOS tube is connected to the second end of the first MOS tube, and the first end of the first MOS tube is grounded; in addition to receiving the first input signal, the gate of the second MOS tube and the gate of the first MOS tube also receive a second static voltage and a first static voltage respectively;

[0013] The second static voltage is used to maintain the second MOS transistor at a static operating point, and the first static voltage is also used to maintain the first MOS transistor at a static operating point.

[0014] Optionally, the first signal input subunit includes a second capacitor, a first capacitor, a second impedance, and a first impedance;

[0015] The first end of the second capacitor receives the first input signal, the second end of the second capacitor is connected to the first end of the second impedance, and the second end of the second impedance is connected to the gate of the second MOS tube; the second capacitor is used to block the second static voltage;

[0016] The first end of the first capacitor also receives the first input signal, the second end of the first capacitor is connected to the first end of the first impedance, and the second end of the first impedance is connected to the gate of the first MOS tube; the first capacitor is also used to block the first static voltage.

[0017] Optionally, the first power amplification unit further includes a second resistor and a first resistor;

[0018] The second resistor is connected between the second static voltage and the gate of the second MOS tube; the first resistor is connected between the first static voltage and the gate of the first MOS tube.

[0019] Optionally, the specific structure of the second Cascode unit is: the second end of the fourth MOS tube serves as the output end of the second Cascode unit, the first end of the fourth MOS tube is connected to the second end of the third MOS tube, and the first end of the third MOS tube is grounded; in addition to receiving the second input signal, the gate of the fourth MOS tube and the gate of the third MOS tube also receive the fourth static voltage and the third static voltage respectively;

[0020] The second static voltage is used to maintain the fourth MOS transistor at a static operating point, and the first static voltage is also used to maintain the third MOS transistor at a static operating point.

[0021] Optionally, the second signal input subunit includes a fourth capacitor, a third capacitor, a fourth impedance, and a third impedance;

[0022] The first end of the fourth capacitor receives the second input signal, the second end of the fourth capacitor is connected to the first end of the fourth impedance, and the second end of the fourth impedance is connected to the gate of the fourth MOS tube; the fourth capacitor is used to block the fourth static voltage;

[0023] The first end of the third capacitor also receives the second input signal, the second end of the third capacitor is connected to the first end of the third impedance, and the second end of the third impedance is connected to the gate of the third MOS tube; the third capacitor is also used to block the third static voltage.

[0024] Optionally, the second power amplification unit further includes a fourth resistor and a third resistor;

[0025] The fourth resistor is connected between the fourth static voltage and the gate of the fourth MOS tube; the third resistor is connected between the third static voltage and the gate of the third MOS tube.

[0026] Optionally, the resistance value of the second impedance to the resistance value of the third impedance are the same, and are all 100Ω.

[0027] Optionally, the resonance unit includes a first inductor network;

[0028] The first inductor network is connected between the first end of the second MOS transistor and the first end of the fourth MOS transistor.

[0029] Optionally, the resonance unit includes a second inductor network and a third inductor network;

[0030] The second inductor network is connected between the first end of the second MOS transistor and the second end of the first MOS transistor;

[0031] The third inductor network is connected between the first end of the fourth MOS tube and the second end of the third MOS tube.

[0032] Optionally, the inductor network specifically includes a first inductor.

[0033] Optionally, the filtering unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, a second inductor, a third inductor, a fourth inductor, and a fifth resistor;

[0034] The first end of the fifth capacitor and the first end of the seventh capacitor serve as the first end and the second end of the filtering unit respectively, and the sixth capacitor is connected between the second end of the fifth capacitor and the second end of the seventh capacitor; the fifth resistor is connected in parallel with the sixth capacitor, the first end of the fifth resistor outputs the filtered first power amplifier signal, and the second end of the fifth resistor outputs the filtered second power amplifier signal;

[0035] The first end of the fifth capacitor is also connected to the first end of the second inductor, and the first end of the seventh capacitor is also connected to the first end of the fourth inductor;

[0036] The second end of the second inductor, the second end of the fourth inductor, and the second end of the third inductor are all connected to a node; the first end of the third inductor serves as the third end of the filter unit.

[0037] According to a second aspect of the present invention, an electronic circuit is provided, comprising the power amplifier circuit provided by the first aspect of the present invention and the optional solution.

[0038] According to a third aspect of the present invention, an electronic device is provided, comprising the electronic circuit provided by the second aspect of the present invention.

[0039] The power amplifier circuit provided by the present invention simultaneously turns on and off the second MOS tube and the first MOS tube through the first input signal, and simultaneously turns on and off the fourth MOS tube and the third MOS tube through the second input signal, so as to reduce the on-resistance, reduce the loss of DC power, and improve the power amplification efficiency; and resonates with the respective parasitic capacitances of the second MOS tube and the first MOS tube through the resonance unit, and resonates with the respective parasitic capacitances of the fourth MOS tube and the third MOS tube, so as to eliminate the influence of each parasitic capacitance and improve the power amplification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0041] Figure 1 is a structural block diagram of the power amplifier circuit provided in an embodiment of the present invention;

[0042] Figure 2 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 1 ;

[0043] Figure 3 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 2 ;

[0044] Figure 4 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 3 ;

[0045] Figure 5 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 4 ;

[0046] Figure 6 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 5 ;

[0047] Figure 7 The circuit structure of the power amplifier circuit provided by the embodiment of the present invention is Figure 6 ; Description of the drawings:

[0048] 10-a first power amplification unit;

[0049] 11- first signal input subunit;

[0050] 12-first Cascode unit;

[0051] 20-a second power amplification unit;

[0052] 21- a second signal input subunit;

[0053] 22-second Cascode unit;

[0054] 30-resonance unit;

[0055] 31- first inductor network;

[0056] 32- second inductor network;

[0057] 33- the third inductor network;

[0058] 40- filtering unit;

[0059] VDD-power supply terminal;

[0060] M1-first MOS tube;

[0061] M2-second MOS tube;

[0062] M3-the third MOS tube;

[0063] M4-the fourth MOS tube;

[0064] R1-first resistor;

[0065] R2-second resistor;

[0066] R3-the third resistor;

[0067] R4-the fourth resistor;

[0068] R5-fifth resistor;

[0069] RF1 - first input signal;

[0070] RF2 - second input signal;

[0071] Z1-first impedance;

[0072] Z2-second impedance;

[0073] Z3-third impedance;

[0074] Z4-fourth impedance;

[0075] C1-first capacitor;

[0076] C2-second capacitor;

[0077] C3-third capacitor;

[0078] C4-the fourth capacitor;

[0079] C5-fifth capacitor;

[0080] C6-sixth capacitor;

[0081] C7-seventh capacitor;

[0082] VG1-first static voltage;

[0083] VG2-second static voltage;

[0084] VG3-third static voltage;

[0085] VG4-fourth static voltage;

[0086] L2-second inductor;

[0087] L3-third inductor;

[0088] L4 - the fourth inductor. DETAILED DESCRIPTION

[0089] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0090] Before describing the embodiments of the present invention, the design concept of the present invention is briefly described:

[0091] When the power amplifier circuit performs power amplification on the input signal, the drain parasitic capacitance, input resistance, and on-resistance of the transistor will affect the efficiency of the power amplification. Generally, the larger the drain parasitic capacitance of the transistor and the on-resistance of the transistor in the circuit, the lower the power amplification efficiency of the circuit; the higher the input impedance of the transistor, the higher the power amplification efficiency of the circuit. In order to eliminate the influence of the drain parasitic capacitance of the transistor, the present invention generates resonance with the drain parasitic capacitance of the transistor through an inductor so that the drain parasitic capacitance does not discharge and the power amplification efficiency is improved; in order to reduce the influence of the on-resistance of the transistor and increase the input impedance of the transistor, the present invention increases the input resistance through a cascode structure, and reduces the on-resistance by simultaneously turning on and off the transistor in the cascode structure.

[0092] In the embodiments of the present invention, the input signals of the power amplifier circuit are all referred to as RF signals. The RF signal is specifically a modulated electromagnetic wave, whose carrier waveform is generally a sine wave, and the RF signal generally carries information through frequency. Specifically: modulation generally includes analog modulation and digital modulation; wherein the analog modulation generally includes amplitude modulation, phase modulation and frequency modulation. The digital modulation generally includes amplitude keying, frequency keying and phase shift keying.

[0093] Please refer to Figure 1 , An embodiment of the present invention provides a power amplifier circuit for amplifying the power of a first input signal RF1 and a second input signal RF2; wherein the phase difference between the first input signal RF1 and the second input signal RF2 is 180. , The circuit includes:

[0094] The first power amplifying unit 10 includes a first cascode unit 12 composed of a second MOS transistor M2 and a first MOS transistor M1 and a first signal input subunit 11;

[0095] The output end of the first signal input subunit 11 is connected to the input end of the first Cascode unit 12, and the first signal input subunit 11 is used to receive the first input signal RF1 and output it to the first Cascode unit 12; the first Cascode unit 12 is used to simultaneously turn on and off the second MOS transistor M2 and the first MOS transistor M1 through the first input signal RF1, so as to power amplify the first input signal RF1 and output a first power amplifier signal;

[0096] The second power amplifying unit 20 includes a second cascode unit 22 composed of a fourth MOS transistor M4 and a third MOS transistor M3 and a second signal input subunit 21;

[0097] The output end of the second signal input subunit 21 is connected to the input end of the second Cascode unit 22, and the second signal input subunit 21 is used to receive the second input signal RF2 and output it to the second Cascode unit 22; the second Cascode unit 22 is used to simultaneously turn on and off the fourth MOS transistor M4 and the third MOS transistor M3 through the second input signal RF2, so as to power amplify the second input signal RF2 and output a second power amplifier signal;

[0098] The resonance unit 30 is coupled to the drain of the first MOS tube M1 and the drain of the fourth MOS tube M4 respectively; the resonance unit 30 is used to resonate with the parasitic capacitance of the second MOS tube M2 and the parasitic capacitance of the first MOS tube M1; the resonance unit 30 is also used to resonate with the parasitic capacitance of the fourth MOS tube M4 and the parasitic capacitance of the third MOS tube M3;

[0099] A filter unit 40; a first end of which is coupled to the output end of the first Cascode unit 12, and a second end of which is coupled to the output end of the second Cascode unit 22; the filter unit 40 is used to receive the first power amplifier signal and the second power amplifier signal, filter the first power amplifier signal and the second power amplifier signal respectively, and output them;

[0100] The power terminal VDD is coupled to the third terminal of the filter unit 40 ; the power terminal VDD is used to provide a power voltage.

[0101] The embodiment of the present invention adopts the above technical solution to increase the input impedance of the first power amplification unit 10 and the second power amplification unit 20, thereby improving the power amplification efficiency of the power amplification circuit; to reduce the on-resistance of the first power amplification unit 10 and the second power amplification unit 20, reduce the loss of DC power, and improve the power amplification efficiency of the power amplification circuit; to offset the influence of the drain capacitance of each transistor in the first power amplification unit 10 and the second power amplification unit 20, thereby improving the power amplification efficiency of the power amplification circuit. The specific principles are as follows:

[0102] As for increasing the input impedance, the input impedance of each is increased by using the characteristics of the first Cascode unit 12 and the second Cascode unit 22, thereby improving the power amplification efficiency of the power amplifier circuit.

[0103] For reducing the on-resistance, the first input signal RF1 simultaneously turns on and off the second MOS transistor M2 and the first MOS transistor M1 in the first Cascode unit 12 through the first signal input subunit 11, so as to reduce the on-resistance of the first Cascode unit 12, reduce the loss of DC power, and improve the power amplifier efficiency of the power amplifier circuit; the second input signal RF2 simultaneously turns on and off the fourth MOS transistor M4 and the third MOS transistor M3 in the second Cascode unit 22 through the second signal input subunit 21, so as to reduce the on-resistance of the second Cascode unit 22, reduce the loss of DC power, and improve the power amplifier efficiency of the power amplifier circuit.

[0104] In order to offset the influence of the drain capacitance of the transistor, the resonance unit 30 is used to generate resonance with the drain capacitance of the transistor in the first Cascode unit 12 to offset the influence of the drain capacitance of the transistor in the first Cascode unit 12, thereby improving the power amplifier efficiency of the power amplifier circuit; the resonance unit 30 is used to generate resonance with the drain capacitance of the transistor in the second Cascode unit 22 to offset the influence of the drain capacitance of the transistor in the second Cascode unit 22, thereby improving the power amplifier efficiency of the power amplifier circuit.

[0105] The first Cascode unit 12 and the first signal input subunit 11 in the embodiment of the present invention are described in detail below.

[0106] Please refer to Figure 2 As a specific implementation, the specific structure of the first Cascode unit 12 is as follows: the second end of the second MOS transistor M2 serves as the output end of the first Cascode unit 12, the first end of the second MOS transistor M2 is connected to the second end of the first MOS transistor M1, and the first end of the first MOS transistor M1 is grounded; in addition to receiving the first input signal RF1, the gate of the second MOS transistor M2 and the gate of the first MOS transistor M1 also receive the second static voltage VG2 and the first static voltage VG1 respectively;

[0107] The second static voltage VG2 is used to maintain the second MOS transistor M2 at a static operating point, and the first static voltage VG1 is also used to maintain the first MOS transistor M1 at a static operating point.

[0108] The beneficial effects of this specific implementation are as follows: the second static voltage VG2 and the first static voltage VG1 make the second MOS tube M2 and the first MOS tube M1 both at a static working point, and because the first input signal RF1 turns on and off the second MOS tube M2 and the first MOS tube M1 at the same time. Therefore, when the first input signal RF1 is greater than zero, the second MOS tube M2 and the first MOS tube M1 are turned on at the same time; when the first input signal RF1 is less than zero, the second MOS tube M2 and the first MOS tube M1 are turned off at the same time, so as to further reduce the on-resistance of the first Cascode unit 12 and improve the power amplifier efficiency of the power amplifier circuit.

[0109] As a supplementary explanation, the respective sizes of the second MOS tube M2 and the first MOS tube M1 will also affect the power amplifier circuit, and the sizes here include but are not limited to the width-to-length ratio. Specifically: if the sizes of the second MOS tube M2 and the first MOS tube M1 are smaller, the input impedance of the first Cascode unit 12 composed of the second MOS tube M2 and the first MOS tube M1 will be greater, but the smaller the sizes of the second MOS tube M2 and the first MOS tube M1, the smaller the current flowing through the second MOS tube M2 and the first MOS tube M1 will be when turned on, thereby reducing the output power. Therefore, the size selection of the second MOS tube M2 and the first MOS tube M1 needs to take into account the balance between the power amplifier efficiency and the output power of the power amplifier circuit.

[0110] Please refer to Figure 2 As a specific implementation, the first signal input subunit 11 includes a second capacitor C2, a first capacitor C1, a second impedance Z2, and a first impedance Z1;

[0111] The first end of the second capacitor C2 receives the first input signal RF1, the second end of the second capacitor C2 is connected to the first end of the second impedance Z2, and the second end of the second impedance Z2 is connected to the gate of the second MOS transistor M2; the second capacitor C2 is used to block the second static voltage VG2;

[0112] The first end of the first capacitor C1 also receives the first input signal RF1, the second end of the first capacitor C1 is connected to the first end of the first impedance Z1, and the second end of the first impedance Z1 is connected to the gate of the first MOS tube M1; the first capacitor C1 is also used to block the first static voltage VG1. Specifically: the second impedance Z2 and the first impedance Z1 are both 100 ohms. The reason is: in the radio frequency field, the characteristic impedance of the transmission line is required to be designed to be 50 ohms, so the embodiment of the present invention realizes the characteristic impedance of the transmission line to be 50 ohms by connecting two 100 ohm impedances in parallel. Of course, the characteristic impedance of the transmission line can also be set to other ohms, such as 72 ohms, which is not limited here. But 50 ohms is a conventional setting, and other types of settings are not common.

[0113] The beneficial effect of this specific implementation is that the second static voltage VG2 and the first static voltage VG1 can be prevented from affecting the first input signal RF1. The specific principle is:

[0114] The second static voltage VG2 and the first static voltage VG1 not only control the second MOS tube M2 and the first MOS tube M1 to work at the static working point, but also flow to the input node of the first input signal RF1 respectively, so the second capacitor C2 is set between the input node of the first input signal RF1 and the input node of the second static voltage VG2, and the first capacitor C1 is set between the input node of the first input signal RF1 and the input node of the first static voltage VG1, and the characteristic of capacitor blocking direct current is used to block the second static voltage VG2 and the first static voltage VG1 from flowing to the input node of the first input signal RF1, so as to prevent the second static voltage VG2 and the first static voltage VG1 from affecting the first input signal RF1.

[0115] Please refer to Figure 3 As a specific implementation, the first power amplification unit 10 further includes a second resistor R2 and a first resistor R1;

[0116] The second resistor R2 is connected between the second static voltage VG2 and the gate of the second MOS transistor M2; the first resistor R1 is connected between the first static voltage VG1 and the gate of the first MOS transistor M1.

[0117] The second Cascode unit 22 and the second signal input subunit 21 in the embodiment of the present invention are described in detail below.

[0118] Please refer to Figure 2As a specific implementation, the specific structure of the second Cascode unit 22 is as follows: the second end of the fourth MOS tube M4 serves as the output end of the second Cascode unit 22, the first end of the fourth MOS tube M4 is connected to the second end of the third MOS tube M3, and the first end of the third MOS tube M3 is grounded; in addition to receiving the second input signal RF2, the gate of the fourth MOS tube M4 and the gate of the third MOS tube M3 also receive the fourth static voltage VG4 and the third static voltage VG3 respectively;

[0119] The second static voltage VG2 is used to maintain the fourth MOS tube M4 at a static operating point, and the first static voltage VG1 is also used to maintain the third MOS tube M3 at a static operating point.

[0120] The beneficial effects of this specific implementation are as follows: the second static voltage VG2 and the first static voltage VG1 make the fourth MOS tube M4 and the third MOS tube M3 both at a static operating point, and because the first input signal RF1 simultaneously turns on and off the fourth MOS tube M4 and the third MOS tube M3. Therefore, when the second input signal RF2 is greater than zero, the fourth MOS tube M4 and the third MOS tube M3 are simultaneously turned on; when the second input signal RF2 is less than zero, the fourth MOS tube M4 and the third MOS tube M3 are simultaneously turned off, so as to further reduce the on-resistance of the second Cascode unit 22 and improve the power amplifier efficiency of the power amplifier circuit.

[0121] As a supplementary explanation, the respective sizes of the fourth MOS tube M4 and the third MOS tube M3 will also affect the power amplifier circuit, and the sizes here include but are not limited to the width-to-length ratio. Specifically: if the sizes of the fourth MOS tube M4 and the third MOS tube M3 are smaller, the input impedance of the second Cascode unit 22 composed of the fourth MOS tube M4 and the third MOS tube M3 will be greater, but the smaller the sizes of the fourth MOS tube M4 and the third MOS tube M3, the smaller the current flowing through the fourth MOS tube M4 and the third MOS tube M3 will be when turned on, thereby reducing the output power. Therefore, the size selection of the fourth MOS tube M4 and the third MOS tube M3 needs to take into account the balance between the power amplifier efficiency and the output power of the power amplifier circuit.

[0122] Please refer to Figure 2 As a specific implementation, the second signal input subunit 21 includes a fourth capacitor C4, a third capacitor C3, a fourth impedance Z4, and a third impedance Z3;

[0123] The first end of the fourth capacitor C4 receives the second input signal RF2, the second end of the fourth capacitor C4 is connected to the first end of the fourth impedance Z4, and the second end of the fourth impedance Z4 is connected to the gate of the fourth MOS transistor M4; the fourth capacitor C4 is used to block the fourth static voltage VG4;

[0124] The first end of the third capacitor C3 also receives the second input signal RF2, the second end of the third capacitor C3 is connected to the first end of the third impedance Z3, and the second end of the third impedance Z3 is connected to the gate of the third MOS tube M3; the third capacitor C3 is also used to block the third static voltage VG3. Specifically: the fourth impedance Z4 and the third impedance Z3 are both 100 ohms. The reason is: in the radio frequency field, the characteristic impedance of the transmission line is required to be designed to be 50 ohms, so the embodiment of the present invention achieves the characteristic impedance of the transmission line to be 50 ohms by connecting two 100 ohm impedances in parallel. Of course, the transmission line impedance can also be set to other ohms, such as 72 ohms, which is not limited here. But 50 ohms is a conventional setting, and other types of settings are not common.

[0125] The beneficial effect of this specific implementation is that it can prevent the fourth static voltage VG4 and the third static voltage VG3 from affecting the second input signal RF2. The specific principle is:

[0126] The fourth static voltage VG4 and the third static voltage VG3 not only control the fourth MOS tube M4 and the third MOS tube M3 to work at the static working point, but also flow to the input node of the second input signal RF2 respectively, so the fourth capacitor C4 is set between the input node of the second input signal RF2 and the input node of the fourth static voltage VG4, and the third capacitor C3 is set between the input node of the second input signal RF2 and the input node of the third static voltage VG3, and the characteristic of capacitor blocking direct current is used to block the fourth static voltage VG4 and the third static voltage VG3 from flowing to the input node of the second input signal RF2, so as to avoid the fourth static voltage VG4 and the third static voltage VG3 from affecting the second input signal RF2.

[0127] Please refer to Figure 3 As a specific implementation, the second power amplification unit 20 further includes a fourth resistor R4 and a third resistor R3;

[0128] The fourth resistor R4 is connected between the fourth static voltage VG4 and the gate of the fourth MOS tube M4; the third resistor R3 is connected between the third static voltage VG3 and the gate of the third MOS tube M3.

[0129] As a specific implementation manner, the second static voltage VG2 is equal to the fourth static voltage VG4, and the first static voltage VG1 is equal to the third static voltage VG3; the reason is: according to the symmetry requirements required by the industry, the second MOS tube M2 and the fourth MOS tube M4 are set to be exactly the same MOS tube, and the first MOS tube M1 and the third MOS tube M3 are set to be exactly the same MOS tube, so the second static voltage VG2 is equal to the fourth static voltage VG4; the first static voltage VG1 is equal to the third static voltage VG3.

[0130] The following specifically introduces different implementations of the resonance unit 30 in the embodiments of the present invention.

[0131] Please refer to Figure 4 As a specific implementation, the resonance unit 30 includes a first inductor network 31; the first inductor network 31 is connected between the first end of the second MOS transistor M2 and the first end of the fourth MOS transistor M4. The essence of the resonance unit 30 is the parallel resonance of the inductor network.

[0132] Please refer to Figure 5 , as another specific implementation, the resonance unit 30 includes a second inductor L2 network 32 and a third inductor L3 network 33;

[0133] The second inductor L2 network 32 is connected between the first end of the second MOS transistor M2 and the second end of the first MOS transistor M1;

[0134] The third inductor L3 network 33 is connected between the first end of the fourth MOS transistor M4 and the second end of the third MOS transistor M3. The essence of the resonance unit 30 is the series resonance of the inductor network.

[0135] The beneficial effects of the above scheme adopted in the embodiment of the present invention are as follows: resonating with the drain capacitors of the second MOS tube M2 and the fourth MOS tube M4 through the inductor network, so that the drain capacitors of the second MOS tube M2 and the fourth MOS tube M4 are not charged or discharged, reducing DC power loss and improving the power amplifier efficiency of the power amplifier circuit. As for whether to choose series resonance or parallel resonance, it can be selected according to needs and is not limited here. Among them, the first inductor network 31 to the third inductor L3 network 33 can include only a single inductor, or a series and parallel connection of multiple inductors, which is not limited here.

[0136] The filtering unit 40 in the embodiment of the present invention is described in detail below.

[0137] Please refer to Figure 6 or Figure 7As a specific implementation, the filtering unit 40 includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a second inductor L2, a third inductor L3, a fourth inductor L4, and a fifth resistor R5;

[0138] The first end of the fifth capacitor C5 and the first end of the seventh capacitor C7 serve as the first end and the second end of the filtering unit 40 respectively, and the sixth capacitor C6 is connected between the second end of the fifth capacitor C5 and the second end of the seventh capacitor C7; the fifth resistor R5 is connected in parallel with the sixth capacitor C6, the first end of the fifth resistor R5 outputs the filtered first power amplifier signal, and the second end of the fifth resistor R5 outputs the filtered second power amplifier signal;

[0139] The first end of the fifth capacitor C5 is also connected to the first end of the second inductor L2, and the first end of the seventh capacitor C7 is also connected to the first end of the fourth inductor L4; specifically: the fifth capacitor C5 and the seventh capacitor C7 are voltage-divided by the sixth capacitor C6, so that the equivalent impedance of the filtering unit 40 matches the characteristic impedance of the transmission line.

[0140] The second end of the second inductor L2 , the second end of the fourth inductor L4 , and the second end of the third inductor L3 are all connected to a node; the first end of the third inductor L3 serves as the third end of the filter unit 40 .

[0141] An embodiment of the present invention further provides an electronic circuit, comprising the power amplifier circuit described in the embodiment of the present invention.

[0142] An embodiment of the present invention further provides an electronic device, comprising the electronic circuit described in the embodiment of the present invention.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power amplifier circuit, used for power amplification of a first input signal and a second input signal; wherein: The phase difference between the first input signal and the second input signal is 180. , characterized in that the circuit comprises: A first power amplification unit, comprising a first cascode unit consisting of a second MOS tube and a first MOS tube, and a first signal input sub-unit; The output end of the first signal input subunit is connected to the input end of the first Cascode unit, and the first signal input subunit is used to receive the first input signal and output it to the first Cascode unit; the first Cascode unit is used to simultaneously turn on and off the second MOS transistor and the first MOS transistor according to the first input signal, so as to power amplify the first input signal and output a first power amplifier signal; The second power amplification unit includes a second cascode unit composed of a fourth MOS tube and a third MOS tube and a second signal input subunit; The output end of the second signal input subunit is connected to the input end of the second Cascode unit, and the second signal input subunit is used to receive the second input signal and output it to the second Cascode unit; the second Cascode unit is used to turn on and off the fourth MOS tube and the third MOS tube at the same time according to the second input signal, so as to power amplify the second input signal and output a second power amplifier signal; A resonance unit, coupled to the drain of the first MOS tube and the drain of the fourth MOS tube respectively; the resonance unit is used to resonate with the parasitic capacitance of the second MOS tube and the parasitic capacitance of the first MOS tube; the resonance unit is also used to resonate with the parasitic capacitance of the fourth MOS tube and the parasitic capacitance of the third MOS tube; A filter unit; a first end of which is coupled to the output end of the first Cascode unit, and a second end of which is coupled to the output end of the second Cascode unit; the filter unit is used to receive the first power amplifier signal and the second power amplifier signal, filter the first power amplifier signal and the second power amplifier signal respectively, and output them; The power supply terminal is coupled to the third terminal of the filter unit; the power supply terminal is used to provide a power supply voltage.

2. The power amplifier circuit according to claim 1, characterized in that: The specific structure of the first Cascode unit is as follows: the second end of the second MOS tube serves as the output end of the first Cascode unit, the first end of the second MOS tube is connected to the second end of the first MOS tube, and the first end of the first MOS tube is grounded; in addition to receiving the first input signal, the gate of the second MOS tube and the gate of the first MOS tube also receive a second static voltage and a first static voltage respectively; The second static voltage is used to maintain the second MOS transistor at a static operating point, and the first static voltage is also used to maintain the first MOS transistor at a static operating point.

3. The power amplifier circuit according to claim 2, characterized in that: The first signal input subunit includes a second capacitor, a first capacitor, a second impedance, and a first impedance; A first end of the second capacitor receives the first input signal, a second end of the second capacitor is connected to a first end of the second impedance, and a second end of the second impedance is connected to a gate of the second MOS transistor; The second capacitor is used to block the second static voltage; The first end of the first capacitor also receives the first input signal, the second end of the first capacitor is connected to the first end of the first impedance, and the second end of the first impedance is connected to the gate of the first MOS tube; the first capacitor is also used to block the first static voltage.

4. The power amplifier circuit according to claim 3, characterized in that: The first power amplification unit further includes a second resistor and a first resistor; The second resistor is connected between the second static voltage and the gate of the second MOS tube; the first resistor is connected between the first static voltage and the gate of the first MOS tube.

5. The power amplifier circuit according to claim 3, characterized in that: The specific structure of the second Cascode unit is as follows: the second end of the fourth MOS tube serves as the output end of the second Cascode unit, the first end of the fourth MOS tube is connected to the second end of the third MOS tube, and the first end of the third MOS tube is grounded; the gate of the fourth MOS tube and the gate of the third MOS tube receive the fourth static voltage and the third static voltage respectively in addition to receiving the second input signal; The second static voltage is used to maintain the fourth MOS transistor at a static operating point, and the first static voltage is also used to maintain the third MOS transistor at a static operating point.

6. The power amplifier circuit according to claim 5, characterized in that: The second signal input subunit includes a fourth capacitor, a third capacitor, a fourth impedance, and a third impedance; The first end of the fourth capacitor receives the second input signal, the second end of the fourth capacitor is connected to the first end of the fourth impedance, and the second end of the fourth impedance is connected to the gate of the fourth MOS transistor; The fourth capacitor is used to block the fourth static voltage; The first end of the third capacitor also receives the second input signal, the second end of the third capacitor is connected to the first end of the third impedance, and the second end of the third impedance is connected to the gate of the third MOS tube; the third capacitor is also used to block the third static voltage.

7. The power amplifier circuit according to claim 6, characterized in that: The second power amplification unit further includes a fourth resistor and a third resistor; The fourth resistor is connected between the fourth static voltage and the gate of the fourth MOS tube; the third resistor is connected between the third static voltage and the gate of the third MOS tube.

8. The power amplifier circuit according to claim 7, characterized in that: The resistance value of the second impedance to the resistance value of the third impedance are all the same, and are all 100Ω.

9. The power amplifier circuit according to claim 8, characterized in that: The resonance unit comprises a first inductor network; The first inductor network is connected between the first end of the second MOS transistor and the first end of the fourth MOS transistor.

10. The power amplifier circuit according to claim 8, characterized in that: The resonance unit includes a second inductor network and a third inductor network; The second inductor network is connected between the first end of the second MOS transistor and the second end of the first MOS transistor; The third inductor network is connected between the first end of the fourth MOS tube and the second end of the third MOS tube.

11. The power amplifier circuit according to claim 9 or 10, characterized in that: The inductor network specifically includes a first inductor.

12. The power amplifier circuit according to claim 1, characterized in that: The filtering unit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, a second inductor, a third inductor, a fourth inductor, and a fifth resistor; The first end of the fifth capacitor and the first end of the seventh capacitor serve as the first end and the second end of the filtering unit respectively, and the sixth capacitor is connected between the second end of the fifth capacitor and the second end of the seventh capacitor; the fifth resistor is connected in parallel with the sixth capacitor, the first end of the fifth resistor outputs the filtered first power amplifier signal, and the second end of the fifth resistor outputs the filtered second power amplifier signal; The first end of the fifth capacitor is also connected to the first end of the second inductor, and the first end of the seventh capacitor is also connected to the first end of the fourth inductor; The second end of the second inductor, the second end of the fourth inductor, and the second end of the third inductor are all connected to a node; the first end of the third inductor serves as the third end of the filtering unit.

13. An electronic circuit, characterized in that: The electronic circuit comprises the power amplifier circuit according to claims 1 to 12.

14. An electronic device, characterized in that: The electronic device comprises the electronic circuit according to claim 13.

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