Method, device and electronic equipment for testing wafer

Abstract

The present application is applicable to the field of semiconductor technology, and provides a method, device and electronic device for testing wafers. The method for testing wafers provided by the present application obtains the depth value to be detected and the allowed detection depth value of the wafer; if the depth value to be detected is greater than the allowed detection depth value, the depth value to be detected is divided into at least two sub-depth values ​​according to the allowed detection depth value, and each sub-depth value is less than the allowed detection depth value; during the test process of the wafer, the wafer is detected according to the test stages corresponding to the at least two sub-depth values, and the detection results corresponding to the at least two test stages are obtained; based on the detection results corresponding to the at least two test stages, the final test result of the wafer is determined. It can solve the technical problems in the prior art that wafer cracks are prone to occur during the wafer testing process, and the test function fails due to contact problems.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and more specifically, to a method, device and electronic equipment for testing wafers. Background Art

[0002] The development of micro-electromechanical system (MEMS) technology has played a huge role in promoting the miniaturization of various sensing devices. Currently, MEMS products are widely used in consumer electronics, automotive electronics, industry, medical care, aerospace and other fields.

[0003] MEMS wafer testing is a key step in the semiconductor manufacturing process. It is used to verify the integrity, component characteristics, connections and packaging of the microstructure designed on the wafer, thereby evaluating and ensuring the quality and performance of MEMS devices during the production process.

[0004] However, since wafers made based on MEMS technology are characterized by high hardness and are not easy to pierce, wafer cracks are likely to occur during the wafer testing process, and the test function may fail due to contact problems, resulting in reduced wafer product yield and prone to quality accidents. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a method, device and electronic equipment for testing wafers, aiming to solve the technical problems in the prior art that wafer cracks are prone to occur during wafer testing and the testing function fails due to contact problems.

[0006] To achieve the above object, according to a first aspect of the present application, a method for testing a wafer is provided, the method comprising:

[0007] Obtaining a depth value to be detected and a permissible detection depth value of the wafer;

[0008] If the depth value to be detected is greater than the allowed detection depth value, dividing the depth value to be detected into at least two sub-depth values ​​according to the allowed detection depth value, wherein each of the sub-depth values ​​is smaller than the allowed detection depth value;

[0009] During the test process of the wafer, the wafer is detected according to the test stages corresponding to at least two of the sub-depth values, to obtain detection results corresponding to at least two of the test stages;

[0010] Based on the detection results corresponding to at least two of the test stages, a final test result of the wafer is determined.

[0011] Optionally, in a possible implementation manner of the first aspect, obtaining a to-be-detected depth value and an allowed detection depth value of a wafer includes:

[0012] Acquire product information of the wafer, wherein the product information includes at least one of the following: product model, material properties, and test layer thickness;

[0013] Acquiring probe information of a probe, wherein the probe is used to detect the product quality of the wafer by inserting the probe into the wafer, and the probe information includes at least one of the following: product model, shape, elasticity and material properties;

[0014] According to the product information and the probe information, a depth value to be detected and an allowable detection depth value of the wafer are determined.

[0015] Optionally, in a possible implementation manner of the first aspect, detecting the wafer according to the test stages corresponding to the at least two sub-depth values ​​to obtain the detection results corresponding to the at least two test stages respectively includes:

[0016] According to at least two of the sub-depth values, the test process of the wafer is divided into at least two test stages, wherein at least two of the test stages are consecutive and each of the test stages corresponds to a sub-depth value;

[0017] In at least two of the test stages, the wafer is detected according to the sub-depth value corresponding to each of the test stages to obtain detection results corresponding to each of the at least two test stages.

[0018] Optionally, in a possible implementation manner of the first aspect, dividing the test process of the wafer into at least two test phases according to the at least two sub-depth values ​​includes:

[0019] determining a number of at least two of the sub-depth values;

[0020] Based on the number of at least two of the sub-depth values, the test process of the wafer is divided into at least two test phases corresponding to the number.

[0021] Optionally, in a possible implementation manner of the first aspect, in at least two of the test stages, detecting the wafer according to the sub-depth value corresponding to each of the test stages to obtain detection results corresponding to at least two of the test stages respectively includes:

[0022] determining an execution order of each of the at least two test phases;

[0023] According to the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages, the wafer is detected to obtain detection results corresponding to at least two of the test stages.

[0024] Optionally, in a possible implementation manner of the first aspect, detecting the wafer according to the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages to obtain detection results corresponding to at least two of the test stages respectively includes:

[0025] Obtaining a starting position of a probe for detecting the wafer;

[0026] According to the starting position of the probe, the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages, the probe is controlled to detect the wafer to obtain detection results corresponding to at least two of the test stages.

[0027] Optionally, in a possible implementation manner of the first aspect, the method further includes:

[0028] Before testing the wafer, the position where the probe contacts the surface of the wafer is used as the starting position of the probe.

[0029] Optionally, in a possible implementation manner of the first aspect, the method further includes:

[0030] Before testing the wafer, if there are multiple probes, control the multiple probes to contact the surface of the wafer in sequence;

[0031] Measuring a first height when a first probe among the plurality of probes contacts the surface of the wafer, and a second height when a second probe contacts the surface of the wafer, wherein the first probe is the first probe among the plurality of probes to contact the surface of the wafer, and the second probe is the last probe among the plurality of probes to contact the surface of the wafer;

[0032] determining a height difference between the first height and the second height;

[0033] When it is determined, based on the comparison result between the height difference value and the preset standard deviation value, that at least one of the multiple probes is not parallel to the surface of the wafer, the height and / or position of at least one of the probes is adjusted until the multiple probes are parallel to the surface of the wafer.

[0034] According to a second aspect of the present application, a device for testing a wafer is provided, the device comprising:

[0035] An acquisition unit, used for acquiring a depth value to be detected and a permissible detection depth value of the wafer;

[0036] a dividing unit, configured to divide the depth value to be detected into at least two sub-depth values ​​according to the allowed detection depth value if the depth value to be detected is greater than the allowed detection depth value, wherein each of the sub-depth values ​​is smaller than the allowed detection depth value;

[0037] A detection unit, used for detecting the wafer according to the test stages corresponding to at least two of the sub-depth values ​​during the test of the wafer, and obtaining detection results corresponding to at least two of the test stages;

[0038] A determination unit is used to determine a final test result of the wafer based on the detection results corresponding to at least two of the test stages.

[0039] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the methods described above when executing the computer program.

[0041] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and wherein the computer program implements any of the methods described above when executed by a processor.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device executes any one of the methods described in the first aspect.

[0043] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0044] By the method, device and electronic device for testing wafers provided by the embodiments of the present application, the method for testing wafers is to determine the depth value to be detected of the wafer before the wafer test begins, that is, the depth at which the probe is expected to penetrate the wafer. At the same time, the allowed detection depth value is determined, which can be understood as the maximum safe depth set based on the material characteristics of the wafer and the test requirements to prevent damage to the wafer. If the depth value to be detected exceeds the allowed detection depth value, the depth value to be detected will be divided into at least two smaller sub-depth values, each of which is less than the allowed detection depth value, to ensure that the wafer will not be damaged during the detection process. During the test process, the probe will perform multi-stage detection according to each sub-depth value, and each test stage will obtain a detection result, which reflects the performance of the wafer at different depths. Finally, based on the detection results of each test stage, a comprehensive analysis can be performed to determine the final test result of the wafer, and then based on the final test result, it can be determined whether the wafer meets the quality standard or whether further processing is required. By testing the wafer by this staged detection method, while ensuring the integrity of the wafer, its electrical performance can be accurately evaluated, and the quality of wafer production can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 is a schematic flow chart of a method for testing a wafer provided in an embodiment of the present application;

[0047] Figure 2 is a schematic diagram of the structure of an automated testing system to which the method for testing a wafer provided in an embodiment of the present application is applicable;

[0048] Figure 3 It is a schematic diagram of a wafer testing scenario to which the method for testing a wafer provided in an embodiment of the present application is applicable;

[0049] Figure 4 is a schematic diagram of an optional scenario for determining a starting position of a probe provided in an embodiment of the present application;

[0050] Figure 5 is a schematic flow chart of an optional method for testing a wafer provided in an embodiment of the present application;

[0051] Figure 6 is a schematic diagram of the structure of a device for testing wafers provided in an embodiment of the present application;

[0052] Figure 7 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0054] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0055] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0056] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0057] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0058] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0059] First, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art.

[0060] Microelectromechanical systems (MEMS) chips are a type of chip that combines microelectronics and micromechanics to create mechanical structures and electronic devices at the micron or nanometer scale. The characteristics of MEMS chips include miniaturization, high precision, low power consumption, and low cost, making them widely used in sensors, actuators, optical devices, and other fields. They can be figuratively understood as a micron or nanometer-scale mechanical system that can convert external physical and chemical signals into electrical signals.

[0061] Complementary metal oxide semiconductor image sensor (CMOS image sensor, CIS), also known as CMOS image sensor, is an optical sensor whose function is to convert light signals into electrical signals and convert them into digital signals through readout circuits. It is widely used in the field of vision and is the core component of camera modules.

[0062] OD: overdrip, which is the depth of the probe penetrating into the wafer surface.

[0063] The above is a brief introduction to the nouns involved in the embodiments of the present application, which will not be repeated below.

[0064] The development of the semiconductor industry chain has formed a relatively complete process flow from chip design, simulation, wafer fab tape-out, mid-stage testing, chip packaging, back-end testing, to product shipment. Among them, the testing link is a link that requires more precision compared to the processing procedures. There are strict requirements for factors such as equipment parameter settings, equipment accuracy, personnel operation specifications, process operation environment control, and design rationality. Especially in recent years, with the emergence of new chips such as complementary metal oxide semiconductor image sensors CI S, micro-electromechanical systems MEMS, and memory FLASH, the test specifications are more miniaturized, efficient, and standardized, and the requirements for testing technology are higher and faster.

[0065] MEMS wafer testing is a key step in the semiconductor manufacturing process. It is used to verify the integrity, component characteristics, connections and packaging of the microstructure designed on the wafer, thereby evaluating and ensuring the quality and performance of MEMS devices during the production process.

[0066] However, since wafers made based on MEMS technology are characterized by high hardness and are not easy to pierce, wafer cracks are likely to occur during the wafer testing process, and the test function may fail due to contact problems, resulting in reduced wafer product yield and prone to quality accidents.

[0067] To solve the above problems, the embodiment of the present application provides a wafer testing solution, which can solve the problem that the MEMS wafer may crack due to the high hardness of the product during testing, and the test function may fail due to contact problems, and can ensure the quality and test function of the MEMS wafer during testing, and can be flexibly adjusted according to different scenarios. It is highly practical and easy to operate.

[0068] Please refer to Figure 1 As shown, Figure 1 A schematic flow chart of a method for testing a wafer provided in the present application is shown. As an example but not a limitation, the method can be applied to the above-mentioned mobile phone 100.

[0069] S101, obtaining a depth value to be detected and a permissible detection depth value of a wafer.

[0070] S102: If the depth value to be detected is greater than the allowed detection depth value, the depth value to be detected is divided into at least two sub-depth values ​​according to the allowed detection depth value, wherein each sub-depth value is smaller than the allowed detection depth value.

[0071] S103, during the wafer testing process, detecting the wafer according to the testing stages corresponding to the at least two sub-depth values, and obtaining detection results corresponding to the at least two testing stages.

[0072] S104, determining a final test result of the wafer based on the detection results corresponding to at least two test stages.

[0073] It is easy to understand that wafer manufacturing is a link in the semiconductor manufacturing process (chip manufacturing process), and wafer testing CP (Chip Probing) is between wafer manufacturing and packaging. Therefore, the method for testing the wafer provided in the example of this application can be performed after the wafer is manufactured and before the wafer is packaged.

[0074] Please refer to Figure 2 The schematic diagram of the automated testing system shown in the figure shows the connection relationship between the tester, probe card, wafer and probe station. The main function of the probe station is to carry the wafers to be tested and automatically transfer the wafers to the test position one by one, so that the probes on the probe card can be connected to the chip pins of the wafer at the test position. The tester applies input signals to the chips in the wafer and collects output signals to determine whether the chip functions and performance meet the design specifications under different working conditions.

[0075] Optionally, in the example of the present application, the depth value to be detected (OD value) of the above-mentioned wafer refers to the total depth value required for detection in this test, which is calculated based on product information based on the wafer and probe information of the probe.

[0076] It should be understood that the depth value to be detected of the wafer is directly related to the accuracy of the wafer test and the integrity of the wafer. If the depth value to be detected is set too small, the probe may not be able to effectively contact the test point on the wafer, thereby affecting the test results; if the depth value to be detected is set too large, the wafer or device may be damaged, resulting in test failure. Therefore, it is necessary to accurately calculate and strictly control the depth value to be detected. For example, in the example of this application, the depth value to be detected of the wafer can be determined based on the product information of the wafer and the probe information of the probe to ensure the successful execution of the wafer test.

[0077] Optionally, in the example of this application, the above-mentioned allowable detection depth value refers to the maximum depth value that the probe is allowed to contact the test point on the wafer without damaging the wafer. For example, according to the material characteristics of the wafer, when the one-time needle insertion depth exceeds 45um, the wafer surface is prone to cracks and cause quality accidents, so the allowable detection depth value can be determined as 45um.

[0078] Since wafers are made of different materials, they have different layer structures and hardnesses. These material properties determine the sensitivity and tolerance of the wafer to the probe pressure. In order to avoid cracks on the wafer surface and cause quality accidents, during wafer testing, if the depth value to be detected is greater than the allowable detection depth value, the depth value to be detected is divided into at least two sub-depth values ​​according to the allowable detection depth value, where each sub-depth value is less than the allowable detection depth value.

[0079] In an optional example, if during a test of a MEMS wafer, based on the wafer product information and the probe information of the probe, it is determined that the depth value to be detected of the wafer is 50um; that is, the depth value that needs to be penetrated into the wafer is 50um; and due to the characteristics of the MEMS wafer, when the depth value of the needle penetrating into the wafer at one time exceeds 45um, cracks are prone to occur on the wafer surface, causing quality accidents, that is, the allowable detection depth value is 45um. Therefore, the depth value to be detected 50um can be divided into two sub-depth values, namely two 25um, the first 25um corresponds to the first test stage, and the second 25um corresponds to the second test stage.

[0080] Please refer to Figure 3 As shown, Figure 3It is a schematic flow chart of an optional method for testing wafers provided by an embodiment of the present application. In order to avoid damage to the wafer caused by a one-time penetration too deep, in the first test stage, the probe penetrates the wafer 25um (the first sub-depth value) through the contact point on the wafer surface. At this time, the wafer is safe and will not produce cracks; then the probe (arrow pointing down) returns to the starting position, and at the same test point, the second test stage is performed. The probe penetrates the wafer 25um (the second sub-depth value) through the contact point on the wafer surface at the same test point. In the second test stage, the actual impact or the actual newly added depth value is only 25um. Since the first sub-depth value of 25um has been penetrated at the same test point in the first test stage, this 25um will no longer be affected by the blocking of the aluminum layer. Therefore, when the probe is controlled to be inserted into the test point again in the second stage, it is also safe to pass through the first sub-depth value of 25um, and the wafer will not be damaged or cracked. In addition, the depth value inserted into the wafer in the two test stages is the depth value to be detected 50um, which can meet the needs of effective wafer testing. Therefore, during the wafer testing process, the wafer is detected according to the test stages corresponding to the two sub-depth values, and the detection results corresponding to the two test stages are obtained, which reflect the electrical properties and structural integrity of the wafer at different depths; finally, based on the detection results corresponding to the two test stages, the final test results of the wafer can be determined, so as to divide the wafer into different quality grades according to whether the test results meet the quality standard requirements.

[0081] In one example, probe testing of wafers, also known as wafer level testing, is mainly used to detect circuit performance and structure on semiconductor wafers. Specifically, wafer testing may include but is not limited to the following aspects:

[0082] Circuit parameter detection: Measure the voltage, current, frequency, power and other parameters of the circuit on the wafer to determine the performance characteristics of the circuit.

[0083] Circuit structure check: Check the structure of the circuit on the wafer to determine whether the circuit structure is correct.

[0084] Wafer packaging measurement: used to measure the structure of wafer packaging to determine the quality of the packaging.

[0085] Wafer surface inspection: Checks for contaminants on the wafer surface to determine the quality of the wafer surface.

[0086] The working principle of the probe test is to place the probe on the surface of the wafer. When the probe touches the surface of the wafer, the wire of the probe connects the circuit of the wafer, so that the parameters and structure of the circuit on the wafer can be measured.

[0087] Through the example of this application, it can be ensured that the depth of the probe penetrating into the wafer during the wafer testing process is appropriate and the wafer is not damaged, and it can also be ensured that the probe reaches the depth value to be detected and effectively contacts the test point on the wafer. Therefore, the electrical performance of the wafer can be effectively tested without damaging the wafer, ensuring the accuracy of the wafer test results and the integrity of the wafer.

[0088] In this application example, the entire test process is controlled by an automated system without manual intervention, which improves the efficiency and repeatability of wafer testing. It can reduce the problems of wafer cracks and test function failures caused by high hardness, thereby improving product quality and reliability. In addition, this automated testing method can also help reduce quality accidents and meet the needs of different MEMS products.

[0089] Optionally, in an example of the present application, in a possible implementation, obtaining a depth value to be detected and a depth value allowed to be detected of a wafer includes:

[0090] Obtain product information of the wafer, wherein the product information includes at least one of the following: product model, material properties and test layer thickness; obtain probe information of the probe, wherein the probe is used to detect the product quality of the wafer by inserting the wafer, and the probe information includes at least one of the following: product model, shape, elasticity and material properties; determine the depth value to be detected and the allowable detection depth value of the wafer based on the product information and the probe information.

[0091] It can be understood that in the example of the present application, the probe card, as a key component in semiconductor manufacturing, is used as the interface between the tester and the chip under test during the wafer testing process. It is mainly responsible for the preliminary measurement of the electrical performance before the chip is sliced ​​and packaged, as well as for screening potential defective chips for subsequent packaging.

[0092] Optionally, the probe card mainly includes: a printed circuit board (PCB), probes and functional components, and sometimes also includes electronic components and a reinforcement board (Stiffener). The probe card can have only one probe, which is used to detect the product quality of the wafer by inserting it into the wafer, or it can have hundreds or even thousands of probes to meet the requirements of integrated circuit or simultaneous multi-point wafer testing.

[0093] It is understandable that the probe information includes at least one of the following: product model, shape, elasticity and material properties. The probe information can determine the pressure resistance of the probe, that is, the range that can be tolerated or inserted. For example, probes of different models may have different sizes, shapes and elastic properties, which will affect the pressure and depth required for the probe to contact the wafer. In the product information of the wafer, the test layer thickness is the thickness of the aluminum layer of the wafer. If the detection depth exceeds the test layer thickness, the circuit will be damaged. If the detection depth is far less than the test layer thickness, poor contact will occur. The material properties used to make the aluminum layer of the wafer are hard and brittle, and are prone to cracks. Based on different product models, some wafers have physical properties such as high viscosity and softness.

[0094] Therefore, in the example of the present application, the depth value to be detected and the allowable detection depth value of the wafer can be determined through comprehensive consideration based on the product information of the wafer and the probe information of the probe.

[0095] Optionally, in a possible implementation, detecting the wafer according to the test phases corresponding to the at least two sub-depth values, and obtaining the detection results corresponding to the at least two test phases, respectively, includes:

[0096] According to the at least two sub-depth values, the wafer testing process is divided into at least two testing stages, wherein the at least two testing stages are continuous and each testing stage corresponds to a sub-depth value.

[0097] In at least two testing stages, the wafer is detected according to the sub-depth value corresponding to each testing stage to obtain detection results corresponding to the at least two testing stages.

[0098] Before the test begins, if it is determined that the depth value to be detected exceeds the allowable detection depth value, the depth value to be detected is divided into two or more sub-depth values. These sub-depth values ​​determine the depth to which the probe penetrates the wafer at each test stage. Then, the wafer test process is divided into a corresponding number of stages based on these sub-depth values. Each stage corresponds to a specific sub-depth value, and these stages are performed continuously.

[0099] In each test stage, the probe is inserted into the wafer for detection according to the corresponding sub-depth value. In this way, the depth of the probe inserted into the wafer for detection can be increased step by step, rather than inserting it too deep at one time, thereby reducing potential damage to the wafer. After each test stage is completed, a detection result will be obtained to determine the electrical performance and structural integrity of the wafer at different depths based on the detection results of different test stages.

[0100] This phased probing method can more accurately assess the quality of the wafer while avoiding wafer crack damage that may be caused by a one-time probe penetrating too deep. This method is particularly suitable for MEMS wafers with higher hardness to avoid cracks or damage during the test process.

[0101] Optionally, in a possible implementation manner, the wafer testing process is divided into at least two testing phases according to at least two sub-depth values, including:

[0102] Determine the number of at least two sub-depth values; and based on the number of at least two sub-depth values, divide the wafer testing process into at least two testing phases corresponding to the number.

[0103] In a possible implementation of wafer-level testing, the test process is divided into at least two test phases. The automated test system will divide the depth value to be detected into multiple sub-depth values ​​required for the wafer to be tested based on the size relationship between the depth value to be detected and the allowable detection depth value of the wafer, and each sub-depth value is smaller than the allowable detection depth value. In addition, the depth value to be detected can be divided into more or fewer sub-depth values ​​based on the physical properties of the wafer and the test requirements. For example, if the wafer material is harder, more sub-depth values ​​may be required to gradually increase the depth of the probe to avoid damage.

[0104] Once the number of sub-depth values ​​is determined, the test process will be divided into a corresponding number of test stages. Each test stage will use a corresponding sub-depth value for detection. The purpose of this is to gradually approach the final required depth value to be detected while reducing potential damage to the wafer.

[0105] For example, if two sub-depth values ​​are determined, the test process will be divided into two stages: In the first test stage, the probe may penetrate 25um into the wafer. In the second test stage, the probe may penetrate another 25um, bringing the total depth value to be probed to 50um. This phased testing method allows the test system to evaluate the performance of the wafer at the end of each stage, thereby obtaining accurate test data at different probing depths, and also helps to identify problems that may occur in the wafer at a specific depth, thereby improving the quality and efficiency of the entire test process.

[0106] Optionally, in a possible implementation, in at least two test stages, the wafer is detected according to the sub-depth value corresponding to each test stage to obtain detection results corresponding to each of the at least two test stages, including:

[0107] determining an order of execution of each of the at least two test phases;

[0108] According to the execution order of each test stage and the sub-depth value corresponding to each test stage, the wafer is detected to obtain detection results corresponding to at least two test stages.

[0109] In the above optional implementation, the test process is subdivided into at least two test phases, each test phase has a corresponding sub-depth value, and these sub-depth values ​​determine the depth to which the probe penetrates into the wafer in each test phase.

[0110] For example, based on the considerations of optimizing the test process and ensuring that the wafer is not damaged, the automated test system will determine the execution order of each test stage. For example, a shallow test stage may be performed first, followed by a deeper test stage.

[0111] According to the execution order of each test stage and the corresponding sub-depth value, at each stage, the probe will penetrate the wafer according to the predetermined sub-depth value, perform the test, and record the corresponding detection results of the test stage, thus providing the performance information of the wafer at different depths. The quality of the wafer can be evaluated more accurately, while avoiding possible damage caused by the probe penetrating too deep.

[0112] Please refer to Figure 4 As shown, Figure 4 This is a schematic diagram of an optional scenario for determining the starting position of the probe provided in an embodiment of the present application. In an optional implementation, the above method also includes: before testing the wafer, the position when the probe contacts the surface of the wafer is used as the starting position of the probe (it can also be understood as the zero position, that is, the detection depth value of the probe to the wafer is zero at this position).

[0113] In one example, in actual operation, the probe station will fix the wafer on a stable chuck, and then accurately control the wafer to move up so that the predetermined test point on the wafer contacts the probe. Or control the probe to move down to contact the predetermined test point on the wafer. The probe system is usually connected to the automated test equipment ATE through a special hardware interface to ensure that each probe can accurately touch the same position.

[0114] During wafer testing, the starting position of the probe contacting the wafer refers to the precise position where the probe first contacts the wafer surface. This position is the reference point for all subsequent test measurements, and ensuring the correct contact between the probe and the wafer is critical to the accuracy of the test. Before each probe is inserted into the wafer, it is necessary to determine the position where the probe contacts the surface of the wafer as the starting position of the probe to ensure the consistency and reliability of the test.

[0115] Optionally, in a possible implementation, according to the execution order of each test stage and the sub-depth value corresponding to each test stage, the wafer is detected to obtain detection results corresponding to at least two test stages, including:

[0116] The starting position of the probe used to detect the wafer is obtained; according to the starting position of the probe, the execution order of each test stage and the sub-depth value corresponding to each test stage, the probe is controlled to detect the wafer to obtain detection results corresponding to at least two test stages.

[0117] In the example of this application, the starting position of the probe is obtained, that is, the precise position when the probe contacts the wafer surface is determined. This position is defined as the starting position of the probe and is the reference point for all depth measurements during the test. Specifically, in each test stage, the probe starts from the starting position and detects the wafer according to the execution order of each test stage and the sub-depth value corresponding to each test stage to obtain the detection result corresponding to the test stage. After that, the probe returns to the starting position to prepare for the probe of the next test stage or the probe also returns to the starting position after the end.

[0118] Through this method, the wafer can be accurately probed at different depths to evaluate the electrical performance and structural integrity of the wafer. This process helps to optimize the test process, reduce the risk of wafer damage, and improve test efficiency.

[0119] Please refer to Figure 5 As shown, Figure 5 This is a schematic flow chart of an optional method for testing a wafer provided in an embodiment of the present application, to ensure that the probe can evenly contact each test point on the wafer during the test process, thereby providing reliable test results. As an optional implementation, the method also includes:

[0120] S501, before testing the wafer, when there are multiple probes, control the multiple probes to contact the surface of the wafer in sequence.

[0121] The probe is suspended, that is, the probe is still some distance away from the wafer surface and has not yet touched the wafer. In step S501, the probe station controls multiple probes to be lowered in a specific order so that they contact the wafer surface in turn, so that each probe can contact the wafer at the correct position and angle, laying the foundation for accurate testing.

[0122] S502 , measuring a first height of a first probe of a plurality of probes when it contacts the surface of a wafer, and a second height of a second probe when it contacts the surface of the wafer.

[0123] The first probe is the first probe among the multiple probes to contact the surface of the wafer, and the second probe is the last probe among the multiple probes to contact the surface of the wafer.

[0124] In the above steps, the probe station measures the height of the first probe that contacts the wafer surface (the first probe) and the last probe that contacts the surface (the second probe) to evaluate the parallelism of multiple probes, that is, whether all probes contact the wafer on the same horizontal plane.

[0125] S503: Determine a height difference between the first height and the second height.

[0126] S504, when it is determined based on the comparison result between the height difference value and the preset standard deviation value that at least one probe among the multiple probes is not parallel to the surface of the wafer, adjust the height and / or position of at least one probe until the multiple probes are parallel to the surface of the wafer.

[0127] In the above steps, the probe station calculates the height difference between the first probe and the second probe contacting the wafer surface. If all probes are parallel to the wafer surface, this height difference should be very small or close to zero. If the height difference exceeds the preset standard deviation value (e.g., 0 or other values ​​close to 0), it indicates that multiple probes may not be parallel to the wafer surface. In this case, the probe station needs to adjust the height and / or position of one or more probes until all probes are parallel to the wafer surface to ensure the consistency and accuracy of the test.

[0128] The above method steps ensure that in a test scenario where multiple probes simultaneously probe the wafer, each probe can contact the wafer with the same pressure and depth, thereby providing reliable test results.

[0129] The wafer testing method provided in this application example can ensure that the quality and test function problems of MEMS wafers in testing are effectively solved, thereby ensuring the reliability and performance of the product. In addition to the investment in the system development phase, there is no additional long-term cost. It has a wide range of applicability and can be applied to a variety of MEMS products to improve product quality. Once the automated test system is developed, the test process can be automated, simplifying the operation process.

[0130] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0131] The method for testing a wafer corresponding to the above embodiment, Figure 6 is a schematic diagram of the structure of a device for testing wafers provided in an embodiment of the present application. The device can be implemented as part or all of a computer device by software, hardware, or a combination of both. The computer device can be Figure 7 Electronic equipment shown.

[0132] Reference Figure 6, the device for testing the wafer comprises:

[0133] An acquisition unit 601 is used to acquire a depth value to be detected and a depth value allowed to be detected of the wafer;

[0134] A division unit 602 is used for dividing the depth value to be detected into at least two sub-depth values ​​according to the allowed detection depth value if the depth value to be detected is greater than the allowed detection depth value, wherein each sub-depth value is less than the allowed detection depth value;

[0135] The detection unit 603 is used to detect the wafer according to the test stages corresponding to the at least two sub-depth values ​​during the test process of the wafer, and obtain the detection results corresponding to the at least two test stages;

[0136] The determination unit 604 is used to determine the final test result of the wafer based on the detection results corresponding to the at least two test stages.

[0137] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.

[0138] Further, based on any of the above embodiments, as an example of the present application, the acquisition unit is specifically used to:

[0139] Obtain product information of the wafer, wherein the product information includes at least one of the following: product model, material properties and test layer thickness; obtain probe information of the probe, wherein the probe is used to detect the product quality of the wafer by inserting the wafer, and the probe information includes at least one of the following: product model, shape, elasticity and material properties; determine the depth value to be detected and the allowable detection depth value of the wafer based on the product information and the probe information.

[0140] Further, based on any of the above embodiments, as an example of the present application, the above detection unit is specifically used for:

[0141] According to at least two sub-depth values, the wafer testing process is divided into at least two testing stages, wherein at least two testing stages are continuous and each testing stage corresponds to a sub-depth value; in at least two testing stages, the wafer is detected according to the sub-depth value corresponding to each testing stage, and detection results corresponding to the at least two testing stages are obtained.

[0142] Further, based on any of the above embodiments, as an example of the present application, the above detection unit is specifically used for:

[0143] Determine the number of at least two sub-depth values; and based on the number of at least two sub-depth values, divide the wafer testing process into at least two testing phases corresponding to the number.

[0144] Optionally, in a possible implementation manner of the first aspect, the detection unit is specifically configured to:

[0145] determining an order of execution of each of the at least two test phases;

[0146] According to the execution order of each test stage and the sub-depth value corresponding to each test stage, the wafer is detected to obtain detection results corresponding to at least two test stages.

[0147] Further, based on any of the above embodiments, as an example of the present application, the above detection unit is specifically used for:

[0148] Obtaining a starting position of a probe for detecting the wafer;

[0149] According to the starting position of the probe, the execution order of each test stage and the sub-depth value corresponding to each test stage, the probe is controlled to detect the wafer to obtain detection results corresponding to at least two test stages.

[0150] Further, based on any of the above embodiments, as an example of the present application, the above device also includes:

[0151] The position determination unit is used to use the position where the probe contacts the surface of the wafer as the starting position of the probe before testing the wafer.

[0152] Further, based on any of the above embodiments, as an example of the present application, the above device also includes:

[0153] A control unit, used for controlling the plurality of probes to sequentially contact the surface of the wafer before testing the wafer, when there are a plurality of probes;

[0154] A measuring unit, used to measure a first height when a first probe among a plurality of probes contacts the surface of a wafer, and a second height when a second probe contacts the surface of the wafer, wherein the first probe is the first probe among the plurality of probes to contact the surface of the wafer, and the second probe is the last probe among the plurality of probes to contact the surface of the wafer;

[0155] a difference determination unit, configured to determine a height difference between a first height and a second height;

[0156] The adjustment unit is used to adjust the height and / or position of at least one probe until the multiple probes are parallel to the surface of the wafer when it is determined that at least one probe among the multiple probes is not parallel to the surface of the wafer based on the comparison result between the height difference value and the preset standard deviation value.

[0157] It should be noted that: when the device for testing wafers provided in the above embodiment performs wafer testing, the division of the above-mentioned functional modules is only used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0158] The functional units and modules in the above embodiments may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit, and the above integrated units may be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the embodiments of the present application.

[0159] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0160] An embodiment of the present application further provides an electronic device, the electronic device comprising one or more processors and a memory;

[0161] The memory is coupled to one or more processors, and the memory is used to store computer program codes, the computer program codes include computer instructions, and the one or more processors call the computer instructions to enable the electronic device to execute the aforementioned method for testing wafers.

[0162] The electronic device may be a mobile phone, a smart screen, a tablet computer, a wearable electronic device, an in-vehicle electronic device, an augmented reality (AR) device, a virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a projector, or a communication device such as a server, a storage device, a base station, or a smart car, etc. The embodiments of the present application do not impose any restrictions on the specific types of electronic devices.

[0163] An embodiment of the present application also provides a computer-readable storage medium, in which computer instructions are stored; when the computer-readable storage medium is run on an electronic device, the electronic device executes the method for testing a wafer as shown above.

[0164] Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media integrated therein. Available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media, or semiconductor media (e.g., solid-state drives (SSDs)), etc.

[0165] An embodiment of the present application also provides a computer program product including computer instructions, which, when executed on an electronic device, enables the electronic device to execute the aforementioned method for testing a wafer.

[0166] The computer storage medium and computer program product provided in the above-mentioned embodiments of the present application are used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding beneficial effects of the method provided above, and will not be repeated here.

[0167] In the above embodiments, it can also be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (such as: coaxial cable, optical fiber, data subscriber line (Digital Subscriber Line, DSL)) or wireless (such as: infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server, data center, etc. that contains one or more available media integrations. The available media may be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as digital versatile discs (DVD)), or semiconductor media (such as solid-state drives (SSD)).

[0168] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, which device may be a mobile phone, a computer, a digital broadcast terminal, a message transceiver, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0169] Device 700 may include one or more of the following components: a processing component 702 , a memory 704 , a power component 706 , a multimedia component 708 , an audio component 710 , an input / output (I / O) interface 712 , a sensor component 714 , and a communication component 716 .

[0170] The processing component 702 generally controls the overall operation of the device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 702 may include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0171] The memory 704 is configured to store various types of data to support operations on the device 700. Examples of such data include instructions for any application or method operating on the device 700, contact data, phone book data, messages, pictures, videos, etc. The memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0172] The power supply component 706 provides power to the various components of the device 700. The power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the device 700.

[0173] The multimedia component 708 includes a screen that provides an output interface between the device 700 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the device 700 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0174] The audio component 710 is configured to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), and when the device 700 is in an operating mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 704 or sent via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0175] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0176] The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the device 700. For example, the sensor assembly 714 can detect the open / closed state of the device 700, the relative positioning of components, such as the display and keypad of the device 700, the sensor assembly 714 can also detect the position change of the device 700 or a component of the device 700, the presence or absence of user contact with the device 700, the orientation or acceleration / deceleration of the device 700, and the temperature change of the device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0177] The communication component 716 is configured to facilitate wired or wireless communication between the device 700 and other devices. The device 700 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (I rDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0178] In an exemplary embodiment, the apparatus 700 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above method.

[0179] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, and the instructions can be executed by the processor 720 of the device 700 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0180] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0181] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments applied for herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0182] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0183] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0184] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for testing a wafer, characterized in that: include: Obtaining a depth value to be detected and a permissible detection depth value of the wafer; If the depth value to be detected is greater than the allowed detection depth value, dividing the depth value to be detected into at least two sub-depth values ​​according to the allowed detection depth value, wherein each of the sub-depth values ​​is smaller than the allowed detection depth value; During the test process of the wafer, the wafer is detected according to the test stages corresponding to at least two of the sub-depth values, to obtain detection results corresponding to at least two of the test stages; Based on the detection results corresponding to at least two of the test stages, a final test result of the wafer is determined.

2. The method according to claim 1, characterized in that Obtain the wafer's depth to be detected and the allowed depth to be detected, including: Acquire product information of the wafer, wherein the product information includes at least one of the following: product model, material properties, and test layer thickness; Acquiring probe information of a probe, wherein the probe is used to detect the product quality of the wafer by inserting the probe into the wafer, and the probe information includes at least one of the following: product model, shape, elasticity and material properties; According to the product information and the probe information, a depth value to be detected and an allowable detection depth value of the wafer are determined.

3. The method according to claim 1, characterized in that The step of detecting the wafer according to the test phases corresponding to at least two of the sub-depth values ​​to obtain the detection results corresponding to at least two of the test phases includes: According to at least two of the sub-depth values, the test process of the wafer is divided into at least two test stages, wherein at least two of the test stages are consecutive and each of the test stages corresponds to a sub-depth value; In at least two of the test stages, the wafer is detected according to the sub-depth value corresponding to each of the test stages to obtain detection results corresponding to each of the at least two test stages.

4. The method according to claim 3, characterized in that The step of dividing the wafer testing process into at least two testing phases according to at least two sub-depth values ​​includes: determining a number of at least two of the sub-depth values; Based on the number of at least two of the sub-depth values, the test process of the wafer is divided into at least two test phases corresponding to the number.

5. The method according to claim 3, characterized in that: The step of detecting the wafer in at least two of the test stages according to the sub-depth value corresponding to each of the test stages to obtain detection results corresponding to at least two of the test stages respectively includes: determining an execution order of each of the at least two test phases; According to the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages, the wafer is detected to obtain detection results corresponding to at least two of the test stages.

6. The method according to claim 5, characterized in that According to the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages, the wafer is detected to obtain detection results corresponding to at least two of the test stages, respectively, including: Obtaining a starting position of a probe for detecting the wafer; According to the starting position of the probe, the execution order of each of the test stages and the sub-depth value corresponding to each of the test stages, the probe is controlled to detect the wafer to obtain detection results corresponding to at least two of the test stages.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Before testing the wafer, the position where the probe contacts the surface of the wafer is used as the starting position of the probe.

8. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Before testing the wafer, if there are multiple probes, controlling the multiple probes to sequentially contact the surface of the wafer; Measuring a first height when a first probe among the plurality of probes contacts the surface of the wafer, and a second height when a second probe contacts the surface of the wafer, wherein the first probe is the first probe among the plurality of probes to contact the surface of the wafer, and the second probe is the last probe among the plurality of probes to contact the surface of the wafer; determining a height difference between the first height and the second height; When it is determined, based on the comparison result between the height difference value and the preset standard deviation value, that at least one of the multiple probes is not parallel to the surface of the wafer, the height and / or position of at least one of the probes is adjusted until the multiple probes are parallel to the surface of the wafer.

9. A device for testing a wafer, characterized in that: The device comprises: An acquisition unit, used for acquiring a depth value to be detected and a permissible detection depth value of the wafer; a dividing unit, configured to divide the depth value to be detected into at least two sub-depth values ​​according to the allowed detection depth value if the depth value to be detected is greater than the allowed detection depth value, wherein each of the sub-depth values ​​is smaller than the allowed detection depth value; A detection unit, used for detecting the wafer according to the test stages corresponding to at least two of the sub-depth values ​​during the test of the wafer, and obtaining detection results corresponding to at least two of the test stages; A determination unit is used to determine a final test result of the wafer based on the detection results corresponding to at least two of the test stages.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

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