A test structure layout forming method, test structure and readable storage medium

Abstract

The present invention provides a layout forming method of a test structure, a test structure and a readable storage medium, the method comprising: in a layout, at least two metal layer groups are designed; the metal layer group includes multiple metal layers, and the metal layers in the same metal layer group are provided with the same target pattern; a target metal layer is selected from each of the metal layer groups, and the test structure is formed based on the target pattern in the target metal layer. According to the layout forming method of a test structure provided by this patent, only one layout design of the test structure is required, that is, the performance monitoring under different metal layer selection schemes can be simultaneously met, the test requirements are met to the greatest extent, the design times are saved, and the error rate is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a layout forming method for a test structure, a test structure and a readable storage medium. Background Art

[0002] Chip foundries often provide design companies with a variety of metal layer options to help customers choose the one that best suits them. This means that under the same process, if the customer selects different metal layer options, the same or different lower metal layers may be connected to the same or different upper metal layers using the same through-hole layer.

[0003] When the metal layer selection scheme is different, it is usually necessary to design multiple corresponding test structures to achieve the monitoring of the target performance. Take the connectivity monitoring of through holes as an example. In the semiconductor field, through holes are usually a necessary solution for connecting two adjacent metal layers. Therefore, the test structure used to monitor the connectivity of through holes can reflect the yield of the chip to a certain extent. It is a very important test structure. Since the connectivity monitoring of through holes is very important, any possible connection form should be monitored by a corresponding test structure. When there are multiple metal layer selection schemes, the corresponding test structure must be re-designed for the selected metal layer each time, which greatly wastes efficiency; due to the characteristics of metal selection, only one metal layer connection method may appear in one tape-out. If all possible connection methods are drawn in the layout, there will be no meaning of any test because they will not appear in actual manufacturing, which is equivalent to wasting area. This is extremely uneconomical for masks where area means money.

[0004] Therefore, this patent aims to provide a layout formation method for a test structure, a test structure and a readable storage medium. Only one layout design of the test structure is required to simultaneously monitor the connectivity of through holes under different metal layer selection schemes (or perform other performance tests, such as a capacitor test structure), thereby meeting the test requirements to the greatest extent and saving layout design times, thereby reducing the error rate. Summary of the invention

[0005] In order to solve all or part of the problems of the above-mentioned prior art, the present invention provides a layout formation method of a test structure, a test structure and a readable storage medium to obtain a test structure that can simultaneously meet the performance monitoring requirements under different metal layer selection schemes.

[0006] In a first aspect, a method for forming a layout of a test structure is provided in this embodiment, comprising:

[0007] In the layout, at least two metal layer groups are designed; the metal layer group includes multiple metal layers, and the metal layers in the same metal layer group are provided with the same target pattern; a target metal layer is selected from each metal layer group, and the test structure is formed based on the target pattern in the target metal layer. The layout design of the test structure obtained by this method can ensure that no matter which metal layer selection is finally used, the designed layout design can realize the corresponding performance monitoring, and there is no need to perform repeated layout design, which can save the design time of the test structure layout and reduce the error rate.

[0008] In some of the embodiments, two metal layer groups are designed in the layout; a target metal layer is selected from each of the two metal layer groups, and the test structure is formed based on a target pattern in the target metal layer; the test structure is a capacitor test structure. The capacitor test structure can be obtained through the layout design.

[0009] In some of the embodiments, at least one through-hole layer group is also designed in the layout, and the through-hole layer group includes at least one through-hole layer; the through-hole layers in the same through-hole layer group are provided with the same target through-holes; a target through-hole layer is selected from each through-hole layer group, and the target through-holes in the target through-hole layer are used to connect the target patterns in two adjacent target metal layers; the test structure is formed based on the target patterns in at least two target metal layers and the target through-holes in at least one target through-hole layer; the test structure is a chain test structure. By adding a through-hole layer, a chain resistance test structure can be formed through the through-hole layer and the metal layer connected thereto, which is used to monitor the connectivity of the through-holes.

[0010] In some embodiments, a dummy pattern is further provided in the metal layer of the metal layer group, and the dummy pattern is not connected to the test structure for electrical testing. The metal layers in the same metal layer group are provided with the same dummy pattern or different dummy patterns are provided. Adding dummy patterns can test the density of metal line arrangement in the metal layer and monitor the open circuit of the metal layer.

[0011] In some of the embodiments, forming the test structure based on the target pattern in the target metal layer includes: determining two metal layer groups from the at least two metal layer groups as a first metal layer group and a second metal layer group; setting at least one first port in the target pattern of the metal layer in the first metal layer group; setting at least one second port in the target pattern of the metal layer in the second metal layer group; connecting the at least one first port of the target metal layer in the first metal layer group and the at least one second port of the target metal layer in the second metal layer group for testing the test structure.

[0012] In some of the embodiments, a third metal layer and a fourth metal layer are further designed in the layout, and the third metal layer and the fourth metal layer are the same metal layer or different metal layers; at least one third port is set in the third metal layer, and the first port in each metal layer in the first metal layer group is respectively connected to the corresponding third port; at least one fourth port is set in the fourth metal layer, and the second port in each metal layer in the second metal layer group is respectively connected to the corresponding fourth port; the at least one third port of the third metal layer and the at least one fourth port of the fourth metal layer are connected for testing the test structure.

[0013] In some of the embodiments, the multiple metal layers in the metal layer group are different metal layers; the multiple through-hole layers in the through-hole layer group are different through-hole layers; the differences include at least one of material differences, process differences, design rule differences, node differences, fab differences, and virtual graphic layout differences.

[0014] In a second aspect, a test structure is provided in this embodiment, comprising at least two metal layer groups; the metal layer groups include multiple metal layers, and the metal layers in the same metal layer group are provided with the same target pattern; a target metal layer is determined from each of the metal layer groups, and the test structure is formed based on the target pattern in the target metal layer. The test structure can be obtained according to any one of the layout forming methods of the test structure in the first aspect above.

[0015] In some of the embodiments, the test structure further includes at least one through-hole layer group, the through-hole layer group includes at least one through-hole layer; the through-hole layers in the same through-hole layer group are provided with the same target through-holes; a target through-hole layer is determined from each through-hole layer group, and the target through-holes in the target through-hole layer are used to connect the target patterns in two adjacent target metal layers; the test structure is formed based on the target patterns in at least two target metal layers and the target through-holes in at least one target through-hole layer; the test structure is a chain test structure. The chain test structure can be used to monitor through-hole connectivity.

[0016] According to a third aspect, a computer-readable storage medium is provided in this embodiment, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for forming a layout of a test structure described in any one of the first aspects are implemented.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include the following: the present invention provides a method for forming a layout of a test structure. The layout design of the test structure obtained by this method can ensure that no matter which metal layer selection is finally used, the designed layout design can achieve corresponding performance monitoring, and there is no need for repeated layout design, which can save the design time of the test structure and reduce the error rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 A schematic diagram of a layout design of a test structure provided in Embodiment 1 of the present invention.

[0020] Figure 2 A schematic diagram of a layout design of a test structure when a dummy is added provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0021] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0022] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0023] In the semiconductor field, through-holes are usually necessary solutions for connecting two adjacent metal (wiring) layers. There can be multiple solutions for metal layers, so that customers can choose the one that best suits them. The purpose of the present invention is to provide a layout formation method, by which a layout design of a set of test structures can be designed when there are multiple metal layer selection schemes, so that no matter which metal layer selection is finally used, the designed layout design can achieve corresponding performance monitoring. However, in some other embodiments, there may also be multiple selection schemes for the through-hole layer, and this patent does not impose specific restrictions.

[0024] Embodiment 1:

[0025] In this embodiment, a layout forming method of a test structure based on a certain via layer Vn used to connect upper and lower metal layers is provided.

[0026] In this embodiment, there are three options for the lower metal layer Mn of the through-hole layer Vn, namely metal layer Mn_a, metal layer Mn_b and metal layer Mn_c; there are two options for the upper metal layer Mn+1 of the through-hole layer Vn, namely metal layer Mn+1_a and metal layer Mn+1_b. That is, there are 6 possible metal layer selection schemes in this embodiment, but only one of them will be prepared each time the wafer is taped out. Therefore, the previous method is to design the layout of the test structure for the determined metal layer scheme each time a scheme is selected; each time the metal layer scheme is changed, it needs to be redesigned, which is time-consuming and labor-intensive. In order to be able to monitor the connectivity of the through-hole layer Vn in the above 6 possible situations with only one layout design, the layout formation method of the test structure will be described with the following example.

[0027] In this embodiment, the lower metal layer connected to the via layer Vn is the metal layer Mn. There are multiple optional schemes for the metal layer Mn (i.e., metal layer Mn_a, metal layer Mn_b, and metal layer Mn_c). The target graphics set in each optional scheme of the metal layer Mn are the same. The stack of all possible schemes of the metal layer Mn is called a metal layer group, referred to as the first metal layer group. Similarly, the upper metal layer connected to the via layer Vn is the metal layer Mn+1. There may also be multiple optional schemes for the metal layer Mn+1 (i.e., metal layer Mn+1_a and metal layer Mn+1_b). The target graphics set in each scheme are the same. The stack of all possible schemes of the metal layer Mn+1 can be called the second metal layer group. The via layer Vn and the above two metal layer groups are set at the same time in a layout, and a layout such as Figure 1 The layout design of the test structure shown in the figure is a chain test structure, and the layout includes two metal layer groups, each metal layer group includes multiple metal layers, and the metal layers in the same metal layer group are provided with the same target pattern, which can be used for the connectivity test of the through hole Vn.

[0028] like Figure 1 As shown, Figure 1 (a) is a top view of the test structure, in which metal layer 1 is a structure in which three lower metal layers are stacked (corresponding to the first metal layer group), and metal layer 2 is a structure in which two upper metal layers are stacked (corresponding to the second metal layer group). Figure 1(b) is a cross-sectional schematic diagram of the test structure, in which metal layers 3, 4 and 5 correspond to metal layers Mn_a, Mn_b and Mn_c respectively; metal layers 6 and 7 correspond to metal layers Mn+1_a and Mn+1_b respectively. It should be noted that after the metal layer selection scheme is determined, only one metal layer among metal layers 3, 4 and 5 will be selected as metal layer Mn for wafer fabrication, and only one metal layer among metal layers 6 and 7 will be selected as metal layer Mn+1 for wafer fabrication.

[0029] It can be understood that in the layout design of the test structure, there are 6 possible chain test structures of lower metal layer → through hole layer → upper metal layer. The first and last ends of each chain structure are endpoints A and B in the figure, where port A is as shown in the figure. Figure 1 The starting point is shown in (a) in the figure, and port B is as follows Figure 1 The end point shown in (a) in .

[0030] The specific connection method is as follows: at least one first port (corresponding to Figure 1 The metal layer 3, the metal layer 4 and the metal layer 5 are all provided with an endpoint A), and at least one second port (corresponding to Figure 1 The metal layer 6 and the metal layer 7 are both provided with terminal B), and the test structure is connected out for testing through the first port and the second port. In this embodiment, a first port is set in the target pattern of the metal layer Mn_a, the metal layer Mn_b and the metal layer Mn_c, and a second port is set in the target pattern of the metal layer Mn+1_a and the metal layer Mn+1_b, and then the test structure is connected out for testing through the first port and the second port.

[0031] In order to realize the connection of the first port and the second port, a third metal layer and a fourth metal layer are additionally designed in the layout, and at least one third port ( Figure 1 Not shown, but marked as "connected to the same port A", the same port A refers to the third port), the first port in each metal layer in the first metal layer group is connected to the corresponding third port; at least one fourth port ( Figure 1It is not drawn in the figure, but is marked as "connected to the same port B", and the same port B refers to the fourth port), and the second port in each metal layer in the second metal layer group is respectively connected to the corresponding fourth port; finally, the test structure is connected through the third port and the fourth port for testing. In this embodiment, the first ports set in the target graphics of the metal layer Mn_a, the metal layer Mn_b and the metal layer Mn_c are all connected to the third port set in the third metal layer, and the second ports set in the target graphics of the metal layer Mn+1_a and the metal layer Mn+1_b are all connected to the fourth port set in the fourth metal layer, and finally, the test structure is connected through the third port and the fourth port for testing. The third metal layer and the fourth metal layer here can be the same metal layer, such as both are Mn+2 metal layers, or they can be different metal layers, and this patent does not make specific limitations.

[0032] The layout design has been completed above. When the metal layer selection is confirmed later, a target metal layer is selected from the first metal layer group and the second metal layer group as the metal layer Mn and the metal layer Mn+1 respectively; based on the target patterns in the two selected target metal layers and the through-hole patterns in the through-hole layer Vn, the through-holes connect the target patterns in the two target metal layers to form a through-hole connectivity test structure. In this test structure, the through-hole layer Vn constitutes a chain test structure with repeated connection relationships of the lower metal layer Mn→through-hole layer Vn→upper metal layer Mn+1→through-hole layer Vn→lower metal layer Mn. At this time, the structure can be used for basic through-hole connectivity monitoring.

[0033] The layout design of the test structure drawn by the above method can ensure that no matter which metal layer is finally selected, the corresponding test structure exists in the same layout design, and then the corresponding lower metal layer-through hole layer-upper metal layer test structure is obtained during tape-out, and there is no need to re-design the layout each time. The test structure obtained after the actual tape-out is a conventional through-hole connectivity test structure when used, and how to use the test structure to perform through-hole connectivity tests is a common technique. The test methods are all prior art and are not the focus of the present invention, so they will not be repeated here. In other embodiments, the material of the through hole that can be monitored by the test structure is Cu or W, and the material of the metal layer in the test structure can be one or more of Cu, Al, and W.

[0034] In this embodiment, there is only one optional scheme for the through-hole layer Vn. In other embodiments, there may be multiple optional schemes for the through-hole layer Vn, and the stacking of all possible schemes of the through-hole layer Vn is called a through-hole layer group, and the target through-holes set in the optional schemes of each through-hole layer Vn are the same. When the layout design is performed at this time, the through-hole layer group can be designed together. After the layout design is completed, the metal layer and the through-hole layer are determined at the same time, that is, a target metal layer is selected from the first metal layer group and the second metal layer group respectively, and a target through-hole layer is selected from the through-hole layer group, and the target through-holes in the target through-hole layer are used to connect the target graphics in the two adjacent target metal layers, thereby forming a chain test structure.

[0035] In the present embodiment, a method for forming a layout of a test structure when a through-hole layer connects two upper and lower metal layers. Further, in other embodiments, a method for forming a layout of a test structure for designing more through-hole layers and more metal layers can be provided. Specifically, referring to the above method, the stacking of all optional schemes for each metal layer is regarded as a metal layer group, and the stacking of all optional schemes for each through-hole layer is regarded as a through-hole layer group, and then all metal layer groups and through-hole layer groups are designed in the same layout. When the scheme of each through-hole layer and each metal layer is determined, a target metal layer can be selected from each metal layer group, and a target through-hole layer can be selected from each through-hole layer group, and a test structure can be formed based on the target pattern in the target metal layer and the target through-hole in the target through-hole layer.

[0036] In other embodiments, the via layer Vn may not be added to the layout design, that is, a target metal layer (i.e., metal layer Mn and metal layer Mn+1) is selected from the two metal layer groups, and a test structure is formed based on the target patterns in the two target metal layers. The test structure can be used for capacitance monitoring between metal layers.

[0037] In other embodiments, the multiple metal layers constituting each metal layer group are different metal layers, and the multiple through-hole layers constituting the through-hole layer group are different through-hole layers, and the differences may come from at least one of material differences, process differences, design rule differences, node differences, and fab factory differences.

[0038] Embodiment 2:

[0039] The second embodiment is formed on the basis of the first embodiment. The difference between the second embodiment and the first embodiment is that in the second embodiment, dummy metal (ie, virtual pattern) is further added to the metal layer of the metal layer group.

[0040] Specifically, dummy metal can be added to each metal layer scheme, that is, for any metal layer in each metal layer group, dummy metal can be added to the metal layer, and the dummy metals set for the metal layers in the same metal layer group can be the same or different.

[0041] In this embodiment, there are three options for the metal layer Mn below the through-hole layer Vn, namely, metal layer Mn_a, metal layer Mn_b and metal layer Mn_c; there are two options for the metal layer Mn+1 above the through-hole layer Vn, namely, metal layer Mn+1_a and metal layer Mn+1_b; at this time, there are a total of 6 possible metal layer selection options.

[0042] In the above six solutions, dummy metal can be added accordingly. When designing the layout later, the metal layer Mn_a after adding dummy metal, the metal layer Mn_b after adding dummy metal, the metal layer Mn_c after adding dummy metal, the metal layer Mn+1_a after adding dummy metal, and the metal layer Mn+1_b after adding dummy metal will be drawn in the same layout, that is, the layout design of the test structure with dummy metal is obtained. The test structure with dummy metal is as follows. Figure 2 shown.

[0043] In this embodiment, the specific setting method of the dummy metal is not limited and can be determined according to the test requirements or design rules. It is worth noting that the dummy metal and the metal layer on the same layer are not connected to each other, so the dummy metal (virtual graphic) will not be connected to the test structure for electrical testing. However, this feature can be used to perform a short-circuit test on the metal layer, that is, two additional ports are connected to the upper metal dummy metal interface and the lower metal dummy metal interface, and two more short-circuit test structures are formed. The test method is to use the lower metal dummy interface and the starting point (the end point can also be used because the starting point and the end point are connected) as two test ports to test whether there is a short circuit between the metal connectivity monitoring structure (i.e., the chain test structure) and the lower metal; use the upper metal dummy interface, the starting point or the end point as two test ports to test whether there is a short circuit between the metal connectivity monitoring structure and the upper metal.

[0044] In other embodiments, the multiple metal layers constituting each metal layer group are different metal layers, and the multiple through-hole layers constituting the through-hole layer group are different through-hole layers, and the differences may come from at least one of material differences, process differences, design rule differences, node differences, fab differences, and virtual graphic layout differences.

[0045] Embodiment three:

[0046] Embodiment 3 of the present application provides a computer device for implementing the steps of the above-mentioned method for forming a layout of a test structure, or the steps of the above-mentioned method for forming a layout of a test structure, and the computer device may include: a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory communicate with each other through the communication bus; the processor can call the logic instructions in the memory, and the logic instructions in the memory can be implemented in the form of software function units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0047] Embodiment 4:

[0048] Embodiment 4 of the present application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the steps of the above-mentioned method for forming a layout of a test structure, or the steps of the above-mentioned method for forming a layout of a test structure.

[0049] Based on such understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes. Based on such understanding, the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, disk, optical disk, etc., including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform various embodiments or some parts of the embodiments.

Claims

1. A method for forming a layout of a test structure, characterized in that: include: In the same layout, the design has at least two metal layer groups; The metal layer group includes a plurality of metal layers, and the metal layers in the same metal layer group are provided with the same target pattern; The metal layer group is a structure obtained by stacking the multiple metal layers; the multiple metal layers in the metal layer group are metal layers with differences, and the differences include at least one of material differences, process differences, design rule differences, node differences, fab differences, and virtual graphic layout differences; A target metal layer is selected from each of the metal layer groups, and the test structure is formed based on a target pattern in the target metal layer.

2. The method for forming a layout of a test structure according to claim 1, characterized in that: In the layout, there are two metal layer groups designed; Selecting a target metal layer from each of the two metal layer groups, and forming the test structure based on a target pattern in the target metal layer; The test structure is a capacitance test structure.

3. The method for forming a layout of a test structure according to claim 1, characterized in that: In the layout, at least one through-hole layer group is also designed, and the through-hole layer group includes at least one through-hole layer; The through-hole layers in the same through-hole layer group are provided with the same target through-holes; Selecting a target through-hole layer from each of the through-hole layer groups, wherein the target through-holes in the target through-hole layer are used to connect target patterns in two adjacent target metal layers; forming the test structure based on target patterns in at least two target metal layers and target vias in at least one target via layer; The test structure is a chain test structure.

4. The method for forming a layout of a test structure according to claim 1, characterized in that: A dummy pattern is also provided in the metal layer of the metal layer group, and the dummy pattern is not connected to the test structure for electrical testing; The metal layers in the same metal layer group are provided with the same virtual patterns or with different virtual patterns.

5. The method for forming a layout of a test structure according to claim 3, characterized in that: The forming of the test structure based on the target pattern in the target metal layer comprises: determining two metal layer groups from the at least two metal layer groups as a first metal layer group and a second metal layer group; At least one first port is provided in the target pattern of the metal layer in the first metal layer group; At least one second port is provided in the target pattern of the metal layer in the second metal layer group; The at least one first port of the target metal layer in the first metal layer group and the at least one second port of the target metal layer in the second metal layer group are connected for testing the test structure.

6. The method for forming a layout of a test structure according to claim 5, characterized in that: In the layout, a third metal layer and a fourth metal layer are also designed, and the third metal layer and the fourth metal layer are the same metal layer or different metal layers; At least one third port is provided in the third metal layer, and the first port in each metal layer in the first metal layer group is respectively connected to the corresponding third port; At least one fourth port is provided in the fourth metal layer, and the second port in each metal layer in the second metal layer group is respectively connected to the corresponding fourth port; The at least one third port of the third metal layer and the at least one fourth port of the fourth metal layer are connected for testing the test structure.

7. The method for forming a layout of a test structure according to claim 3, characterized in that: The plurality of through-hole layers in the through-hole layer group are different through-hole layers; The difference includes at least one of a material difference, a process difference, a design rule difference, a node difference, a fab factory difference, and a virtual graphic layout difference.

8. A test structure, characterized in that: At least two metal layer groups are included in one layout; the metal layer group includes a plurality of metal layers, and the metal layers in the same metal layer group are provided with the same target pattern; The metal layer group is a structure obtained by stacking the multiple metal layers; the multiple metal layers in the metal layer group are metal layers with differences, and the differences include at least one of material differences, process differences, design rule differences, node differences, fab differences, and virtual graphic layout differences; A target metal layer is determined from each of the metal layer groups, and the test structure is formed based on a target pattern in the target metal layer.

9. A test structure according to claim 8, characterized in that: Also comprising at least one through-hole layer group, the through-hole layer group comprising at least one through-hole layer; The through-hole layers in the same through-hole layer group are provided with the same target through-holes; Determine a target via layer from each of the via layer groups, wherein the target vias in the target via layer are used to connect target patterns in two adjacent target metal layers; forming the test structure based on target patterns in at least two target metal layers and target vias in at least one target via layer; The test structure is a chain test structure.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for forming a layout of a test structure according to any one of claims 1 to 7 are implemented.

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