Method for manufacturing a semiconductor device

Abstract

The present invention discloses a method for manufacturing a semiconductor device, which belongs to the field of semiconductor technology. The manufacturing method includes: providing a substrate, forming a pseudo gate on the substrate; forming a sidewall structure on both sides of the pseudo gate; forming an interlayer dielectric layer on the substrate, the surface of the dielectric layer is flush with the surface of the pseudo gate; removing the pseudo gate to form a recess; forming a first gate dielectric layer at the bottom and sidewall of the recess, the first gate dielectric layer is a high dielectric constant dielectric; forming a second gate dielectric layer on the first gate dielectric layer; annealing the first gate dielectric layer and the second gate dielectric layer; depositing a metal work function layer and a metal layer on the second gate dielectric layer to form a metal gate. Through the manufacturing method of a semiconductor device provided by the present invention, leakage current caused by crystallization of the first gate dielectric layer can be prevented, interface defects can be greatly reduced, stress-induced leakage current can be reduced, and negative bias temperature instability can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for manufacturing a semiconductor device. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, integrated circuit chips are developing towards higher semiconductor device density and higher integration. As the feature size of semiconductor devices continues to shrink, the polysilicon gate process cannot meet the requirements of semiconductor devices. The use of metal gates instead of polysilicon gates can solve problems such as threshold voltage drift, polysilicon gate depletion effect, excessive gate resistance and Fermi level pinning. Among them, in the process of metal gate manufacturing, a high dielectric constant medium is used as the gate dielectric layer. After the high dielectric constant medium is deposited, decoupled plasma nitridation (DPN) and post nitridation annealing (PNA) are performed to improve the interface characteristics between the metal gate and the high-K dielectric, and improve the thermal stability and oxidation resistance of the device. However, it will cause serious crystallization of the high dielectric constant dielectric, leading to problems such as gate leakage and interface defects. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor device. Through the method for manufacturing a semiconductor device provided by the present invention, the thermal stability of a high dielectric constant medium can be increased, leakage current caused by crystallization of the first gate dielectric layer can be prevented, interface defects can be greatly reduced, stress-induced leakage current can be reduced, and negative bias temperature instability can be improved.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0005] Providing a substrate, and forming a dummy gate on the substrate;

[0006] Forming sidewall structures on both sides of the dummy gate;

[0007] forming an interlayer dielectric layer on the substrate, wherein a surface of the dielectric layer is flush with a surface of the dummy gate;

[0008] removing the dummy gate to form a recess;

[0009] Forming a first gate dielectric layer on the bottom and sidewalls of the recess, wherein the first gate dielectric layer is a high dielectric constant dielectric;

[0010] forming a second gate dielectric layer on the first gate dielectric layer;

[0011] performing annealing treatment on the first gate dielectric layer and the second gate dielectric layer; and

[0012] A metal work function layer and a metal layer are deposited on the second gate dielectric layer to form a metal gate.

[0013] In one embodiment of the present invention, the material of the second gate dielectric layer is nitrogen-rich titanium nitride, and the nitrogen content in the second gate dielectric layer is 50%-70%.

[0014] In one embodiment of the present invention, the method for forming the second gate dielectric layer includes: when the temperature of the deposition chamber is, for example, 400°C~600°C, repeatedly introducing titanium source gas and nitrogen source gas, and the flow ratio of the titanium source gas to the nitrogen source gas is 1:30~1:100.

[0015] In one embodiment of the present invention, the thickness of the second gate dielectric layer is greater than 60Å.

[0016] In one embodiment of the present invention, the annealing process is performed in a nitrogen-rich atmosphere, and the gas used in the nitrogen-rich atmosphere includes ammonia, nitrogen or hydrazine.

[0017] In one embodiment of the present invention, the annealing temperature of the annealing treatment is 300° C.-500° C.

[0018] In one embodiment of the present invention, before forming the dummy gate, a gate oxide layer is formed on the substrate, and the thickness of the gate oxide layer is 10Å~12Å.

[0019] In one embodiment of the present invention, the thickness of the first gate dielectric layer is 18Å~20Å.

[0020] In an embodiment of the present invention, the manufacturing method further includes: after forming the dummy gate, forming a lightly doped region in the substrate on both sides of the dummy gate.

[0021] In an embodiment of the present invention, the manufacturing method further comprises: after forming the sidewall structure, forming a heavily doped region in the substrate on a side of the sidewall structure away from the dummy gate.

[0022] In summary, the present invention provides a method for manufacturing a semiconductor device, which can increase the thermal stability of a high dielectric constant medium, prevent the crystallization of the first gate dielectric layer, prevent leakage current caused by the crystallization of the first gate dielectric layer, and avoid nitrogen atoms being enriched at the interface between the first gate dielectric layer and the gate oxide layer, thereby avoiding an increase in interface defects and further improving the performance of the semiconductor device. It can greatly reduce interface defects, reduce stress-induced leakage current, and improve negative bias temperature instability. It can improve the problem of poor interface contact between the first gate dielectric layer and the substrate, and improve the gate's ability to control the channel, adjust the threshold voltage, and reduce leakage current. It can improve the thermal stability and oxidation resistance of the metal gate, and improve the reliability and performance of the semiconductor device. It can simplify the manufacturing process, improve manufacturing efficiency, and reduce the production cost of the enterprise while improving the performance of the semiconductor device.

[0023] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0025] Figure 1 It is a schematic diagram of forming a pad oxide layer, a pad nitride layer and a first photoresist layer on a substrate in one embodiment of the present invention.

[0026] Figure 2 FIG. 4 is a schematic diagram of forming a shallow trench isolation structure in one embodiment of the present invention.

[0027] Figure 3 FIG. 4 is a schematic diagram of forming a well region in an embodiment of the present invention.

[0028] Figure 4 FIG. 4 is a schematic diagram of forming a gate material layer and a hard mask layer in one embodiment of the present invention.

[0029] Figure 5 FIG. 4 is a schematic diagram of forming a dummy gate according to an embodiment of the present invention.

[0030] Figure 6 FIG. 4 is a schematic diagram of forming a lightly doped region in one embodiment of the present invention.

[0031] Figure 7 It is a schematic diagram of forming a sidewall structure, a heavily doped region and a self-aligned metal silicide in one embodiment of the present invention.

[0032] Figure 8It is a schematic diagram of forming a contact hole etching stop layer and a dielectric layer in one embodiment of the present invention.

[0033] Fig. 9 FIG. 4 is a schematic diagram of planarizing a dielectric layer to a first hard mask layer according to an embodiment of the present invention.

[0034] Fig.10 It is a schematic diagram after removing the first hard mask layer and the dummy gate according to an embodiment of the present invention.

[0035] Fig.11 It is a schematic diagram of forming a first gate dielectric layer and a second gate dielectric layer in one embodiment of the present invention.

[0036] Fig.12 FIG. 4 is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0037] Description of labels:

[0038] 10. Substrate; 101. Well region; 11. Pad oxide layer; 12. Pad nitride layer; 13. First photoresist layer; 131. Opening; 14. Shallow trench isolation structure; 15. Gate oxide layer; 16. Gate material layer; 161. Pseudo gate; 17. First hard mask layer; 18. Second hard mask layer; 19. Second photoresist layer; 21. Lightly doped region; 22. Sidewall structure; 23. Heavily doped region; 24. Self-aligned metal silicide layer; 25. Contact hole etch stop layer; 26. Interlayer dielectric layer; 27. Concave portion; 28. First gate dielectric layer; 29. ​​Second gate dielectric layer; 30. Metal gate. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0041] In the description of this specification, it should be understood that the directions or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing this solution and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on this solution. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0042] The present invention provides a method for manufacturing a semiconductor device, which can increase the thermal stability of a high dielectric constant medium when forming a metal gate, prevent leakage current caused by crystallization of the first gate dielectric layer, and avoid nitrogen atoms being enriched at the interface between the first gate dielectric layer and the gate oxide layer, thereby avoiding an increase in interface defects and further improving the performance of the semiconductor device. It can greatly reduce interface defects, reduce stress-induced leakage current, and improve negative bias temperature instability. The semiconductor device prepared by the present invention can be widely used in various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, household appliances, and aerospace.

[0043] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), silicon wafer or other semiconductor materials formed by III / V compounds, etc., and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate. In other embodiments, the type of substrate 10 is selected according to the semiconductor device to be manufactured. The present invention does not limit the type of semiconductor devices, and the semiconductor devices are, for example, field effect transistors (FET), metal-oxide-semiconductor field-effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS), insulated gate bipolar transistors (IGBT), gate turn off thyristors (GTO), or thyristors. In this embodiment, for example, a MOS transistor is taken as an example to describe the method for manufacturing a semiconductor device.

[0044] See also Figure 1As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on the substrate 10. The pad oxide layer 11 can improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12 as a buffer layer. The pad oxide layer 11 is, for example, a material such as dense silicon oxide, and the pad oxide layer 11 can be formed by any one of the methods such as dry oxygen oxidation, wet oxygen oxidation, or in-situ steam growth (ISSG). In this embodiment, the pad oxide layer 11 is formed by, for example, dry oxygen oxidation, and the thickness of the pad oxide layer 11 is, for example, 10nm~40nm. A pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed by, for example, low pressure chemical vapor deposition (LPCVD) and other methods. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm. By providing the pad nitride layer 12, the substrate 10 can be protected from the influence of the planarization process such as chemical mechanical polishing (CMP) involved in the process of manufacturing the shallow trench isolation structure 14. In addition, the pad nitride layer 12 can be used as a mask in the subsequent shallow trench isolation structure formation process to protect the substrate 10 from damage when etching the substrate 10.

[0045] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12, and a plurality of openings 131 are formed on the first photoresist layer 13 through exposure and development processes, and the openings 131 are used to define the position of the shallow trench isolation structure 14. Using the first photoresist layer 13 as a mask, etching is performed to remove the pad nitride layer 12, the pad oxide layer 11 and a portion of the substrate 10 exposed by the opening 131 to form a shallow trench (not shown in the figure). In this embodiment, for example, dry etching is used to form the shallow trench, and after the etching is completed, the first photoresist layer 13 is removed. After the shallow trench is formed, an insulating medium is deposited in the shallow trench until the insulating medium covers the surface of the pad nitride layer 12. In this embodiment, the insulating medium is, for example, silicon oxide. The present invention does not limit the deposition method of the insulating medium. For example, a high-quality insulating medium can be formed by high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio chemical vapor deposition (HARP-CVD). In other embodiments, the insulating medium can also be other insulating materials suitable for isolation and formation methods. After the insulating medium is prepared, the insulating medium is planarized, for example, the insulating medium is planarized by chemical mechanical polishing (CMP). For example, a portion of the insulating medium and a portion of the pad nitride layer 12 are removed by grinding, and then the pad nitride layer 12 is removed to obtain a shallow trench isolation structure 14, and the shallow trench isolation structure 14 is, for example, higher than the pad oxide layer 11 on both sides. The present invention does not limit the removal method of the pad nitride layer 12, for example, it is removed by dry etching, wet etching, or a combination of dry etching and wet etching.

[0046] See also Figures 2 to 3As shown, in one embodiment of the present invention, after the shallow trench isolation structure 14 is prepared, the substrate 10 is ion-implanted with the pad oxide layer 11 as an ion-implanted buffer layer to form a well region 101, wherein the type of ions implanted in the well region 101 is selected according to the type of semiconductor device. In one embodiment of the present invention, when the semiconductor device is, for example, a PMOS transistor, the doped ions in the well region 101 are, for example, N-type doped ions, such as phosphorus (P) or arsenic (As). In another embodiment of the present invention, when the semiconductor device is, for example, an NMOS transistor, the doped ions in the well region 101 are, for example, P-type doped ions, such as boron (B) or gallium (Ga). After the ion implantation, the well region 101 is subjected to a rapid thermal annealing process (RTA) so that the ion implantation diffuses to a suitable depth and improves the avalanche breakdown resistance of the semiconductor device. For another example, wet etching is used to etch the pad oxide layer 11 , and the wet etching solution is, for example, hydrofluoric acid or buffered oxide etchant (BOE).

[0047] See also Figures 3 to 4 As shown, in one embodiment of the present invention, after removing the pad oxide layer, a gate oxide layer 15 is formed on the substrate 10. The gate oxide layer 15 is, for example, a silicon oxide layer, and the gate oxide layer 15 is, for example, formed by thermal oxidation, in-situ water vapor growth method or physical vapor deposition (PVD) and the like. The thickness of the gate oxide layer 15 is, for example, 10Å~12Å. After forming the gate oxide layer 15, a gate material layer 16 is formed on the gate oxide layer 15. The gate material layer 16 includes, for example, polysilicon. In this embodiment, the gate material layer 16 is, for example, formed by chemical vapor deposition, and the thickness of the gate material layer is, for example, 100nm~300nm. A first hard mask layer 17 and a second hard mask layer 18 are sequentially formed on the gate material layer 16, wherein the first hard mask layer 17 is, for example, a silicon nitride layer, and the thickness is, for example, 10nm~20nm, and the second hard mask layer 18 is, for example, a silicon oxide layer, and the thickness is, for example, 20nm~30nm. By setting two hard mask layers, the dummy gate is protected when the sidewall structure, heavily doped area, self-aligned metal silicide layer or contact hole etch stop layer and other structures are subsequently formed, thereby ensuring the height of the dummy gate and thus ensuring the height of the metal gate and improving the height consistency of the subsequent metal gate.

[0048] See also Figures 4 to 5As shown, in one embodiment of the present invention, after forming the second hard mask layer 18, a photoresist layer is formed on the second hard mask layer 18 and then the photoresist is exposed and developed to form a second photoresist layer 19. Then, using the second photoresist layer 19 as a mask, the hard mask layer, the gate material layer 16 and the gate oxide layer 15 are etched by, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process, and the remaining gate material layer 16 is defined as a dummy gate 161. After etching, the second photoresist layer 19 is removed by ashing or wet etching.

[0049] See also Figures 5 and 6 As shown, in one embodiment of the present invention, after forming the dummy gate 161, a lightly doped region 21 is formed in the substrate 10 on both sides of the dummy gate 161. The doping ions in the lightly doped region 21 are formed, for example, by ion implantation, and the type of the implanted ions is opposite to the type of ions in the well region 101. That is, when the semiconductor device is a PMOS transistor, the doping ions in the lightly doped region 21 are, for example, P-type impurities such as boron or gallium, and when the semiconductor device is an NMOS transistor, the doping ions in the lightly doped region 21 are, for example, N-type impurities such as phosphorus or arsenic.

[0050] See also Figure 6 to Figure 7 As shown, in one embodiment of the present invention, after forming the lightly doped region 21, a sidewall structure 22 is formed on both sides of the dummy gate, wherein the sidewall structure 22 is, for example, a stacked structure, and in the process of forming the sidewall structure 22, the second hard mask layer 18 is basically completely consumed. In this embodiment, the sidewall structure 22 is a stack of silicon nitride and silicon oxide, starting from the side close to the dummy gate 161. By setting the interface between the sidewall structure 22 and the dummy gate 161 as a silicon nitride layer, the stability of the sidewall structure 22 can be improved after the dummy gate is removed. In other embodiments, the sidewall structure 22 is, for example, other stacked structures. By setting the sidewall structure 22 as a stacked structure, the uniformity of the dummy gate is improved, thereby ensuring the stability of the threshold voltage of the semiconductor device.

[0051] See also Figure 7As shown, in one embodiment of the present invention, after forming the sidewall structure 22, a heavily doped region 23 is formed in the substrate 10 on the side of the sidewall structure 22 away from the dummy gate 161, and the edge of the heavily doped region 23 is aligned with the side of the sidewall structure 22 away from the dummy gate 161. Among them, through the photoresist process, the area where the heavily doped region 23 needs to be formed is exposed, for example, the heavily doped region 23 is formed by injecting doping ions, and the type of the injected ions is opposite to the type of ions in the well region, that is, the same as the type of ions in the lightly doped region 21, and the doping concentration of the heavily doped region 23 is greater than the doping concentration of the lightly doped region 21, and the doping depth of the heavily doped region 23 is greater than the doping depth of the lightly doped region 21. After forming the heavily doped region 23, the heavily doped region 23 and the lightly doped region 21 are activated, for example, the substrate 10 is subjected to rapid thermal annealing. Through rapid thermal annealing, the lattice defects generated during the manufacturing process can be repaired and the doping ions can be activated, thereby activating the heavily doped region 23 and the lightly doped region 21.

[0052] See also Figures 7 and 8 As shown, in one embodiment of the present invention, after forming the heavily doped region 23, a metal layer (not shown in the figure) is formed on all structures on the substrate 10. Through heat treatment, the metal reacts with the exposed substrate 10, and then the unreacted metal layer is removed to form a self-aligned metal silicide layer 24 on the heavily doped region 23. The self-aligned metal silicide layer 24 can improve the contact resistance of the conductive plugs subsequently formed on the source and drain. After forming the self-aligned metal silicide layer 24, a contact hole etch stop layer 25 is formed on the substrate 10. The contact hole etch stop layer 25 is, for example, silicon nitride. The contact hole etch stop layer 25, for example, covers the sidewall structure 22, the dummy gate 161, the self-aligned metal silicide layer 24 and the shallow trench isolation structure 14. In the subsequent manufacturing process, the etching depth is controlled to prevent the substrate 10 from being over-etched, thereby improving the performance of the semiconductor device.

[0053] See also Figures 8 to 9As shown, in one embodiment of the present invention, after forming the contact hole etch stop layer 25, an interlayer dielectric layer 26 is formed on the substrate 10, and the interlayer dielectric layer 26, for example, covers the dummy gate 161, the sidewall structure 22, the shallow trench isolation structure 14 and the substrate 10. Among them, the interlayer dielectric layer 26 is, for example, a low dielectric constant material such as silicon oxide or silicon fluoride (SiF), silicon oxycarbide (SiOC), silicon oxyfluoride (SiOF), and is obtained, for example, by a chemical vapor deposition method. After forming the interlayer dielectric layer 26, the interlayer dielectric layer 26 is planarized, for example, by chemical mechanical polishing to planarize the interlayer dielectric layer 26. In the polishing process, the first hard mask layer 17 is used as the polishing stop layer, non-selective polishing is used, and the polishing time is controlled to remove the interlayer dielectric layer 26 on the dummy gate 161 and the contact hole etch stop layer 25. After the planarization process, the surface of the interlayer dielectric layer 26, the surface of the first hard mask layer 17, and the surface of the contact hole etch stop layer 25 are flush.

[0054] See also Figures 9 and 10 As shown, in one embodiment of the present invention, after the interlayer dielectric layer 26 is planarized, the first hard mask layer 17 and the dummy gate 161 are removed to form a recess 27 at the position of the dummy gate 161. When removing the first hard mask layer 17 and the dummy gate 161, the gate oxide layer 15 is used as an etching stop layer, and dry etching, wet etching, or a combination of dry etching and wet etching are used. The present invention does not make specific restrictions. In the removal process, the sidewall structure 22 is not destroyed, so as to serve as the sidewall structure of the metal gate prepared later, thereby improving the electrical performance of the semiconductor device.

[0055] See also Figure 10 to Figure 11As shown, in one embodiment of the present invention, after the recess 27 is formed, a first gate dielectric layer 28 is formed on the bottom and sidewalls of the recess, and the first gate dielectric layer 28 is, for example, a high dielectric constant dielectric, and the high dielectric constant dielectric is, for example, hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium oxynitrogen silicate (ZrSiON), hafnium silicate (HfSiO), hafnium oxynitrogen silicate (HfSiON), hafnium lanthanum oxynitride (HfLaON) or hafnium aluminum oxide (HfAlO), etc. One or a mixture of several of the above, and the thickness of the first gate dielectric layer 28 is, for example, 18Å~20Å. The first gate dielectric layer 28 can be formed, for example, by using atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), chemical vapor deposition or physical vapor deposition. A gate oxide layer 15 is provided between the first gate dielectric layer 28 and the substrate 10 to improve the poor interface contact between the first gate dielectric layer 28 and the substrate, and to improve the control capability of the gate over the channel, adjust the threshold voltage and reduce the leakage current.

[0056] See also Fig.11As shown, in one embodiment of the present invention, after forming the first gate dielectric layer 28, a second gate dielectric layer 29 is formed on the first gate dielectric layer 28. The second gate dielectric layer 29 is, for example, nitrogen-rich titanium nitride, and the nitrogen content in the second gate dielectric layer 29 is, for example, 50% to 70%. In this embodiment, the second gate dielectric layer 29 is prepared by, for example, physical vapor deposition or atomic layer deposition, and the thickness of the second gate dielectric layer 29 is, for example, greater than 60Å, and for example, less than or equal to 150Å. In one embodiment of the present invention, for example, the second gate dielectric layer 29 is formed by atomic layer deposition, and the temperature of the deposition chamber is, for example, 400°C to 600°C, and titanium source gas and nitrogen source gas are repeatedly introduced, the titanium source gas includes, for example, at least one of gaseous titanium tetrachloride or (C5H5)Ti(C7H7) (CPCHT), and the nitrogen source gas includes, for example, ammonia or a mixture of nitrogen and hydrogen, and the flow ratio of the titanium source gas to the nitrogen source gas is, for example, 1:30 to 1:100, so as to obtain nitrogen-rich titanium nitride, which can improve the thermal stability and oxidation resistance of the metal gate, and improve the reliability and performance of the semiconductor device. By increasing the thickness of the second gate dielectric layer 29 and setting it as a nitrogen-rich layer, the interface defects (Dit) can be greatly reduced, the stress induced leakage current (SILC) can be reduced, and the negative bias temperature instability (NBTI) can be improved.

[0057] See also Fig.11 As shown, in one embodiment of the present invention, before forming the second gate dielectric layer 29, for example, in a nitrogen-rich atmosphere, the first gate dielectric layer 28 and the second gate dielectric layer 29 are annealed, wherein the annealing temperature is, for example, 300°C to 500°C, the heating time is, for example, 20s to 40s, and the gas used in the nitrogen-rich atmosphere includes, for example, ammonia, nitrogen, or hydrazine, etc., oxygen-free gas, so as to avoid oxidation of the second gate dielectric layer 29 and reduce defects in the second gate dielectric layer 29. At the same time, during the annealing process, some nitrogen atoms in the second gate dielectric layer 29 will enter the first gate dielectric layer 28, which can increase the thermal stability of the high dielectric constant medium, prevent the first gate dielectric layer 28 from crystallizing, and prevent leakage current caused by the crystallization of the first gate dielectric layer 28. At the same time, controlling the annealing temperature and annealing time can further avoid crystallization of the first gate dielectric layer 28, and at the same time avoid nitrogen atoms from being enriched at the interface between the first gate dielectric layer 28 and the gate oxide layer 15, avoid increasing interface defects, and further improve the performance of the semiconductor device. At the same time, compared with performing DNP and PNA processes after depositing the first gate dielectric layer 28, annealing is performed after depositing the second gate dielectric layer 29, which can improve the performance of the semiconductor device while simplifying the manufacturing process, improving manufacturing efficiency and reducing enterprise production costs.

[0058] See also Figure 11 to Figure 12 As shown, in one embodiment of the present invention, after annealing, a plurality of metal work function layers and metal conductive layers (not shown in the figure) are deposited on the second gate dielectric layer 29, and the metal conductive layer is arranged on the plurality of metal work function layers until the recess 27 is completely filled to form a metal gate 30. Among them, the material of the metal work function layer is, for example, one or a stack of tantalum nitride (TaN), titanium nitride, titanium aluminide (TiAl), titanium aluminum nitride (TiAIN) or tungsten nitride (WN), and the metal work function layer is formed by, for example, plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition or physical vapor deposition. Among them, the number of layers and materials of the metal work function layer are selected according to the type of semiconductor device to meet the threshold voltage requirements of different semiconductor devices. The metal conductive layer is, for example, a metal material with good conductivity such as metal aluminum, tungsten, copper or silver. After the metal gate 30 is formed, for example, a conductive plug and a metal wiring layer are made, which will not be elaborated here.

[0059] In summary, the present invention provides a method for manufacturing a semiconductor device. By improving the method for manufacturing a semiconductor device, the thermal stability of a high dielectric constant medium can be increased, the crystallization of the first gate dielectric layer can be prevented, and the leakage current caused by the crystallization of the first gate dielectric layer can be prevented. At the same time, nitrogen atoms are prevented from being enriched at the interface between the first gate dielectric layer and the gate oxide layer, and the increase of interface defects is avoided, thereby further improving the performance of the semiconductor device. It is possible to greatly reduce interface defects, reduce stress-induced leakage current, and improve negative bias temperature instability. It is possible to improve the problem of poor interface contact between the first gate dielectric layer and the substrate, and improve the gate's ability to control the channel, adjust the threshold voltage, and reduce leakage current. It is possible to improve the thermal stability and oxidation resistance of the metal gate, and improve the reliability and performance of the semiconductor device. It is possible to simplify the manufacturing process, improve manufacturing efficiency, and reduce the production cost of the enterprise while improving the performance of the semiconductor device.

[0060] The above description of the illustrated embodiments of the present invention (including the contents described in the Abstract) is not intended to be an exhaustive list or to limit the present invention to the precise form disclosed herein. Although specific embodiments of the present invention and examples of the present invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention as will be recognized and appreciated by those skilled in the art. As noted, these modifications may be made to the present invention in accordance with the above description of the embodiments described in the present invention, and these modifications will be within the spirit and scope of the present invention.

[0061] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, such as the technical solution formed by replacing the above features with the technical features with similar functions disclosed in this application (but not limited to). In addition to the technical features described in the specification, the remaining technical features are known technologies to those skilled in the art. In order to highlight the innovative features of the present invention, the remaining technical features will not be described in detail here.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, and forming a dummy gate on the substrate; Forming sidewall structures on both sides of the dummy gate; forming an interlayer dielectric layer on the substrate, wherein a surface of the dielectric layer is flush with a surface of the dummy gate; removing the dummy gate to form a recess; Forming a first gate dielectric layer on the bottom and sidewalls of the recess, wherein the first gate dielectric layer is a high dielectric constant dielectric; A second gate dielectric layer is formed on the first gate dielectric layer; the material of the second gate dielectric layer is nitrogen-rich titanium nitride, and the nitrogen content in the second gate dielectric layer is 50% to 70%; the thickness of the second gate dielectric layer is greater than 60Å; Performing an annealing treatment on the first gate dielectric layer and the second gate dielectric layer, wherein the annealing temperature of the annealing treatment is 300° C. to 500° C.; and A metal work function layer and a metal layer are deposited on the second gate dielectric layer to form a metal gate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming the second gate dielectric layer includes: when the temperature of the deposition chamber is 400° C. to 600° C., repeatedly introducing a titanium source gas and a nitrogen source gas, wherein the flow ratio of the titanium source gas to the nitrogen source gas is 1:30 to 1:

100.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The annealing process is performed in a nitrogen-rich atmosphere, and the gas used in the nitrogen-rich atmosphere includes ammonia, nitrogen or hydrazine.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the dummy gate, a gate oxide layer is formed on the substrate, and the thickness of the gate oxide layer is 10Å~12Å.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the first gate dielectric layer is 18Å~20Å.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The manufacturing method further comprises: after forming the dummy gate, forming a lightly doped region in the substrate on both sides of the dummy gate.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The manufacturing method further comprises: after forming the sidewall structure, forming a heavily doped region in the substrate on a side of the sidewall structure away from the dummy gate.

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