Glass-based multi-chip heterogeneous integrated structure and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and discloses a glass-based multi-chip heterogeneous integrated structure and a preparation method thereof, including: making a first glass base with multiple redistribution layers on the front, and making the first glass base have a mounting hole; making a second glass base with a redistribution layer on the front, and the thickness of the second glass base is less than the thickness of the first glass base; the second glass base is installed in the mounting hole of the first glass base and fixed by a connecting material, so that a groove structure is formed between the redistribution layer on the front of the second glass base and the outermost redistribution layer on the front of the first glass base, and the back of the second glass base opposite to the groove structure is flush with the back of the first glass base; providing multiple chips, and attaching the chips to the front of the first glass base and the second glass base, respectively, the chip attached to the second glass base is a radio frequency chip, and the chip attached to the first glass base is a non-radio frequency chip. The present invention can realize differential heterogeneous integration of radio frequency chips and non-radio frequency chips, reduce radio frequency losses, and has a simple process.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a glass-based multi-chip heterogeneous integrated structure and a preparation method thereof. Background Art

[0002] Radio frequency (RF) chips and other conventional chips are typically integrated into packages with the special characteristics of RF signals and their environmental sensitivity taken into account. In traditional integrated circuit packaging technology, the process steps for packaging RF chips together with other conventional chips are as follows:

[0003] (1) First provide a substrate, and then make grooves and through holes on the surface of the substrate;

[0004] (2) Fabricate circuit layers in the recessed grooves and through holes, as well as on the substrate surface;

[0005] (3) The radio frequency chip and other conventional chips are attached to the circuit layer on the surface of the substrate and then encapsulated.

[0006] In this process, to reduce the RF loss of the RF chip, it is usually mounted on the circuit layer inside the immersion tank. However, the main problem with this process is that it is difficult to fabricate the circuit layer inside the immersion tank. Summary of the Invention

[0007] One of the objectives of this invention is to provide a glass-based multi-chip heterogeneous integrated structure and its fabrication method. By mounting a second glass substrate in a mounting groove of a glass substrate, differential heterogeneous integration of RF chips and non-RF chips can be achieved, which can effectively reduce the RF loss of RF chips and eliminate the need for a circuit layer in the mounting groove, thus simplifying the process.

[0008] The second objective of this invention is to provide a glass-based multi-chip heterogeneous integrated structure and its fabrication method. By mounting a second glass substrate in a mounting groove of a glass substrate, multi-chip heterogeneous integration is achieved. This method is particularly suitable for multi-chip integrated packaging containing radio frequency (RF) chips and can effectively reduce the RF loss of the RF chips. Furthermore, the glass-based multi-chip heterogeneous integrated structure has high strength and is not prone to warping.

[0009] To achieve this object, the present invention adopts the following technical solutions:

[0010] As one approach to heterogeneous integration of glass-based multi-chip chips, this method includes the following steps:

[0011] S10, manufacturing a first glass substrate with a multi-layer redistribution layer on the front side, and providing the first glass substrate with mounting holes;

[0012] S20. Fabricate a second glass substrate with a redistribution layer on the front side, the thickness of the second glass substrate being less than the thickness of the first glass substrate;

[0013] S30. The second glass substrate is installed in the mounting hole of the first glass substrate and fixed by connecting material, and a groove structure is formed between the redistribution layer on the front side of the second glass substrate and the outermost redistribution layer on the front side of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate.

[0014] S40. Provide multiple chips and attach the chips to the front sides of the first glass substrate and the second glass substrate respectively, wherein the chip attached to the second glass substrate is a radio frequency chip and the chip attached to the first glass substrate is a non-radio frequency chip.

[0015] As a further embodiment of the glass-based multi-chip heterogeneous integration method, in step S30, the second glass substrate is fixed in the mounting hole of the first glass substrate by a connecting material, wherein the connecting material is selected from any one of water glass, glass powder, glass paste, and adhesive resin.

[0016] As a further solution of the glass-based multi-chip heterogeneous integration method, step S10 specifically includes:

[0017] S10a. Provide a first glass plate and open a mounting hole through the first glass plate;

[0018] S10b, forming a first redistribution layer on the front surface of the first glass plate;

[0019] S10c. A dielectric layer is fabricated on the surface of the first wiring layer, and an opening is made in the dielectric layer to form a window that exposes part of the first wiring layer.

[0020] S10d, forming a conductive column in the window and forming a second redistribution layer on the surface of the dielectric layer;

[0021] S10e. A first solder mask layer is formed on the surface of the second overlay layer, and the pad area of ​​the second overlay layer is exposed.

[0022] As a further aspect of the glass-based multi-chip heterogeneous integration method, step S20 specifically includes:

[0023] S20a. Provide a second glass plate with the same thickness as the first glass plate and a clearance fit with the mounting hole, and fabricate a third wiring layer on the front side of the second glass plate.

[0024] S20b: A second solder mask layer is formed on the surface of the third wiring layer, and the pad area of ​​the third wiring layer is exposed.

[0025] On the other hand, the present invention provides a glass-based multi-chip heterogeneous integration structure, which is fabricated by the above-mentioned glass-based multi-chip heterogeneous integration method and includes a first glass substrate, a second glass substrate and multiple chips.

[0026] The first glass substrate includes a first glass plate, the first glass plate having a mounting hole along its thickness direction, and the front side of the first glass plate having multiple redistribution layers.

[0027] The second glass substrate includes a second glass plate with the same thickness as the first glass plate and a gap fit with the mounting hole, and a redistribution layer is provided on the front side of the second glass plate;

[0028] The second glass substrate is installed in the installation hole and fixed by a connecting material, and a groove structure is formed between the redistribution layer on the front side of the second glass substrate and the outermost redistribution layer on the front side of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate;

[0029] Some of the chips are non-RF chips and are attached to the outermost redistribution layer on the front side of the first glass substrate;

[0030] Some of the chips are radio frequency chips, which are attached to the redistribution layer on the front side of the second glass substrate.

[0031] As a second embodiment of the glass-based multi-chip heterogeneous integration method of the present invention, the glass-based multi-chip heterogeneous integration method includes the following steps:

[0032] S10, manufacturing a first glass substrate with multiple redistribution layers on the front side and a redistribution layer on the back side, and providing the first glass substrate with mounting holes and a plurality of through holes, wherein the redistribution layer on the front side is connected to the redistribution layer on the back side via conductive posts in the through holes;

[0033] S20, preparing a second glass substrate having a redistribution layer on the front side and a redistribution layer on the back side having the same structure as the redistribution layer on the back side of the first glass substrate, wherein the thickness of the second glass substrate is less than that of the first glass substrate, and the clearance between the second glass substrate and the mounting hole is matched;

[0034] S30, installing the second glass substrate in the installation hole of the first glass substrate, and forming a groove structure between the redistribution layer on the front surface of the second glass substrate and the outermost redistribution layer on the front surface of the first glass substrate, and the back surface of the second glass substrate opposite to the groove structure is flush with the back surface of the first glass substrate;

[0035] S40. Provide several chips, and attach the chips to the front sides of the first glass substrate and the second glass substrate, respectively. The chip attached to the first glass substrate is a non-RF chip, and the chip attached to the second glass substrate is a RF chip.

[0036] As a further embodiment of the glass-based multi-chip heterogeneous integration method, step S10 specifically includes:

[0037] S10a. A first glass plate is provided, with a plurality of first through holes and a mounting hole;

[0038] S10b, a first conductive post is made in the first through hole, a first rewiring layer is made on the front side of the first glass plate and a second rewiring layer is made on the back side of the first glass plate, and the first rewiring layer is connected to the second rewiring layer through the first conductive post.

[0039] S10c: A first dielectric layer is pressed on the surface of the first redistribution layer and a second dielectric layer is pressed on the surface of the second redistribution layer, and the first dielectric layer is made into a hole structure that exposes part of the first redistribution layer.

[0040] S10d: A second conductive post is formed in the hole structure and a third rewiring layer is formed on the surface of the first dielectric layer, and the second rewiring layer is connected to the first rewiring layer through the second conductive post.

[0041] S10e, A first solder mask layer is formed on the surface of the third wiring layer, and the pad area of ​​the third wiring layer is exposed to the first solder mask layer.

[0042] As a further aspect of the glass-based multi-chip heterogeneous integration method, step S20 specifically includes:

[0043] S20a. Provide a second glass plate with the same thickness as the first glass plate and a gap fit with the mounting hole; fabricate a fourth wiring layer on the front side of the second glass plate and a fifth wiring layer on the back side of the second glass plate.

[0044] S20b: A third solder mask layer is formed on the surface of the fourth overlay layer, and the pad area of ​​the fourth overlay layer is exposed to the third solder mask layer.

[0045] S20c, A third dielectric layer is pressed onto the back side of the fifth wiring layer.

[0046] On the other hand, the present invention provides a glass-based multi-chip heterogeneous integration structure, which is fabricated using the above-mentioned glass-based multi-chip heterogeneous integration method and includes a first glass substrate, a second glass substrate and multiple chips;

[0047] The first glass substrate includes a first glass plate, wherein a mounting hole is defined along the thickness of the first glass plate, a plurality of redistribution layers are provided on the front side of the first glass plate, and a redistribution layer is provided on the back side of the first glass plate, wherein the redistribution layer on the front side of the first glass plate is connected to the redistribution layer on the back side of the first glass plate via a conductive post embedded in the first glass plate;

[0048] The second glass substrate includes a second glass plate having the same thickness as the first glass plate, a redistribution layer being provided on the front side of the second glass plate, and a redistribution layer having the same structure as the redistribution layer on the back side of the first glass plate being provided on the back side of the second glass plate;

[0049] The second glass substrate is installed in the installation hole and fixed by a connecting material, and a groove structure is formed between the redistribution layer on the front side of the second glass substrate and the outermost redistribution layer on the front side of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate;

[0050] Some of the chips are non-RF chips and are attached to the outermost redistribution layer on the front side of the first glass substrate;

[0051] Some of the chips are radio frequency chips, which are attached to the redistribution layer on the front side of the second glass substrate.

[0052] As a further embodiment of the glass-based multi-chip heterogeneous integrated structure, in the multilayer redistribution layers on the front side of the first glass plate, a first dielectric layer is disposed between two adjacent redistribution layers, and the two adjacent redistribution layers are connected by a second conductive post embedded in the first dielectric layer. A first solder mask layer is disposed on the surface of the outermost redistribution layer, and the pad area of ​​the outermost redistribution layer is exposed outside the first solder mask layer. The redistribution layer on the back side of the first glass substrate is a single layer, and a second dielectric layer is disposed on the side of the redistribution layer away from the first glass plate. The sum of the thicknesses of all the redistribution layers, the first dielectric layer, and the first solder mask layer on the front side of the first glass plate is equal to the sum of the thicknesses of the redistribution layer and the second dielectric layer on the back side of the first glass plate.

[0053] The redistribution layer on the front side of the second glass plate is provided with a second solder mask layer, and the pad area of ​​the redistribution layer is exposed outside the second solder mask layer. The redistribution layer on the back side of the second glass plate is a single layer, and a third dielectric layer is provided on the side of the redistribution layer away from the second glass plate. The sum of the thicknesses of the redistribution layer and the second dielectric layer on the back side of the first glass plate is equal to the sum of the thicknesses of the redistribution layer and the third dielectric layer on the back side of the second glass plate.

[0054] The beneficial effects of this invention are:

[0055] By manufacturing separate glass substrates for mounting chips with different requirements and then securing the thinner glass substrate within the mounting holes of the thicker glass substrate, this method enables differential heterogeneous integration of various chips. This approach is particularly suitable for heterogeneous integration of RF chips and other chips, enabling all-glass packaging and interconnection of complex structures. Compared to existing technologies, this method also simplifies the process by eliminating the need for a circuit layer within the sink.

[0056] The present invention, by designing the thickness of the front and back sides of the first glass plate of the first glass substrate to be the same, can effectively reduce the warpage of the glass-based multi-chip heterogeneous integrated structure and improve the strength of the glass-based multi-chip heterogeneous integrated structure. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0058] Figure 1 This is a cross-sectional schematic diagram of the first glass substrate described in Embodiment 1 of the present invention.

[0059] Figure 2 This is a cross-sectional schematic diagram of the second glass substrate described in Embodiment 1 of the present invention.

[0060] Figure 3 This is a cross-sectional schematic diagram of the glass-based multi-chip heterogeneous integrated structure described in Embodiment 1 of the present invention.

[0061] Figure 4 This is a cross-sectional schematic diagram of the first glass substrate described in Embodiment 2 of the present invention.

[0062] Figure 5 This is a cross-sectional schematic diagram of the second glass substrate described in Embodiment 2 of the present invention.

[0063] Figure 6 This is a cross-sectional schematic diagram of the glass-based multi-chip heterogeneous integrated structure described in Embodiment 2 of the present invention.

[0064] Figure 1-3 middle:

[0065] 1. First glass substrate; 11. First glass plate; 12. Mounting hole; 13. First redistribution layer; 14. Second dielectric layer; 15. Conductive post; 16. Second redistribution layer; 17. First solder mask layer;

[0066] 2. Second glass substrate; 21. Second glass plate; 22. Third redistribution layer; 23. Second solder resist layer;

[0067] 3. First chip;

[0068] 4. Second chip;

[0069] Figure 4-6 middle:

[0070] 10. First glass substrate; 101. First glass plate; 102. Mounting hole; 103. First conductive post; 104. First redistribution layer; 105. Second redistribution layer; 106. Second dielectric layer; 107. Third dielectric layer; 108. Second conductive post; 109. Third redistribution layer; 110. First solder resist layer;

[0071] 20, second glass substrate; 201, second glass plate; 202, fourth redistribution layer; 203, fifth redistribution layer; 204, fourth dielectric layer; 205, second solder resist layer;

[0072] 30. The first chip;

[0073] 40. The second chip. DETAILED DESCRIPTION

[0074] The technical solution of the present invention will be further described below with reference to the accompanying drawings and through specific implementation methods.

[0075] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual images. They should not be construed as limiting the scope of this patent. To better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0076] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present patent. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0077] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" or similar designation indicating a connection between components should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0078] Example 1

[0079] This embodiment provides a glass-based multi-chip heterogeneous integration method, comprising the following steps:

[0080] S10, manufacturing a first glass substrate with a multi-layer redistribution layer on the front side, and providing the first glass substrate with mounting holes;

[0081] S20. Fabricate a second glass substrate with a redistribution layer on the front side, the thickness of the second glass substrate being less than the thickness of the first glass substrate;

[0082] S30. The second glass substrate is installed in the mounting hole of the first glass substrate and fixed by connecting material, and a groove structure is formed between the redistribution layer on the front of the second glass substrate and the outermost redistribution layer on the front of the first glass substrate, and the back of the second glass substrate opposite to the groove structure is flush with the back of the first glass substrate.

[0083] S40. Provide multiple chips and attach the chips to the front sides of the first glass substrate and the second glass substrate respectively. The chip attached to the second glass substrate is a radio frequency (RF) chip, and the chip attached to the first glass substrate is a non-RF chip.

[0084] Optionally, in step S30, the second glass substrate is fixed in the mounting hole of the first glass substrate by a connecting material, which is selected from any one of water glass, glass powder, glass paste, and adhesive resin.

[0085] In this embodiment, a mounting hole is made in the first glass substrate, and a second glass substrate is embedded into the mounting hole of the first glass substrate. The radio frequency (RF) chip is mounted on the redistribution layer that is in close contact with the second glass substrate. Non-RF chips can be mounted on the outermost layer of the multiple redistribution layers on the first glass substrate as needed. This enables differential heterogeneous integration of the RF chip and other non-RF chips, and shortens the distance between the RF chip and the second glass substrate, thereby reducing the RF signal loss of the RF chip and improving the signal transmission stability of the RF chip.

[0086] Optionally, step S10 specifically includes:

[0087] S10a. Provide a first glass plate and open a mounting hole through the first glass plate;

[0088] S10b, Create a first wiring layer on the front side of the first glass plate;

[0089] S10c. A dielectric layer is fabricated on the surface of the first wiring layer, and holes are made in the dielectric layer to form windows that expose part of the first wiring layer.

[0090] S10d, create conductive pillars inside the window and create a second wiring layer on the surface of the dielectric layer;

[0091] S10e, a first solder mask layer is formed on the surface of the second routing layer, and the pad area of ​​the second routing layer is exposed.

[0092] Optionally, step S20 specifically includes:

[0093] S20a, Provide a second glass plate with the same thickness as the first glass plate and a clearance matching the mounting hole, and fabricate a third wiring layer on the front side of the second glass plate;

[0094] S20b: Create a second solder mask layer on the surface of the third wiring layer and expose the pad area of ​​the third wiring layer.

[0095] Next, we will combine the appendix Figure 1-3 The following detailed implementation schemes illustrate the glass-based multi-chip heterogeneous integration method of this embodiment.

[0096] Specifically, the fabrication method of the glass-based multi-chip heterogeneous integrated structure in this embodiment includes the following steps:

[0097] Step 1: Preparation of the first glass substrate 1

[0098] (1) Provide a first glass plate 11, perform laser modification on the first glass plate 11, and then etch it to form a mounting hole 12;

[0099] (2) Press the first dielectric layer into the mounting hole 12 so that the first dielectric layer fills the mounting hole 12 and the surface of the first dielectric layer is flush with the front and back sides of the first glass plate 11 respectively.

[0100] (3) A seed layer is formed by vacuum sputtering on the front side of the first glass plate 11 and the surface of the first dielectric layer on the same side as the front side; the seed layer can be a titanium metal layer + copper metal layer, or other alloys, which will not be described in detail here.

[0101] (4) Press a photosensitive film onto the surface of the seed layer, and after exposure and development, form a first window that exposes part of the first glass plate 11.

[0102] (5) Electroplating is performed inside the first window to create the first superwire layer 13;

[0103] (6) Remove the residual photosensitive film to expose part of the seed layer (including the seed layer on the front side of the first dielectric layer);

[0104] (7) etching the exposed seed layer to completely expose the front surface of the first dielectric layer and partially expose the first glass plate 11;

[0105] (8) Remove the first dielectric layer inside the mounting hole 12;

[0106] (9) A second dielectric layer 14 is pressed on the surface of the first redistribution layer 13, and the second dielectric layer 14 is made into a hole structure that exposes part of the first redistribution layer 13.

[0107] (10) forming a seed layer in the hole structure and on the surface of the second dielectric layer 14 by vacuum sputtering;

[0108] (11) Pressing a photosensitive film on the surface of the seed layer, and subjecting it to exposure and development treatment, to form a second window exposing a portion of the second dielectric layer 14;

[0109] (12) forming a conductive column 15 in the hole structure and a second redistribution layer 16 in the second window by electroplating;

[0110] (13) Remove the residual photosensitive film so that part of the seed layer is exposed to the second rewiring layer 16;

[0111] (14) Etching the exposed seed layer;

[0112] (15) Apply a first solder mask layer 17 to the surface of the second redistribution layer 16;

[0113] (16) The first solder mask layer 17 is exposed and developed to expose the pad area of ​​the second redistribution layer 16, thus obtaining the desired result. Figure 1 The first glass substrate 1 is shown.

[0114] In other embodiments, the number of layers of the second wiring layer 16 is not limited to one layer, but can also be a multi-layer structure, with the multi-layer structure separated and interconnected by dielectric layers, depending on the actual situation and is not limited thereto.

[0115] Step 2: Preparation of the second glass substrate 2

[0116] (1) Provide a second glass plate 21 with the same thickness as the first glass plate 11 and a gap fit with the mounting hole 12, and make a seed layer on the front side of the first glass plate 11 by vacuum sputtering;

[0117] (4) Press a photosensitive film onto the seed layer, and after exposure and development, form a third window;

[0118] (5) forming a third redistribution layer 22 in the third window by electroplating;

[0119] (6) Remove the remaining photosensitive film to expose part of the seed layer;

[0120] (7) Etch the exposed seed layer;

[0121] (8) A second solder mask layer 23 is formed on the surface of the third wiring layer 22;

[0122] (9) The second solder mask layer 23 is exposed and developed to expose the pad area of ​​the third redistribution layer 22, thus obtaining the desired result. Figure 2 The second glass substrate 2 is shown.

[0123] Step 3: The second glass substrate 2 is embedded with the first glass substrate 1

[0124] (1) Apply glass paste to the wall of the mounting hole 12 in the first glass substrate 1 and to the outer periphery of the second glass substrate 2;

[0125] (2) Install the second glass substrate 2 into the mounting hole 12 of the first glass substrate 1, so that the back of the first glass substrate 1 and the back of the second glass substrate 2 are flush, and the front of the first glass substrate 1 and the front of the second glass substrate 2 form a groove structure (the front of the second glass substrate 2 serves as the bottom of the groove).

[0126] (3) Perform sintering treatment to fix the second glass substrate 2 to the first glass substrate 1.

[0127] In this embodiment, the first solder resist layer 17 and the second solder resist layer 23 have high temperature resistance, so the sintering process will not affect their performance.

[0128] For other heat-sensitive first solder resist layer 17 and second solder resist layer 23, the specific steps (15)-(16) in step one and the specific steps (8)-(9) in step two can be performed after sintering, and will not be described in detail here.

[0129] Step 4: Chip Mounting

[0130] Provides a number of first chips 3 that are non-RF chips and a number of second chips 4 that are RF chips;

[0131] The first chip 3 is flip-chip mounted on the second wiring layer 16, and the I / O ports of the first chip 3 are connected to the pad areas of the second wiring layer 16.

[0132] The second chip 4 is flip-chip mounted on the third wiring layer 22, and the I / O ports of the second chip 4 are connected to the pad areas of the third wiring layer 22, thus achieving the desired result. Figure 3 The glass-based multi-chip heterogeneous integrated structure shown.

[0133] It should be noted that chip mounting can also be performed in steps one and two, respectively, which will not be elaborated further.

[0134] In subsequent processes, the chip can be encapsulated and electrically exposed to form a glass-based multi-chip heterogeneous integrated packaging structure, which will not be elaborated further.

[0135] like Figure 3 As shown, the glass-based multi-chip heterogeneous integrated structure of this embodiment includes a first glass substrate 1, a second glass substrate 2, a first chip 3, and a second chip 4;

[0136] The first glass substrate 1 includes a first glass plate 11, the first glass plate 11 having a mounting hole 12 defined along its thickness. A first redistribution layer 13, a second dielectric layer 14, a second redistribution layer 16, and a first solder resist layer 17 are sequentially disposed on the front surface of the first glass plate 11 from bottom to top. The first redistribution layer 13 is connected to the second redistribution layer 16 via a conductive column 15 embedded in the second dielectric layer 14. The pad area of ​​the second redistribution layer 16 is exposed on the first solder resist layer 17.

[0137] The second glass substrate 2 includes a second glass plate 21 with the same thickness as the first glass plate 11 and a clearance fit with the mounting hole 12. A third wiring layer 22 is provided on the front side of the second glass plate 21. A second solder mask layer 23 is provided above the third wiring layer 22. The pad area of ​​the third wiring layer 22 is exposed on the second solder mask layer 23.

[0138] The second glass substrate 2 is installed in the mounting hole 12 and fixed by the connecting material. A groove structure is formed between the third wiring layer 22 on the front side of the second glass substrate 2 and the outermost second wiring layer 16 on the front side of the first glass substrate 1. The back side of the second glass substrate 2 opposite to the groove structure is flush with the back side of the first glass substrate 1.

[0139] The first chip 3 is a non-RF chip, which is attached to the front side of the first glass substrate 1 and located on the second redistribution layer 16, and the I / O port of the first chip 3 is connected to the pad area of ​​the second redistribution layer 16.

[0140] The second chip 4 is an RF chip, which is attached to the third wiring layer 22 on the front side of the second glass substrate 2, and the I / O port of the second chip 4 is connected to the pad area of ​​the third wiring layer 22.

[0141] Example 2

[0142] This embodiment is a further improvement on the first embodiment described above.

[0143] Specifically, the glass-based multi-chip heterogeneous integration method of this embodiment includes the following steps:

[0144] S10, manufacturing a first glass substrate with multiple redistribution layers on the front side and a redistribution layer on the back side, and providing the first glass substrate with mounting holes and a plurality of through holes, wherein the redistribution layer on the front side is connected to the redistribution layer on the back side via conductive posts in the through holes;

[0145] S20, preparing a second glass substrate having a redistribution layer on the front side and a redistribution layer on the back side having the same structure as the redistribution layer on the back side of the first glass substrate, wherein the thickness of the second glass substrate is less than that of the first glass substrate and the clearance of the second glass substrate and the mounting hole are matched;

[0146] S30, installing the second glass substrate in the installation hole of the first glass substrate, and forming a groove structure between the redistribution layer on the front surface of the second glass substrate and the outermost redistribution layer on the front surface of the first glass substrate, and the back surface of the second glass substrate opposite to the groove structure is flush with the back surface of the first glass substrate;

[0147] S40. Provide several chips, and attach the chips to the front sides of the first glass substrate and the second glass substrate, respectively. The chip attached to the first glass substrate is a non-RF chip, and the chip attached to the second glass substrate is a RF chip.

[0148] Based on the realization of differential heterogeneous integration of RF chips and non-RF chips, this embodiment designs circuit structures with the same structure on the back of the first glass plate and the second glass plate, so that the thickness of the circuit structures on the front and back sides of the relatively large first glass plate are consistent, which can reduce the warping of the entire glass-based multi-chip heterogeneous integrated structure, thereby improving the strength of the glass-based multi-chip heterogeneous integrated structure.

[0149] Furthermore, step S10 specifically includes:

[0150] S10a. A first glass plate is provided, with a plurality of first through holes and a mounting hole;

[0151] S10b, forming a first conductive pillar in the first through hole, forming a first redistribution layer on the front surface of the first glass plate, and forming a second redistribution layer on the back surface of the first glass plate, and connecting the first redistribution layer to the second redistribution layer through the first conductive pillar;

[0152] S10c, pressing a first dielectric layer on the surface of the first redistribution layer and pressing a second dielectric layer on the surface of the second redistribution layer, and performing a hole processing on the first dielectric layer to form a hole structure that exposes a portion of the first redistribution layer;

[0153] S10d: A second conductive post is fabricated in the hole structure and a third wiring layer is fabricated on the surface of the first dielectric layer, and the second wiring layer is connected to the first wiring layer through the second conductive post.

[0154] S10e, A first solder mask layer is formed on the surface of the third wiring layer, and the pad area of ​​the third wiring layer is exposed to the first solder mask layer.

[0155] Furthermore, step S20 specifically includes:

[0156] S20a, Provide a second glass plate with the same thickness as the first glass plate and which fits the gap of the mounting hole, and make a fourth wiring layer on the front side of the second glass plate and a fifth wiring layer on the back side of the second glass plate.

[0157] S20b: A third solder mask layer is formed on the surface of the fourth routing layer, and the pad area of ​​the fourth routing layer is exposed to the third solder mask layer.

[0158] S20c, A third dielectric layer is pressed onto the back of the fifth wiring layer.

[0159] Next, we will combine the appendix Figure 4-6 The following specific embodiments further illustrate the glass-based multi-chip heterogeneous integration method of this embodiment. Specifically, the fabrication method of the glass-based multi-chip heterogeneous integration unstructure of this embodiment includes the following steps:

[0160] Step 1: Preparation of the first glass substrate 10

[0161] (1) Provide a first glass plate 101, perform laser modification on the first glass plate 101, and then perform etching to form a plurality of first through holes and a mounting hole 102;

[0162] (2) Press the first dielectric layer into the mounting hole 102 so that the first dielectric layer fills the mounting hole 102 and the surface of the first dielectric layer is flush with both sides of the first glass plate 101.

[0163] (3) A seed layer is formed by vacuum sputtering on both sides of the first glass plate 101, both sides of the first dielectric layer and the surface of the through hole; the seed layer can be a titanium metal layer + copper metal layer, or other alloys, which will not be described in detail here.

[0164] (4) Press photosensitive films onto the seed layers on both sides of the first glass plate 101 and the first dielectric layer respectively, and after exposure and development, form the first window and make the photosensitive film cover the seed layers on both sides of the first dielectric layer.

[0165] (5) A first conductive post 103 is made in the through hole by electroplating and a first rewiring layer 104 is made in the first window adjacent to the front of the first glass plate 101. A second rewiring layer 105 is made in the first window adjacent to the back of the first glass plate 101, and the first rewiring layer 104 is connected to the second rewiring layer 105 through the first conductive post 103.

[0166] (6) Remove the residual photosensitive film to expose part of the seed layer (including the seed layer on both sides of the first dielectric layer);

[0167] (7) Etch the exposed seed layer to expose the first dielectric layer and part of the first glass plate 101;

[0168] (8) A second dielectric layer 106 is pressed on the surface of the first wiring layer 104 and the front side of the first dielectric layer, and a third dielectric layer 107 is pressed on the surface of the second wiring layer 105.

[0169] (9) The second dielectric layer 106 is made into a hole structure that exposes part of the first redistribution layer 104;

[0170] (10) A seed layer is fabricated in the hole structure and on the surface of the second dielectric layer 106 by vacuum sputtering;

[0171] (11) forming a photosensitive film on the seed layer, and exposing and developing the photosensitive film to form a second window that exposes a portion of the seed layer (excluding the seed layer on the surface of the first dielectric layer);

[0172] (12) A second conductive post 108 is made in the hole structure by electroplating and a third wiring layer 109 is made in the second window, and the third wiring layer 109 is connected to the first wiring layer 104 through the second conductive post 108.

[0173] (13) Remove the residual photosensitive film and etch the exposed seed layer (including the seed layer facing the first dielectric layer);

[0174] (14) Remove the first dielectric layer inside the mounting hole 102 and the second dielectric layer 106 on the surface of the first dielectric layer;

[0175] (15) A first solder mask layer 110 is formed on the surface of the third wiring layer 109;

[0176] (16) The first solder mask layer 110 is exposed and developed to expose the pad area of ​​the third redistribution layer 109, thus obtaining the desired result. Figure 4 The first glass substrate 10 is shown.

[0177] In other embodiments, the number of layers of the third wiring layer 109 is not limited to one layer, but can also be a multi-layer structure, with the multi-layer structure separated and interconnected by dielectric layers, depending on the actual situation and is not limited thereto.

[0178] Step 2: Prepare the second glass substrate 20

[0179] (1) Provide a second glass plate 201, the thickness of the second glass plate 201 is the same as the thickness of the first glass plate 101, and the second glass plate 201 is clearance-fitted with the mounting hole 102.

[0180] (2) A seed layer is fabricated on both sides of the second glass plate 201 by vacuum sputtering; the seed layer can be a titanium metal layer + a copper metal layer, or other alloys, which will not be elaborated further.

[0181] (3) Press a photosensitive film onto the seed layer, and after exposure and development, form a third window;

[0182] (5) A fourth wiring layer 202 is formed in the third window adjacent to the front side of the second glass plate 201 by electroplating, and a fifth wiring layer 203 is formed in the third window adjacent to the back side of the second glass plate 201.

[0183] (6) Remove the residual photosensitive film and press the fourth dielectric layer 204 onto the surface of the fifth redistribution layer 203;

[0184] (7) A second solder mask layer 205 is fabricated on the surface of the fourth redistribution layer 202;

[0185] (8) Expose and develop the second solder mask layer 205 to expose the pad area of ​​the fourth redistribution layer 202, thus obtaining the desired result. Figure 5 The second glass substrate 20.

[0186] In this embodiment, the second glass plate 201 can also be made to have a through hole, so that the fourth wiring layer 202 can be interconnected with the fifth wiring layer 203 through the conductive post embedded in the through hole. The specific details will not be elaborated here.

[0187] Step 3: The second glass substrate 20 is fitted with the first glass substrate 10.

[0188] (1) A bonding material, such as water glass, is applied to the wall of the mounting hole 102 in the first glass substrate 10 and to the outer periphery of the second glass substrate 20;

[0189] (2) The second glass substrate 20 is installed in the mounting hole 102 of the first glass substrate 10, so that the back of the first glass substrate 10 and the back of the second glass substrate 20 are flush, and the front of the first glass substrate 10 and the front of the second glass substrate 20 form a groove structure (the front of the second glass substrate 20 serves as the bottom of the groove structure).

[0190] (3) Perform sintering treatment to fix the second glass substrate 20 to the first glass substrate 10.

[0191] Step 4: Chip Mounting

[0192] A first chip 30, which is a non-RF chip, and a second chip 40, which is an RF chip, are provided.

[0193] The first chip 30 is flip-chip mounted on the third wiring layer 109, that is, the I / O port of the first chip 30 is connected to the pad area of ​​the third wiring layer 109.

[0194] The second chip 40 is flip-chip mounted onto the fourth wiring layer 202 located within the recessed structure, meaning that the I / O ports of the second chip 40 are connected to the pad areas of the fourth wiring layer 202, thus achieving the desired result. Figure 6 The glass-based multi-chip heterogeneous integrated structure shown.

[0195] In the above Examples 1 and 2, sintering technology is a conventional technique in the field, and the connecting materials include, but are not limited to, the water glass, glass powder, glass paste (also known as nano metal paste), and adhesive resin.

[0196] Of course, the chip mounting in this embodiment is not limited to face-down mounting, but can also be face-up mounting, which will not be elaborated further.

[0197] Similarly, in this embodiment, the second glass substrate 20 can be installed in the mounting hole 102 of the first glass substrate 10 and sintered before performing the specific steps (15)-(16) in step one and the specific steps (7)-(8) in step two.

[0198] Similarly, after packaging and electrically extracting the chips of the glass-based multi-chip heterogeneous integrated structure, a glass-based multi-chip heterogeneous integrated packaging structure can be obtained, which will not be elaborated further.

[0199] like Figure 6 As shown, the glass-based multi-chip heterogeneous integrated structure of this embodiment includes a first glass substrate 10, a second glass substrate 20, a first chip 30, and a second chip 40.

[0200] (1) Wherein, the first glass substrate 10 includes a first glass plate 101, and the first glass plate 101 has a mounting hole 102 along its thickness direction; the front side of the first glass plate 101 is provided with a first redistribution layer 104, a second dielectric layer 106, a third redistribution layer 109 and a first solder resist layer 110 in sequence from bottom to top; the first redistribution layer 104 is connected to the third redistribution layer 109 through a second conductive post 108 embedded in the second dielectric layer 106; the solder pad area of ​​the third redistribution layer 109 is exposed outside the first solder resist layer 110; the first glass plate 101 A second wiring layer 105 is provided on the back side, and the first wiring layer 104 on the front side of the first glass plate 101 is connected to the second wiring layer 105 on the back side of the first glass plate 101 through the first conductive post 103 embedded in the first glass plate 101. A third dielectric layer 107 is provided on the side of the second wiring layer 105 away from the first glass plate 101. The sum of the thicknesses of the first wiring layer 104, the second dielectric layer 106, the third wiring layer 109 and the first solder mask layer 110 is equal to the sum of the thicknesses of the second wiring layer 105 and the third dielectric layer 107.

[0201] The second glass substrate 20 includes a second glass plate 201 with the same thickness as the first glass plate 101. A fourth wiring layer 202 is provided on the front side of the second glass plate 201. The surface of the fourth wiring layer 202 is covered with a second solder resist layer 205, and the pad area of ​​the fourth wiring layer 202 is exposed outside the second solder resist layer 205. A fifth wiring layer 203 with the same structure as the second wiring layer 105 on the back side of the first glass plate 101 is provided on the back side of the second glass plate 201. A fourth dielectric layer 204 is provided on the side of the fifth wiring layer 203 away from the second glass plate 201. The sum of the thicknesses of the fourth dielectric layer 204 and the fifth wiring layer 203 is equal to the sum of the thicknesses of the second wiring layer 105 and the third dielectric layer 107.

[0202] The second glass substrate 20 is installed in the mounting hole 102 and fixed by the connecting material. A groove structure is formed between the fourth wiring layer 202 on the front side of the second glass substrate 20 and the outermost third wiring layer 109 on the front side of the first glass substrate 10. The back side of the second glass substrate 20 opposite to the groove structure is flush with the back side of the first glass substrate 10.

[0203] The first chip 30 is a non-RF chip, which is attached to the outermost third wiring layer 109 on the front side of the first glass substrate 10, and the I / O port of the first chip 30 is connected to the pad area of ​​the third wiring layer 109.

[0204] The second chip 40 is an RF chip, which is attached to the fourth wiring layer 202 on the front side of the second glass substrate 20, and the I / O port of the second chip 40 is connected to the pad area of ​​the fourth wiring layer 202.

[0205] It should be stated that the above-described specific embodiments are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that various modifications, equivalent substitutions, and variations can be made to the present invention. However, such variations, as long as they do not depart from the spirit of the present invention, should be within the scope of protection of the present invention. Furthermore, some terminology used in this specification and claims is not limiting, but merely for ease of description.

Claims

1. A glass-based multi-chip heterogeneous integration method, characterized in that: The following steps are involved: S10, making the first glass substrate: S10a, providing a first glass plate, and opening a mounting hole penetrating the first glass plate; S10b, forming a first redistribution layer on the front surface of the first glass plate; S10c, manufacturing a dielectric layer on the surface of the first redistribution layer, and performing hole processing on the dielectric layer to form a window for partially exposing the first redistribution layer; S10d, forming a conductive column in the window and forming a second redistribution layer on the surface of the dielectric layer; S10e, forming a first solder resist layer on the surface of the second redistribution layer, and exposing the pad area of ​​the second redistribution layer; S20, manufacturing a second glass base having a thickness less than that of the first glass base: S20a, providing a second glass plate having the same thickness as the first glass plate and having a clearance matching the mounting hole, and manufacturing a third redistribution layer on the front side of the second glass plate; S20b, forming a second solder resist layer on the surface of the third redistribution layer, and exposing the pad area of ​​the third redistribution layer; S30, installing the second glass substrate in the installation hole of the first glass substrate and fixing it through a connecting material, and forming a groove structure between the third redistribution layer of the second glass substrate and the second redistribution layer of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate; S40. Provide a plurality of chips, and attach the chips to the second redistribution layer of the first glass substrate and the third redistribution layer of the second glass substrate, respectively, wherein the chip attached to the third redistribution layer is a radio frequency chip, and the chip attached to the second redistribution layer is a non-radio frequency chip.

2. The glass-based multi-chip heterogeneous integration method according to claim 1, characterized in that: In step S30, the second glass base is fixed in the mounting hole of the first glass base by a connecting material, and the connecting material is selected from any one of water glass, glass powder, glass paste, and adhesive resin.

3. A glass-based multi-chip heterogeneous integration method, characterized in that: The following steps are involved: S10, making the first glass substrate: S10a, providing a first glass plate, and forming a plurality of first through holes and a mounting hole; S10b, manufacturing a first conductive column in the first through hole, manufacturing a first redistribution layer on the front side of the first glass plate, and manufacturing a second redistribution layer on the back side of the first glass plate, and connecting the first redistribution layer with the second redistribution layer through the first conductive column; S10c, pressing a first dielectric layer on the surface of the first redistribution layer and pressing a second dielectric layer on the surface of the second redistribution layer, and performing hole processing on the first dielectric layer to form a hole structure that exposes a portion of the first redistribution layer; S10d, manufacturing a second conductive column in the hole structure and manufacturing a third redistribution layer on the surface of the first dielectric layer, and connecting the second redistribution layer to the first redistribution layer through the second conductive column; S10e, forming a first solder resist layer on the surface of the third redistribution layer, and making the pad area of ​​the third redistribution layer exposed to the first solder resist layer; S20, manufacturing a second glass base having a thickness smaller than that of the first glass base and matching the gap of the mounting hole: S20a, providing a second glass plate having the same thickness as the first glass plate and matching the gap of the mounting hole, forming a fourth redistribution layer on the front side of the second glass plate and forming a fifth redistribution layer on the back side of the second glass plate; S20b, forming a third solder resist layer on the surface of the fourth redistribution layer, and making the pad area of ​​the fourth redistribution layer exposed on the third solder resist layer; S20c, pressing a third dielectric layer on the back side of the fifth redistribution layer; S30, installing the second glass substrate in the installation hole of the first glass substrate, and forming a groove structure between the fourth redistribution layer of the second glass substrate and the third redistribution layer of the first glass substrate, and the back surface of the second glass substrate opposite to the groove structure is flush with the back surface of the first glass substrate; S40. Provide several chips, and attach the chips to the third redistribution layer of the first glass substrate and the fourth redistribution layer of the second glass substrate, respectively, wherein the chip attached to the third redistribution layer is a non-RF chip, and the chip attached to the fourth redistribution layer is a RF chip.

4. A glass-based multi-chip heterogeneous integrated structure, prepared by the glass-based multi-chip heterogeneous integration method according to any one of claims 1 to 2, characterized in that: It includes a first glass substrate, a second glass substrate and a plurality of chips; The first glass substrate comprises a first glass plate, a mounting hole is provided in the thickness direction of the first glass plate, and a plurality of redistribution layers are provided on the front side of the first glass plate; The second glass substrate comprises a second glass plate having the same thickness as the first glass plate and having a clearance matching the mounting hole, and a redistribution layer is disposed on the front side of the second glass plate; The second glass substrate is installed in the installation hole and fixed by a connecting material, and a groove structure is formed between the redistribution layer on the front side of the second glass substrate and the outermost redistribution layer on the front side of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate; Some chips are non-RF chips and are attached to the outermost redistribution layer on the front surface of the first glass substrate; Some chips are radio frequency chips and are attached to the redistribution layer on the front side of the second glass substrate.

5. A glass-based multi-chip heterogeneous integrated structure, prepared by the glass-based multi-chip heterogeneous integration method according to claim 3, characterized in that: It includes a first glass substrate, a second glass substrate and a plurality of chips; The first glass substrate comprises a first glass plate, wherein a mounting hole is provided in the thickness direction of the first glass plate, a plurality of redistribution layers are provided on the front side of the first glass plate, a redistribution layer is provided on the back side of the first glass plate, and the redistribution layer on the front side of the first glass plate is connected to the redistribution layer on the back side of the first glass plate via a conductive column embedded in the first glass plate; The second glass substrate comprises a second glass plate having the same thickness as the first glass plate, a redistribution layer is disposed on the front side of the second glass plate, and a redistribution layer having the same structure as the redistribution layer on the back side of the first glass plate is disposed on the back side of the second glass plate; The second glass substrate is installed in the installation hole and fixed by a connecting material, and a groove structure is formed between the redistribution layer on the front side of the second glass substrate and the outermost redistribution layer on the front side of the first glass substrate, and the back side of the second glass substrate opposite to the groove structure is flush with the back side of the first glass substrate; Some chips are non-RF chips and are attached to the outermost redistribution layer on the front surface of the first glass substrate; Some chips are radio frequency chips and are attached to the redistribution layer on the front side of the second glass substrate.

6. The glass-based multi-chip heterogeneous integrated structure according to claim 5, characterized in that: Among the multiple layers of redistribution layers on the front side of the first glass plate, a first dielectric layer is provided between two adjacent redistribution layers, and the two adjacent redistribution layers are connected via a second conductive column embedded in the first dielectric layer, a first solder resist layer is provided on the surface of the outermost redistribution layer, and a pad area of ​​the outermost redistribution layer is exposed to the first solder resist layer; the redistribution layer on the back side of the first glass substrate is a single layer, and a second dielectric layer is provided on a side of the redistribution layer away from the first glass plate; the sum of the thickness of all the redistribution layers, the first dielectric layer and the first solder resist layer on the front side of the first glass plate is equal to the sum of the thickness of the redistribution layer and the second dielectric layer on the back side of the first glass plate; A second solder resist layer is provided on the surface of the redistribution layer on the front side of the second glass plate, and the pad area of ​​the redistribution layer is exposed on the second solder resist layer, the redistribution layer on the back side of the second glass plate is a single layer, and a third dielectric layer is provided on the side of the redistribution layer away from the second glass plate, and the sum of the thickness of the redistribution layer and the second dielectric layer on the back side of the first glass plate is equal to the sum of the thickness of the redistribution layer and the third dielectric layer on the back side of the second glass plate.

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