Serial deserializer and network device

Abstract

The invention relates to the technical field of serial deserializer design, and discloses a serial deserializer and a network device. The serial deserializer comprises a first-in-first-out queue module, a physical coding sublayer module and a physical medium attachment layer module; one end of the first-in-first-out queue module is connected to a target media access control layer module, and the other end of the first-in-first-out queue module is connected to one end of the physical coding sublayer module; the physical coding sublayer module comprises a first state configuration machine and a coding unit, the first state configuration machine is used to receive a configuration instruction, and is used to adjust the configuration information of the first-in-first-out queue module, the configuration information of the coding unit and the configuration information of the physical medium attachment layer module according to the configuration instruction, so that the first-in-first-out queue module, the coding unit and the physical medium attachment layer module are adapted to data transmission under a target communication protocol. The invention enables the serial deserializer to flexibly connect to the media access control layer modules under various communication protocols.

Description

Technical Field

[0001] The present invention relates to the technical field of serial deserializer design, and in particular to a serial deserializer and a network device. Background Art

[0002] A serializer / deserializer (SerDes) can combine multiple low-speed parallel data streams into one high-speed serial data stream for transmission, and then decode the serial data streams back into parallel data streams at the receiving end, so as to transmit data efficiently and accurately in the communication system.

[0003] SerDes consists of two parts: the Physical Coding Sublayer (PCS) and the Physical Medium Attachment (PMA). The PCS is responsible for encoding and decoding data, converting parallel data into a format suitable for serial transmission, and performing the opposite operation at the receiving end. The PMA is responsible for converting the coded data provided by the PCS into a physical signal to adapt to a specific physical transmission medium (such as copper cable or optical fiber, etc.), and performing the opposite operation (converting physical signals into digital signals) at the receiving end.

[0004] At present, SerDes is generally designed based on Application Specific Integrated Circuit (ASIC). The PCS designed based on ASIC for SerDes is generally specially designed according to the protocol requirements. For example, taking the demand for supporting the Ethernet protocol as an example, a PCS based on the Ethernet protocol will be specially designed, resulting in SerDes being only suitable for specific network communication protocols and having poor flexibility. Summary of the invention

[0005] In view of this, the present invention provides a serial deserializer and a network device to solve the problem that the serial deserializer is only applicable to a specific network communication protocol and has poor flexibility.

[0006] In a first aspect, the present invention provides a serial deserializer, which is formed based on a field programmable logic gate array, and includes a first-in-first-out queue module, a physical coding sublayer module and a physical medium attachment layer module; one end of the first-in-first-out queue module is connected to a target media access control layer module, the other end of the first-in-first-out queue module is connected to one end of the physical coding sublayer module, the other end of the physical coding sublayer module is connected to one end of the physical medium attachment layer module, and the other end of the physical medium attachment layer module is connected to a physical transmission medium, wherein the target media access control layer module is one of a plurality of media access control layer modules, and the plurality of media access control layer modules correspond to different communication protocols; the first-in-first-out queue module is used to isolate the physical media access control layer module. The physical coding sublayer module comprises a first state configuration machine and a coding unit, wherein the first state configuration machine is used to receive configuration instructions, and to adjust the configuration information of the first-in-first-out queue module, the configuration information of the coding unit and the configuration information of the physical medium attachment layer module according to the configuration instructions, so that the first-in-first-out queue module, the coding unit and the physical medium attachment layer module are adapted to the data transmission under the target communication protocol, wherein the configuration information comprises at least one of bit width information, rate information and clock information, and the target communication protocol is the communication protocol corresponding to the target media access control layer module.

[0007] In this embodiment, when designing a serial deserializer based on a field programmable gate array, the physical coding sublayer module is de-protocolized. After the target media access control layer module is connected to the serial deserializer, the configuration information of the first-in-first-out queue module, the configuration information of the encoding unit and the configuration information of the physical medium attachment layer module are adjusted to the target configuration information through the first state configuration machine set in the physical coding sublayer module, so that the first-in-first-out queue module, the encoding unit and the physical medium attachment layer module are adapted to the data transmission under the target communication protocol, thereby enabling the serial deserializer to flexibly connect to the media access control layer modules under various communication protocols to meet the usage requirements of different application scenarios.

[0008] In an optional implementation, the physical medium attachment layer module includes a data channel and an initialization unit; the first state configuration machine is connected to the initialization unit, and the first state configuration machine adjusts the configuration information of the data channel through the initialization unit.

[0009] In an optional embodiment, the serial deserializer also includes a bypass channel, one end of the bypass channel is connected to the physical medium attachment layer module, and the other end is connected to the first-in-first-out queue module; the bypass channel is used to transfer the first data of the data channel to the first-in-first-out queue module, or to transfer the second data of the first-in-first-out queue module to the data channel.

[0010] In this embodiment, when the physical coding sublayer does not need to perform additional encoding, decoding or other processing operations, the serial data output by the physical medium attachment layer module can be directly transmitted to the first-in-first-out queue module through the bypass channel, or transmitted from the first-in-first-out queue module to the physical medium attachment layer module for transmission, which can shorten the data transmission path and reduce processing delays.

[0011] In an optional embodiment, the bypass channel includes a second state configuration machine, which is used to put the encoding unit, the data channel and the first-in-first-out queue module in bypass mode to transfer the first data to the first-in-first-out queue module or to transfer the second data to the data channel.

[0012] In an optional embodiment, there are multiple encoding units, multiple data channels and multiple first-in-first-out queue modules, and multiple encoding units correspond one-to-one to multiple data channels, and multiple encoding units correspond one-to-one to multiple first-in-first-out queue modules.

[0013] In an optional embodiment, the multiple first-in-first-out queue modules are connected to the multiple media access control layer modules via a fully interconnected network software configuration module, and the fully interconnected network software configuration module is used to connect the target media access control layer module with the target first-in-first-out queue module, and the target first-in-first-out queue module is at least one of the multiple first-in-first-out queue modules.

[0014] In an optional embodiment, the fully interconnected network software configuration module includes an interconnection unit, an input interface and an output interface; the multiple input pins of the input interface are respectively connected to the multiple media access control layer modules, and the multiple output pins of the output interface are respectively connected to the multiple first-in-first-out queue modules. The interconnection unit is used to make the target input pin and the target output pin in a connected state, the target input pin is an input pin among the multiple input pins connected to the target media access control layer module, and the target output pin is an output pin among the multiple output pins connected to the target first-in-first-out queue module.

[0015] In an optional implementation, the FIFO queue module is further used to adjust the bit width of the third data after receiving the third data from the target media access control layer module, so that the clock frequency of the third data is synchronized with the clock frequency of the encoding unit.

[0016] In an optional implementation, the first state configuration machine is used to obtain the configuration instruction from a peripheral bus interface.

[0017] In a second aspect, the present invention provides a network device, comprising: a serial deserializer of the above-mentioned first aspect or any corresponding embodiment thereof, a fully interconnected network software configuration module and multiple media access control layer modules, wherein the serial deserializer is connected to the multiple media access control layer modules through the fully interconnected network software configuration module. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a schematic diagram of the structure of the conventional serial deserializer and the media access control layer module;

[0020] Figure 2 is a structural schematic diagram of a serial deserializer according to an embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of another serial deserializer according to an embodiment of the present invention;

[0022] Figure 4 is a structural schematic diagram of another serial deserializer according to an embodiment of the present invention;

[0023] Figure 5 is a schematic structural diagram of a bypass channel according to an embodiment of the present invention;

[0024] Figure 6 It is a structural schematic diagram of a serial deserializer connected to multiple media access control layer modules according to an embodiment of the present invention;

[0025] Figure 7 Schematic diagram of the structure of the fully interconnected network software configuration module according to an embodiment of the present invention.

[0026] Figure numerals: 200, serial deserializer; 210, first-in-first-out queue module; 220, physical coding sublayer module; 221, first state configuration machine; 222, encoding unit; 230, physical medium attachment layer module; 231, data channel; 232, initialization unit; 240, bypass channel; 241, second state configuration machine; 300, media access control layer module; 301, target media access control layer module; 400, full internetwork software configuration module; 410, internetwork unit; 420, input interface; 430, output interface. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0028] The PCS module of the ASIC-based SerDes needs to be specially designed according to the protocol requirements and connected to the Media Access Control (MAC) module corresponding to the specific communication protocol. For example, Figure 1 As shown, the MAC (A) module is connected to the PCS (N) module through an interface (Interface), and the MAC (B) module is connected to the PCS (N-1) module through an interface (Interface). Among them, the PCS (N) module is also connected to the PMA (N) module through a SerDes interface, and the PCS (N-1) module is also connected to the PMA (N-1) module through a SerDes interface. The MAC (A) module and the MAC (B) module are also connected to other systems (such as processors, etc.) through a bus protocol (Advanced eXtensible Interface, AXI) interface. The PCS module in the SerDes designed based on ASIC can only be connected to the MAC module corresponding to a specific communication protocol. When connecting to the MAC module corresponding to other communication protocols to transmit data, the corresponding SerDes needs to be redesigned, and the flexibility of SerDes is poor.

[0029] In view of this, the present invention designs a serial deserializer based on a field programmable gate array (FPGA), utilizes the flexible configurability of FPGA, optimizes the structural design of the PCS module, and enables the serial deserializer to flexibly connect to MAC modules under various communication protocols to meet the needs of different application scenarios.

[0030] The serial deserializer provided by the present invention is described in detail below with reference to the accompanying drawings.

[0031] The serial deserializer provided by the present invention is designed based on FPGA. Figure 2 As shown, the SerDes 200 includes a First Input First Output (FIFO) module 210 , a Physical Coding Sublayer (PCS) module 220 , and a Physical Medium Attachment (PMA) module 230 .

[0032] Specifically, one end of the FIFO module 210 is connected to the target MAC module 301, the other end of the FIFO module 210 is connected to one end of the PCS module 220, the other end of the PCS module 220 is connected to one end of the PMA module 230, and the other end of the PMA module 230 is connected to a physical transmission medium (such as an optical fiber or a copper cable, etc.).

[0033] Among them, the target MAC module 301 is one of multiple MAC modules, and the communication protocols corresponding to the multiple MAC modules are different. For example, the communication protocol can be an Ethernet protocol, a high-speed serial computer expansion bus (peripheral component interconnect express, PCIE) protocol or a universal serial bus (Universal Serial Bus, USB) protocol, etc.

[0034] The FIFO module 210 is used to isolate the clock domains of the PCS module 220 and the target MAC module 301, and to isolate the clock domain of the PMA module 230 and the clock domain of the target MAC module 301. Specifically, the FIFO module 210 can be a clock domain bridge between the external target MAC module 301 and the internal PCS module 220 and the PMA module 230, provide data buffering between clock domains of different frequencies, and solve synchronization problems of clock domain crossing, such as clock edge misalignment or clock offset, etc. That is, when transmitting data across clock domains, the FIFO module 210 can serve as a synchronization point to ensure that data is correctly captured at the appropriate clock edge, reducing data loss and errors.

[0035] The PCS module 220 includes a first state configuration machine (CONFIG FSM) 221 and an encoding unit 222. The first state configuration machine 221 is used to receive a configuration instruction, and is used to adjust the configuration information of the FIFO module 210, the configuration information of the encoding unit 222, and the configuration information of the PMA module 230 according to the configuration instruction, so that the FIFO module 210, the encoding unit 222, and the PMA module 230 adapt to the data transmission under the target communication protocol. That is, the first state configuration machine 221 adjusts the configuration information of the FIFO module 210, the encoding unit 222, and the PMA module 230 to the target configuration information according to the configuration instruction, so that the FIFO module 210, the encoding unit 222, and the PMA module 230 adapt to the data transmission under the target communication protocol.

[0036] Among them, the configuration instruction is used to instruct the first state configuration machine 221 to adjust the configuration information of the FIFO module 210, the configuration information of the encoding unit 222 and the configuration information of the PMA module 230. The configuration instruction includes target configuration information that matches the target communication protocol. The configuration information includes at least one of bit width information, rate information and clock information. The target communication protocol is the communication protocol corresponding to the target MAC module 301.

[0037] It should be understood that the bit width refers to the number of data buses, that is, the number of bits of parallel data transmitted each time. The configuration of the bit width determines the parallel data processing capability and the width of the transmission interface. It matches the bit width of the MAC, ensuring that the data can be seamlessly connected at the transmission and receiving ends without loss or misalignment. Rate refers to the data transmission rate, which can be the number of bits of data transmitted per second. The communication rate negotiated with the MAC is consistent with the expected and actual transmission data rates at both ends to avoid data overflow or underload. The clock is the core of synchronous data transmission. Synchronizing with the clock of the MAC can ensure accurate transmission and reception of data.

[0038] Specifically, the PCS module 220 is de-protocolized so that the PCS module 220 no longer corresponds to a specific communication protocol. When the serial deserializer 200 is connected to the target MAC module 301, the first state configuration machine 221 receives the configuration instruction and configures the FIFO module 210, the encoding unit 222 and the PMA module 230 according to the configuration instruction so that the states of the FIFO module 210, the encoding unit 222 and the PMA module 230 meet the requirements of the target communication protocol.

[0039] Exemplarily, the first state configuration machine 221 is used to obtain configuration instructions from an Advanced Peripheral Bus (APB) interface. The configuration instructions may be generated by a device such as a processor based on a target communication protocol of the target MAC module 301.

[0040] During data transmission, after the FIFO module 210 receives the second data from the target MAC module 301, it sends the second data to the encoding unit 222. The encoding unit 222 is used to encode the received second data to obtain second encoded data, and send the second encoded data to the PMA module 230. After receiving the second encoded data, the PMA module 230 is used to convert the second encoded data into a second physical signal so that the second encoded data adapts to the physical transmission medium.

[0041] After receiving the first physical signal from the physical transmission medium, the PMA module 230 is also used to convert the first physical signal into first data and send the first data to the encoding unit 222. The encoding unit 222 is also used to decode the received first data to obtain first decoded data, and send the first decoded data to the FIFO module 210, which is forwarded to the target MAC module 301 by the FIFO module 210.

[0042] Specifically, the encoding unit 222 can perform 8b / 10b encoding and 64b / 66b encoding. In 8b / 10b encoding, every 8 bits of data will be encoded into a 10-bit symbol, and the additional 2 bits are used for synchronization and error detection, which is often used in lower-rate Ethernet standards such as Gigabit Ethernet. In 64b / 66b encoding, a 64-bit data block is encoded into a 66-bit data block, which is suitable for higher data transmission rates, such as 10 Gigabit Ethernet and above.

[0043] The original data stream is encoded before data transmission, and extra bits are added to achieve DC balance (ensuring that the number of 1s and 0s in the signal is roughly equal, avoiding long periods of continuous high or low levels that cause synchronization difficulties at the receiving end) and error detection capabilities.

[0044] In this embodiment, when designing a serial deserializer based on FPGA, the PCS module is de-protocolized. After the target MAC module 301 is connected to the serial deserializer 200, the configuration information of the FIFO module 210, the configuration information of the encoding unit 222, and the configuration information of the PMA module 230 are adjusted to the target configuration information through the first state configuration machine 221 set in the PCS module 220, so that the FIFO module 210, the encoding unit 222 and the PMA module 230 are adapted to the data transmission under the target communication protocol, thereby enabling the serial deserializer to flexibly connect to MAC modules under various communication protocols to meet the usage requirements of different application scenarios.

[0045] Exemplarily, the FIFO module 210 is also used to adjust the bit width of the third data after receiving the third data from the target MAC module 301, so that the clock frequency of the third data is synchronized with the clock frequency of the encoding unit. Specifically, the clock frequency of the target MAC module 301 is less than the clock frequency of the encoding unit 222. Before the data is transmitted from the target MAC module 301 to the encoding unit 222, the FIFO module 210 can accumulate the data and then output the data to the encoding unit 222 at a faster speed to achieve bit width widening. Among them, bit width widening refers to the process of increasing data throughput by increasing the number of data bits transmitted each time.

[0046] Furthermore, if Figure 2 As shown, the PMA module 230 includes a data lane (Lane) 231 and an initialization block (Initialize Block) 232. The initialization block 232 is connected to the first state configuration machine 221, and the first state configuration machine 221 adjusts the configuration information of the data lane 231 through the initialization block 232. Specifically, the first state configuration machine 221 is used to send target configuration information to the initialization block 232. After receiving the target configuration information, the initialization block 232 trains the data lane 231 and adjusts the configuration information of the data lane 231 to the target configuration information.

[0047] The present application does not limit the number of encoding units 222, data channels 231 and FIFO modules 210. The number of encoding units 222, data channels 231 and FIFO modules 210 can all be 1, or the number of encoding units 222, data channels 231 and FIFO modules 210 can all be multiple.

[0048] For example, Figure 3 As shown, multiple encoding units 222 correspond to multiple data channels 231 one by one, and multiple encoding units 222 correspond to multiple FIFO modules 210 one by one. Figure 3 For example, the number of encoding units 222, data channels 231 and FIFO modules 210 is 4, but the present invention is not limited thereto. For example, the number of encoding units 222, data channels 231 and FIFO modules 210 can also be 2 or 8.

[0049] For example, Figure 4 As shown, the serial deserializer 200 also includes a bypass channel 240, one end of the bypass channel 240 is connected to the PMA module 230, and the other end is connected to the FIFO module 210. The bypass channel 240 is used to directly transmit the first data of the data channel 231 to the FIFO module 210, or to directly transmit the second data of the FIFO module 210 to the data channel 231, so as to realize the direct connection between the PMA module 230 and the external interface and improve the flexibility.

[0050] In this embodiment, when the PCS module 220 is not required to perform additional encoding, decoding or other processing operations, the serial data output by the PMA module 230 can be directly transmitted to the FIFO module 210 through the bypass channel 240, or transmitted from the FIFO module 210 to the PMA module 230 for transmission, which can shorten the data transmission path and reduce processing delays.

[0051] Specifically, Figure 5 As shown, the bypass channel 240 includes a second state configuration machine 241, and the second state configuration machine 241 is used to put the encoding unit 222, the data channel 231 and the FIFO module 210 in the bypass mode to transmit the first data to the FIFO module 210 or to transmit the second data to the data channel 231. Specifically, after the second state configuration machine 241 is triggered, the states of the encoding unit 222, the data channel 231 and the FIFO module 210 are adjusted to stop encoding or decoding of the encoding unit 222, and the data channel 231 is directly connected to the FIFO module 210.

[0052] For example, Figure 6 As shown, multiple FIFO modules 210 are connected to multiple media access control layer modules (MAC) 300 through a fully interconnected network software configuration (Soft ConfigMux) module 400. The fully interconnected network software configuration module 400 is used to connect the target MAC module 301 to the target FIFO module, and the target FIFO module is at least one of the multiple FIFO modules 210. That is, through the fully interconnected network software configuration module 400, different FIFO modules 210 and different MAC modules 300 can be connected according to needs.

[0053] Specifically, Figure 7 As shown, the fully interconnected network software configuration module 400 includes an interconnection network unit (SWITCHBOX) 410, an input interface (Input MUX) 420 and an output interface (Output MUX) 430. The multiple input pins of the input interface 420 are respectively connected to the multiple MAC modules 300, and the multiple output pins of the output interface 430 are respectively connected to the multiple FIFO modules 210. The interconnection network unit 410 is used to connect the target input pin and the target output pin. The target input pin is an input pin connected to the target MAC module 301 among the multiple input pins, and the target output interface is an output pin connected to the target FIFO module among the multiple output pins.

[0054] Specifically, the interconnection network unit 410 is a software-configurable fully interconnected network. Through software configuration, the fully interconnected network is realized, and the data links and clock reset links corresponding to the input interface and the output interface are interconnected through software static configuration. Exemplarily, when power is turned on and initialized, the software configures the hardware of the interconnection network unit 410 according to the truth table to realize the interconnection of data, clock and reset.

[0055] The embodiment of the present invention also provides a network device, such as Figure 6 As shown, the network device includes multiple MAC modules 300, a fully interconnected network software configuration module 400 and a serial deserializer 200 provided by any of the above embodiments, and the serial deserializer 200 is connected to the multiple MAC modules 300 through the fully interconnected network software configuration module 400.

[0056] Specifically, in this embodiment, the serial deserializer 200 is connected to the MAC module 300 through the fully interconnected network software configuration module 400 and the FIFO module 210. The number of serial deserializers 200 can also be multiple, and the number of MAC modules 300 and the number of serial deserializers 200 can be flexibly increased or decreased according to demand.

[0057] Exemplarily, the network device may be a computer device or a server or other device.

[0058] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0061] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0062] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0063] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A serial deserializer, characterized in that: The serial deserializer is formed based on a field programmable logic gate array, and the serial deserializer includes a first-in-first-out queue module, a physical coding sublayer module and a physical medium attachment layer module; One end of the first-in-first-out queue module is connected to a target media access control layer module, the other end of the first-in-first-out queue module is connected to one end of the physical coding sublayer module, the other end of the physical coding sublayer module is connected to one end of the physical medium attachment layer module, and the other end of the physical medium attachment layer module is connected to a physical transmission medium, wherein the target media access control layer module is one of a plurality of media access control layer modules, and the plurality of media access control layer modules correspond to different communication protocols; The first-in-first-out queue module is used to isolate the clock domain of the physical coding sublayer module and the target media access control layer module, and is used to isolate the clock domain of the physical medium attachment layer module and the target media access control layer module; The physical coding sublayer module includes a first state configuration machine and a coding unit. The first state configuration machine is used to receive configuration instructions and to adjust the configuration information of the first-in-first-out queue module, the configuration information of the coding unit and the configuration information of the physical medium attachment layer module according to the configuration instructions, so that the first-in-first-out queue module, the coding unit and the physical medium attachment layer module adapt to data transmission under the target communication protocol, wherein the configuration information includes at least one of bit width information, rate information and clock information, and the target communication protocol is the communication protocol corresponding to the target media access control layer module.

2. The serial deserializer according to claim 1, characterized in that: The physical medium additional layer module includes a data channel and an initialization unit; The first state configuration machine is connected to the initialization unit, and the first state configuration machine adjusts the configuration information of the data channel through the initialization unit.

3. The serial deserializer according to claim 2, characterized in that: The serial deserializer further includes a bypass channel, one end of which is connected to the physical medium attachment layer module, and the other end of which is connected to the first-in-first-out queue module; The bypass channel is used to transmit the first data of the data channel to the first-in-first-out queue module, or to transmit the second data of the first-in-first-out queue module to the data channel.

4. The serial deserializer according to claim 3, characterized in that: The bypass channel includes a second state configuration machine, which is used to put the encoding unit, the data channel and the first-in-first-out queue module in bypass mode to transfer the first data to the first-in-first-out queue module or transfer the second data to the data channel.

5. The serial deserializer according to any one of claims 2 to 4, characterized in that: There are multiple encoding units, multiple data channels and multiple first-in-first-out queue modules, and multiple encoding units correspond one-to-one to multiple data channels, and multiple encoding units correspond one-to-one to multiple first-in-first-out queue modules.

6. The serial deserializer according to claim 5, characterized in that: The multiple first-in-first-out queue modules are connected to the multiple media access control layer modules through a fully interconnected network software configuration module. The fully interconnected network software configuration module is used to connect the target media access control layer module with the target first-in-first-out queue module, and the target first-in-first-out queue module is at least one of the multiple first-in-first-out queue modules.

7. The serial deserializer according to claim 6, characterized in that: The full internetworking software configuration module includes an internetworking unit, an input interface and an output interface; The multiple input pins of the input interface are respectively connected to the multiple media access control layer modules, and the multiple output pins of the output interface are respectively connected to the multiple first-in-first-out queue modules. The interconnection network unit is used to make the target input pin and the target output pin in a connected state. The target input pin is an input pin connected to the target media access control layer module among the multiple input pins, and the target output pin is an output pin connected to the target first-in-first-out queue module among the multiple output pins.

8. The serial deserializer according to any one of claims 1 to 4, characterized in that: The FIFO queue module is further used to adjust the bit width of the third data after receiving the third data from the target media access control layer module, so that the clock frequency of the third data is synchronized with the clock frequency of the encoding unit.

9. The serial deserializer according to any one of claims 1 to 4, characterized in that: The first state configuration machine is used to obtain the configuration instruction from the peripheral bus interface.

10. A network device, characterized in that: include: The serial deserializer, the fully interconnected network software configuration module and the multiple media access control layer modules as described in any one of claims 1 to 9, wherein the serial deserializer is connected to the multiple media access control layer modules through the fully interconnected network software configuration module.

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