Zero current detection device

Abstract

The present invention discloses a zero current detection device, including an inductor for receiving input voltage and storing current, a low-voltage side switch element and a high-voltage side switch element for switching according to the charging and discharging of the inductor, a gate driver for controlling the on and off of the low-voltage side switch element and the high-voltage side switch element, a pulse frequency modulation controller for controlling the working state of the gate driver according to the feedback voltage output from the high-voltage side switch element and a preset reference voltage, and an element zero-crossing detection circuit for generating a shutdown timing to shut down the high-voltage side switch. The scheme of the present application can accurately detect the zero current point (Zero Current Point) and solve the overcurrent phenomenon without being affected by the ringing effect generated by the digital control method.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a zero current detection device. Background Art

[0002] An inductor-based boost DC-DC switching regulator generally requires a zero current detection technique to detect the occurrence of zero inductor current in order to switch the operating state.

[0003] Figure 1 It is a structural diagram of an existing inductor-based boost DC-DC switching regulator. Figure 2 and Figure 3 Schematic diagram of an existing zero current detection circuit. Figure 2 It is a zero current detection circuit using a comparator. When the inductor current flows through the high-side transistor, the VX node voltage is compared with the VOUT voltage. The zero current detection circuit using a comparator is very intuitive, but it is easily affected by the comparator characteristics. Since the turn-on resistance of the high-side transistor of the zero current detection circuit using a comparator is small, the difference voltage between the VX node and the VOUT node is too small to compare the resulting current close to zero. Therefore, the zero current detection circuit using a comparator is easily affected by the offset voltage or delay time of the comparator. The zero current detection circuit using a comparator consumes a large amount of standby current to reduce the delay of the comparator, resulting in reduced efficiency.

[0004] Figure 3 This is a zero current detection circuit of the digital control method. To detect zero current, the zero current detection circuit of the digital control method uses the VX node falling timing monitoring. The zero current detection circuit of the digital control method does not use a comparator for zero current detection of the inductor. Therefore, in the zero current detection circuit of the digital control method, the design of the zero current detection circuit is very simple and is not affected by the comparator characteristics.

[0005] However, the zero current detection circuit using digital control may cause abnormal operation of zero current detection due to the ringing effect of the VX node voltage, and the accuracy is reduced due to delay. When the high-voltage side transistor of the zero current detection circuit using digital control is turned off, the inductor current path will be suddenly cut off, and the energy stored in the inductor and the parasitic capacitance will resonate. The zero current detection circuit using digital control will generate overcurrent due to the short off time during the initial operation, which will cause circuit damage.

[0006] Figure 4 This is a schematic diagram of the delay when zero current detection occurs, such as Figure 4As shown in the figure, a delay is generated due to the ringing effect of the switching node. The ringing effect of the switching node refers to the high-frequency oscillation phenomenon in the power conversion circuit. The ringing effect occurs at the switching node, mainly in switching power supply devices or DC-DC converters. When the switching transistor is in the ON state, the energy accumulated in the existing capacitors and inductors resonates and generates a ringing effect.

[0007] Figure 5 This is a schematic diagram of the overcurrent phenomenon when detecting zero current. Figure 5 As shown, the existing digital control method zero current detection circuit will have overcurrent phenomenon during initial operation. Therefore, in order to solve the shortcomings of the existing digital control method zero current detection circuit, a digital control configuration that is not affected by the ringing effect and a device that can solve the overcurrent phenomenon are needed.

[0008] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0009] The object of the present invention is to provide a zero current detection device for solving the problem in the prior art that the zero current detection circuit is affected by the ringing effect and has an overcurrent phenomenon.

[0010] In order to solve the above technical problems, the present invention proposes a zero current detection device, comprising:

[0011] An inductor, which receives input voltage and stores current;

[0012] A low-voltage side switch element, connected to the inductor, and configured to switch according to the charging and discharging of the inductor;

[0013] A high-voltage side switch element, connected to the inductor, and configured to switch according to the charging and discharging of the inductor;

[0014] A gate driver connected to the low-voltage side switch element and the high-voltage side switch element, and used to control the on and off of the low-voltage side switch element and the high-voltage side switch element;

[0015] A pulse frequency modulation controller, connected to the gate driver, for controlling the working state of the gate driver according to the feedback voltage outputted from the high-voltage side switch element and a preset reference voltage;

[0016] A zero-crossing detection circuit, wherein the input end of the zero-crossing detection circuit is connected to a monitoring node, the output end of the zero-crossing detection circuit is connected to the gate driver, the monitoring node is a connection point between the inductor and the low-voltage side switch element and the high-voltage side switch element, and is used to generate a shutdown timing to shut down the high-voltage side switch element.

[0017] Optionally, the zero current detection device further includes:

[0018] A comparator is connected to the pulse frequency modulation controller and is used to output a control signal to the pulse frequency modulation controller when the current flowing through the inductor exceeds a preset limiting current so that the pulse frequency modulation controller generates a signal for shutting down the high-voltage side switch element.

[0019] Optionally, two input terminals of the comparator are respectively used to receive the limiting current and the current flowing through the inductor, and the output terminal of the comparator is connected to the pulse frequency modulation controller.

[0020] Optionally, the zero-crossing detection circuit utilizes a D flip-flop to monitor a voltage change of the monitoring node.

[0021] Optionally, the zero-crossing detection circuit includes a first D flip-flop, a counter, a delay unit and a second D flip-flop;

[0022] The clock signal input terminal of the first D flip-flop is connected to the monitoring node, and the output terminal of the first D flip-flop is connected to the input terminal of the counter.

[0023] The output end of the counter is connected to the input end of the delay unit, the output end of the delay unit is connected to the clock signal input end of the second D flip-flop, and the output end of the second D flip-flop is connected to the gate driver.

[0024] Optionally, a first NOT gate is provided between the clock signal input terminal of the first D flip-flop and the monitoring node;

[0025] An input end of the first NOT gate is connected to the monitoring node, and an output end of the first NOT gate is connected to a clock signal input end of the first D flip-flop.

[0026] Optionally, a NOR gate and a second NOT gate are provided between the output end of the second D flip-flop and the gate driver;

[0027] The two input ends of the NOR gate are respectively connected to the output end of the second D flip-flop and the reset end of the second D flip-flop, the output end of the NOR gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the gate driver.

[0028] Optionally, the output end of the NOR gate is also connected to the input end of the delay device.

[0029] Optionally, the gate driver controls the low-voltage side switch element to be in an on state when the inductor is charged, and the low-voltage side switch element to be in an off state when the inductor is discharged.

[0030] Optionally, the gate driver controls the high-side switch element to be in an off state when the inductor is charged, and the high-side switch element to be in an on state when the inductor is discharged.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention proposes a zero current detection device, including an inductor for receiving input voltage and storing current, a low-voltage side switch element and a high-voltage side switch element for switching according to the charging and discharging of the inductor, a gate driver for controlling the on and off of the low-voltage side switch element and the high-voltage side switch element, a pulse frequency modulation controller for controlling the working state of the gate driver according to the feedback voltage output from the high-voltage side switch element and a preset reference voltage, and an element zero-crossing detection circuit for generating a shutdown timing to shut down the high-voltage side switch. The scheme of the present application can accurately detect the zero current point (Zero Current Point) and solve the overcurrent phenomenon without being affected by the ringing effect generated by the digital control method. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of an existing inductor-based boost DC-DC switching regulator;

[0034] Figure 2 is a schematic diagram of a zero current detection circuit using a comparator;

[0035] Figure 3 It is a zero current detection circuit of digital control mode;

[0036] Figure 4 This is a schematic diagram of the delay during zero current detection;

[0037] Figure 5 This is a schematic diagram of the overcurrent phenomenon that occurs when zero current is detected;

[0038] Figure 6 is a structural schematic diagram of a zero current detection device proposed in an embodiment of the present invention;

[0039] Figure 7 is a timing diagram of the operation of the zero current detection device proposed in the embodiment of the present invention;

[0040] Figure 8 It is a flow chart of utilizing the zero current detection device proposed in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] Please refer to Figure 6 , an embodiment of the present invention provides a zero current detection device, comprising:

[0045] Inductor L, used to receive input voltage and store current;

[0046] A low-voltage side switch element 510, connected to the inductor, and configured to switch according to the charging and discharging of the inductor;

[0047] A high-side switch element 520 connected to the inductor and configured to switch according to the charging and discharging of the inductor;

[0048] A gate driver 530 connected to the low-voltage side switch element and the high-voltage side switch element, and used to control the on and off of the low-voltage side switch element 510 and the high-voltage side switch element 520;

[0049] A pulse frequency modulation controller 540, connected to the gate driver, for controlling the working state of the gate driver 530 according to the feedback voltage outputted from the high-side switch element 520 and a preset reference voltage;

[0050] The zero-crossing detection circuit 550 has an input end connected to a monitoring node, an output end connected to the gate driver, and a monitoring node V X It is a connection point between the inductor and the low-voltage side switching element and the high-voltage side switching element, and is used to generate a turn-off timing to turn off the high-voltage side switching element.

[0051] The difference from the prior art is that this embodiment proposes a zero current detection device, including an inductor for receiving input voltage and storing current, a low-voltage side switch element and a high-voltage side switch element for switching according to the charging and discharging of the inductor, a gate driver for controlling the on and off of the low-voltage side switch element and the high-voltage side switch element, a pulse frequency modulation controller for controlling the working state of the gate driver according to the feedback voltage output from the high-voltage side switch element and a preset reference voltage, and an element zero-crossing detection circuit for generating a shutdown timing to shut down the high-voltage side switch. The scheme of the present application can accurately detect the zero current point (Zero Current Point) and solve the overcurrent phenomenon without being affected by the ringing effect generated by the digital control method.

[0052] It should be noted that, in this embodiment, the low-voltage side switch element 510 and the high-voltage side switch element 520 may be PMOS transistors or NMOS transistors.

[0053] Specifically, in this embodiment, the zero current detection device further includes:

[0054] The comparator 560 is connected to the pulse frequency modulation controller, and is used to output a control signal to the pulse frequency modulation controller when the current flowing through the inductor exceeds a preset limiting current so that the pulse frequency modulation controller generates a signal for shutting down the high-side switching element.

[0055] Specifically, in this embodiment, the two input terminals of the comparator are respectively used to receive the limiting current and the current flowing through the inductor, and the output terminal of the comparator is connected to the pulse frequency modulation controller.

[0056] Specifically, in this embodiment, the zero-crossing detection circuit uses a D flip-flop to monitor the monitoring node V X voltage changes.

[0057] Specifically, in this embodiment, the zero-crossing detection circuit includes a first D flip-flop 552, a counter 554, a delay unit 556 and a second D flip-flop 558;

[0058] The clock signal input terminal of the first D flip-flop 552 is connected to the monitoring node V XThe output terminal of the first D flip-flop 552 is connected to the input terminal of the counter 554,

[0059] The output end of the counter is connected to the input end of the delay unit, the output end of the delay unit 556 is connected to the clock signal input end of the second D flip-flop 558 , and the output end of the second D flip-flop is connected to the gate driver 530 .

[0060] Specifically, in this embodiment, the clock signal input terminal of the first D flip-flop 552 is connected to the monitoring node V X A first NOT gate is provided between the two;

[0061] An input end of the first NOT gate is connected to the monitoring node, and an output end of the first NOT gate is connected to a clock signal input end of the first D flip-flop.

[0062] Specifically, in this embodiment, a NOR gate and a second NOT gate are provided between the output end of the second D flip-flop 558 and the gate driver 530;

[0063] The two input terminals of the NOR gate are respectively connected to the output terminal of the second D flip-flop 558 and the reset terminal of the second D flip-flop 558, the output terminal of the NOR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the gate driver.

[0064] Specifically, in this embodiment, the output end of the NOR gate is also connected to the input end of the delay device.

[0065] Specifically, in this embodiment, the gate driver controls the low-voltage side switch element to be in an on state when the inductor is charged, and the low-voltage side switch element to be in an off state when the inductor is discharged.

[0066] Specifically, in this embodiment, the gate driver 530 controls the high-side switch element to be in an off state when the inductor is charged, and the high-side switch element 520 is in an on state when the inductor is discharged.

[0067] According to this embodiment, the zero current detection device 500 converts the input voltage into a higher output voltage, and detects the moment when the current across the inductor L is zero during the output process. The zero current detection device 500 can accurately synchronize the switches between the high-voltage side and the low-voltage side power transistors. Synchronization is an important factor in power conversion efficiency and stability. The zero current detection device 500 refers to a circuit that detects the moment when no current flows between the two ends of the inductor L.

[0068] The zero current detection device 500 in this embodiment includes an inductor L, a low-voltage side switch element 510 , a high-voltage side switch element 520 , a gate driver 530 , a PFM (Pulse Frequency Modulation) controller 540 , a zero-crossing detection circuit 550 , and a comparator 560 .

[0069] Inductor L at input voltage V IN When the magnetic field is used to store the current I L .

[0070] The low voltage side switch element 510 is switched according to the charge and discharge of the inductor L. The low voltage side switch element 510 is connected to the inductor L, switched to the charging temperature, and closed when switched to the discharging temperature.

[0071] The high-side switch element 520 is switched according to the charge and discharge of the inductor L. The high-side switch element 520 is connected to the inductor L, and is switched on during discharge and switched off during charge.

[0072] The gate driver 530 is provided with a gate voltage applied for switching by the low-side switch element 510 and the high-side switch element 520 .

[0073] The PFM controller 540 divides the feedback voltage V into R1 and R2. FB With reference voltage V REF The PFM controller 540 uses TON and the T of the zero-crossing detection circuit 550 through COT (Constant-On-Time). OFF The signal adjusts the pulse frequency to adjust the output voltage.

[0074] The PFM controller 540 effectively controls the output voltage. When the PFM controller 540 outputs a higher voltage, it minimizes energy loss by reducing the switching frequency, and when the output voltage is low, it maintains high power by increasing the switching frequency. When the pulse width is fixed, the PFM controller 540 controls the output voltage by modulating the pulse frequency of the input signal. The PFM controller 540 adjusts the pulse frequency according to the change of the output voltage to effectively transfer energy.

[0075] The PFM controller 540 generates a current I for charging the inductor L. L Power on T ON The PFM controller 540 allows the detected current to be ON The current limit I LIM When it is turned on, the timing T ON Switch to off timer T OFF , thereby limiting the detected current to the limit current I LIM the following.

[0076] The comparator 560 solves the over-current phenomenon generated due to the short turn-off time at the initial operation.

[0077] According to this embodiment, the zero-crossing detection circuit 550 uses a D-flip-flop to monitor and detect V X The zero-crossing detection circuit 550 does not monitor V X The node voltage is thus determined by the zero-crossing detection circuit 550 , and thus the performance of the zero-crossing detection circuit 550 is not affected by comparator characteristics such as offset and delay.

[0078] Zero crossing detection circuit 550 detects V in the D-flip flop clock in response to the edge of the signal X The zero-crossing detection circuit 550 generates a V when the PMOS / NMOS power switch is turned off. X The wrapping of the node does not affect the operation of the zero-crossing detection circuit 550 .

[0079] The D-flip-flop and V X Regardless of the connection of the node, the VX_FALLING signal is output once it is switched. The zero crossing detection circuit 550 is more robust than previous concepts because the wraparound cannot affect the output of the D-flip flop.

[0080] The zero-crossing detection circuit 550 uses a D-flip-flop to generate a discharge current I from the inductor L. L The closing time T OFF , detect that there is no phase current I between the two ends of the inductor L L The zero-crossing detection circuit 550 uses a D-flip-flop to generate a turn-off timing T based on the voltage of the node connected to the output terminal of the inductor L. OFF The zero-crossing detection circuit 550 compares the closing timing T OFF and the falling edge of the node voltage to adjust the position of the target signal.

[0081] The zero-crossing detection circuit 550 in this embodiment includes a first D flip-flop 552, a counter 554, a delay unit 556, and a second D flip-flop 558. It is understood that the components included in the zero-crossing detection circuit 550 are not limited thereto.

[0082] The first D flip-flop 552 is a delay type flip-flop that delays the input signal to the time of the clock pulse and then outputs the same signal. The first D flip-flop 552 passes the input D directly to the first D flip-flop. The first D flip-flop 552 is connected to the low-voltage side switch element 510 and stores the current Q output (VX_FALLING) of the input VX node voltage in the second D flip-flop. The first D flip-flop 552 maintains the current state when Clk is 0. When Clk is 1, the first D flip-flop 552 retains the output of the first D flip-flop as the current D value and passes the first output intact to the second D flip-flop.

[0083] The first D flip-flop 552 is connected to the low-voltage side switch element 510 and delays the time output of the clock pulse by inputting the VX_FALLING signal generated by the VX node.

[0084] The counter 554 is a circuit for counting numbers, and works in conjunction with the first D flip-flop 552. The counter 554 increases by 1 for each clock pulse. The counter 554 is triggered by the Clk of the signal input from the first D flip-flop 552 at the rising edge, and operates the up counter (UP Counter). The counter 554 is triggered by the Clk of the signal input from the first D flip-flop 552 at the falling edge, thereby starting the down counter (DOWN Counter).

[0085] The counter 554 outputs an off time (OFFTime). The counter 554 generates an off timing (TOFF) based on the VX_FALLING signal.

[0086] The delay unit 556 operates in conjunction with the counter 554. The delay unit 556 detects an active pulse edge delayed from the OFF time (OFFTime) input from the counter 554 to the clock pulse time, and then adjusts the position of the target signal.

[0087] The delay unit 556 turns off the timing T by comparing OFF The rise time of the VX_FALLING signal and the rise time of the VX_FALLING signal adjust the position of the target signal. The delay unit 556 is closed at the timing T OFF When the target signal is shorter than the VX_FALLING signal, the target signal is output by increasing the delay of the target signal. OFF When the target signal is greater than the VX_FALLING signal, the target signal is outputted by reducing the delay of the target signal. When the off timing (TOFF) is consistent with the VX_FALLING signal, the delay unit 556 detects that the current (IL) value on the inductor L is zero.

[0088] The second D flip-flop 558 is a delay type flip-flop that delays the input signal to the time of the clock pulse and then outputs the same signal. The second D flip-flop 558 directly passes the input D to the first D flip-flop. The second D flip-flop 558 stores (maintains) the target signal input from the delay unit 556 in the second D flip-flop. The second D flip-flop 558 maintains the current state when Clk is 0. When Clk is 1, the second D flip-flop 558 keeps the output of the first D flip-flop at the current D value and passes the first output intact to the second D flip-flop.

[0089] The second D flip-flop 558 outputs the target signal input from the delay unit 556 at a time delayed by the clock pulse.

[0090] The comparator 560 detects the sensed current and the set limit current I LIM value.

[0091] Figure 7 5 is a schematic diagram of the process of detecting zero current according to this embodiment. The delay unit 556 of the zero-crossing detection circuit 550 adjusts the position of the target signal. The delay unit 556 of the zero-crossing detection circuit 550 compares the VX_FALLING signal generated by the VX node with the closing timing T OFF The delay unit 556 of the zero-crossing detection circuit 550 closes the timing T by comparing OFF The rise time of VX_FALLING and the rise time of VX_FALLING are used to adjust the position of the target signal.

[0092] The delay unit 556 of the zero-crossing detection circuit 550 turns off the timing T OFF When it is shorter than the VX_FALLING signal, the target signal delay will be increased, and the closing timing T OFF When it is longer than the VX_FALLING signal, the delay of the target signal will be reduced.

[0093] The delay unit 556 of the zero-crossing detection circuit 550 performs a feedback operation, and when the VX_FALLING signal matches the off timing (TOFF), the inductor (L) current (IL) value is 0. The target signal includes a Flag signal for controlling the end point of the off time (OFFTime).

[0094] Figure 8 : is a schematic diagram showing the zero current detection process using a comparator in this embodiment. The comparator 560 detects the detected current and the preset limiting current I LIM The zero-crossing detection circuit 550 sets the off time (OFFTime). The PFM controller 540 sets the off time (OFFTime) when the detected current reaches the limit current I during the on time (ONTime). LIMWhen the ON timer is turned off, the system works in the OFF time mode. LIM Contains the Flag signal, which is used to control the end point of the opening timing (ONTime).

[0095] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0096] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A zero current detection device, characterized in that: include: An inductor, which receives input voltage and stores current; A low-voltage side switch element, connected to the inductor, and configured to switch according to the charging and discharging of the inductor; A high-voltage side switch element, connected to the inductor, and configured to switch according to the charging and discharging of the inductor; A gate driver connected to the low-voltage side switch element and the high-voltage side switch element, and used to control the on and off of the low-voltage side switch element and the high-voltage side switch element; A pulse frequency modulation controller, connected to the gate driver, for controlling the working state of the gate driver according to the feedback voltage outputted from the high-voltage side switch element and a preset reference voltage; A zero-crossing detection circuit, wherein the input end of the zero-crossing detection circuit is connected to a monitoring node, the output end of the zero-crossing detection circuit is connected to the gate driver, the monitoring node is a connection point between the inductor and the low-voltage side switch element and the high-voltage side switch element, and is used to generate a turn-off timing to turn off the high-voltage side switch element; The zero-crossing detection circuit includes a first D flip-flop, a counter, a delay unit and a second D flip-flop; The clock signal input terminal of the first D flip-flop is connected to the monitoring node, and the output terminal of the first D flip-flop is connected to the input terminal of the counter. The output end of the counter is connected to the input end of the delay unit, the output end of the delay unit is connected to the clock signal input end of the second D flip-flop, and the output end of the second D flip-flop is connected to the gate driver.

2. The zero current detection device according to claim 1, characterized in that: The zero current detection device also includes: A comparator is connected to the pulse frequency modulation controller and is used to output a control signal to the pulse frequency modulation controller when the current flowing through the inductor exceeds a preset limiting current so that the pulse frequency modulation controller generates a signal for shutting down the high-voltage side switch element.

3. The zero current detection device according to claim 2, characterized in that: The two input terminals of the comparator are used to receive the limiting current and the current flowing through the inductor respectively, and the output terminal of the comparator is connected to the pulse frequency modulation controller.

4. The zero current detection device according to claim 3, characterized in that: The zero-crossing detection circuit uses a D flip-flop to monitor the voltage change of the monitoring node.

5. The zero current detection device according to claim 1, characterized in that: A first NOT gate is provided between the clock signal input terminal of the first D flip-flop and the monitoring node; An input end of the first NOT gate is connected to the monitoring node, and an output end of the first NOT gate is connected to a clock signal input end of the first D flip-flop.

6. The zero current detection device according to claim 1, characterized in that: A NOR gate and a second NOT gate are provided between the output end of the second D flip-flop and the gate driver; The two input ends of the NOR gate are respectively connected to the output end of the second D flip-flop and the reset end of the second D flip-flop, the output end of the NOR gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is connected to the gate driver.

7. The zero current detection device according to claim 6, characterized in that: The output end of the NOR gate is also connected to the input end of the delay device.

8. The zero current detection device according to claim 1, characterized in that: The gate driver controls the low-voltage side switch element to be in an on state when the inductor is charged, and the low-voltage side switch element to be in an off state when the inductor is discharged.

9. The zero current detection device according to claim 1, characterized in that: The gate driver controls the high-side switch element to be in an off state when the inductor is charged, and the high-side switch element to be in an on state when the inductor is discharged.

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