p-GaN gate high electron mobility transistor model and its modeling method

Abstract

The present invention relates to a p-GaN gate high electron mobility transistor model and a modeling method thereof, wherein the model comprises: a basic model, comprising a GaN HEMT device model, wherein the GaN HEMT device model comprises a gate-to-source part, a drain-to-source part, and a gate resistor located between a gate node and a gate; a sub-model, comprising a first sub-circuit, a second sub-circuit, and a third sub-circuit connected in series with each other, wherein the first sub-circuit comprises a diode D1 and a gate-source voltage-controlled resistor R2 connected in parallel with each other, the second sub-circuit comprises a resistor R1 and a capacitor C1 connected in parallel with each other, and the third sub-circuit comprises a diode D2 and a gate-drain voltage-controlled resistor R3 connected in parallel with each other; and the sub-model is connected in series with the gate resistor. The present invention can effectively solve the problem that the device model of the traditional p-GaN gate HEMT is insufficient in modeling threshold voltage drift, prevents the potential risk of circuit function failure caused by threshold voltage drift, and greatly reduces the risk and cost of integrated circuit design.

Description

Technical Field

[0001] The invention relates to a high electron mobility transistor, in particular to a p-GaN gate high electron mobility transistor model, and also to a modeling method of the p-GaN gate high electron mobility transistor model. Background Art

[0002] Gallium nitride high electron mobility transistor (GaN-HEMT) is a heterojunction field effect transistor with wide applications in the field of power electronics. It mainly uses the two-dimensional electron gas (2DEG) formed by the AlGaN / GaN heterojunction as the conduction channel, and has excellent electrical characteristics such as low on-resistance, low conduction loss and high-frequency switching. The p-GaN gate HEMT grows a positively charged (P-type) GaN layer on top of the AlGaN barrier layer of the HEMT, which can achieve the device gate in the off state without gate voltage control, that is, the turn-on voltage is greater than 0V, and it is a normally off (enhancement) device.

[0003] The model is a bridge between device technology and circuit design. It provides circuit designers with device-level model parameters for circuit simulation. An accurate and practical model is the basic guarantee for accurate circuit design. Among the many reliability issues of p-GaN gate HEMT devices, threshold voltage drift is one of the most important problems. When the device starts working, the drift of the threshold voltage will lead to the potential risk of circuit function failure. Although the physical models ASM-HEMT (Advanced Spice Model for GaN HEMT) and MVSG (MIT Virtual Source GaN HEMT) certified by the Compact Model Coalition (CMC) include most of the physical effects, the impact of threshold voltage drift is not considered. Therefore, a modeling of the threshold voltage drift model for p-GaN gate HEMT devices has become urgently needed. Summary of the invention

[0004] Based on this, it is necessary to provide a threshold voltage drift model of a p-GaN gate HEMT device and a modeling method thereof.

[0005] A p-GaN gate high electron mobility transistor model, comprising: a basic model, comprising a GaN HEMT device model, the GaN HEMT device model comprising a gate-to-source part, a drain-to-source part and a gate resistor located between a gate node and a gate; a sub-model, comprising a first sub-circuit, a second sub-circuit and a third sub-circuit located between a first end and a second end and connected in series with each other, the first sub-circuit comprising a diode D1 and a gate-source voltage-controlled resistor R2 connected in parallel with each other, the second sub-circuit comprising a resistor R1 and a capacitor C1 connected in parallel with each other, the third sub-circuit comprising a diode D2 and a gate-drain voltage-controlled resistor R3 connected in parallel with each other; the anode and cathode of the diode D2 are closer to the first end and the cathode is closer to the second end, the anode and cathode of the diode D1 are closer to the second end and the cathode is closer to the first end; the sub-model is connected in series with the gate resistor; wherein the sub-model is located between the gate and the gate node in the GaN HEMT device model, the first end is used to connect the gate, and the second end is used to connect the gate node; or the sub-model is located between the gate and the gate node in the GaN HEMT device model, the first end is used to connect the gate, and the second end is used to connect the gate node; Between the gate signal source and the gate in the HEMT device model, the first end is used to connect the gate signal source, and the second end is used to connect the gate.

[0006] The above-mentioned p-GaN gate high electron mobility transistor model (hereinafter referred to as the overall model) adds a sub-model that can simulate defects and traps that cause threshold voltage drift on the basis of the basic model. The sub-model is mainly composed of component models such as RC networks, so it has practical physical significance. The first sub-circuit determines the storage charge discharge capability, and the third sub-circuit determines the storage charge injection capability, and the two jointly affect the gate current value Ig. The gate current value Ig and the resistance value of the resistor R1 determine the threshold voltage drift of the overall model, and the resistance value of the resistor R1 and the capacitance value of the capacitor C1 determine the time constant of the threshold voltage drift of the overall model. It can effectively solve the problem of insufficient modeling of threshold voltage drift in the device model of the traditional p-GaN gate HEMT, prevent the potential risk of circuit function failure caused by threshold voltage drift, and greatly reduce the risk and cost of integrated circuit design.

[0007] In one embodiment, the sub-models are connected in a connection order from the first end to the second end: first sub-circuit - second sub-circuit - third sub-circuit.

[0008] In one embodiment, the resistance value of the gate-source voltage-controlled resistor R2 is m×(Vgs+0.001) -1 ; Where m is the gate-source voltage control coefficient, and Vgs is the gate-source voltage.

[0009] In one embodiment, the resistance value of the gate-drain voltage-controlled resistor R3 is n×(Vdg+0.001)-1 ; Where n is the drain-gate voltage control coefficient, and Vdg is the drain-gate voltage.

[0010] In one of the embodiments, the p-GaN gate high electron mobility transistor model further includes a gate current model.

[0011] In one of the embodiments, the GaN HEMT device model is a GaN HEMT device model with a gate leakage model.

[0012] A modeling method for a p-GaN gate high electron mobility transistor model comprises: establishing the p-GaN gate high electron mobility transistor model described in any of the above embodiments; acquiring electrical characteristic data of the p-GaN gate high electron mobility transistor, and extracting parameters of the basic model in combination with device structure parameters of the p-GaN gate high electron mobility transistor; acquiring drift data of the threshold voltage over time of the p-GaN gate high electron mobility transistor under different gate-drain voltages, and extracting parameters of the sub-model.

[0013] The modeling method of the p-GaN gate high electron mobility transistor model adds a sub-model that can simulate defects and traps that cause threshold voltage drift to the basic model, and then extracts model parameters for the basic model and the sub-model. This can effectively solve the problem that the traditional p-GaN gate HEMT device model is insufficient in modeling threshold voltage drift, prevent the potential risk of circuit function failure caused by threshold voltage drift, and greatly reduce the risk and cost of integrated circuit design.

[0014] In one embodiment, the sub-model is defined using Verilog-A code, SPICE code, or circuit netlist.

[0015] In one embodiment, the electrical characteristic data includes at least one of a transfer curve, an output curve, and a leakage curve.

[0016] In one embodiment, the step of acquiring the threshold voltage drift data over time includes: performing a threshold voltage drift test, wherein the threshold voltage drift test is a test under static stress and / or transient stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0018] Figure 1is a schematic cross-sectional view of an exemplary p-GaN gate HEMT;

[0019] Figure 2 is a schematic diagram of gate circuit equivalent and charge storage of an exemplary p-GaN gate HEMT;

[0020] Figure 3 This is a measured graph of the threshold voltage drift of a commercial p-GaN gate HEMT product;

[0021] Figure 4 is a simplified circuit model of an exemplary p-GaN gate HEMT;

[0022] Figure 5 is a simplified circuit diagram of a p-GaN gate high electron mobility transistor model in an embodiment of the present application;

[0023] Figure 6 is a flow chart of a modeling method of a p-GaN gate high electron mobility transistor model in an embodiment of the present application;

[0024] Figure 7 It is the circuit simulation result of the p-GaN gate high electron mobility transistor model in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0028] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0029] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0031] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0032] Figure 1 The cross-sectional schematic diagram of an exemplary p-GaN gate HEMT includes: a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, and a p-GaN layer 5. The channel layer 3 and the barrier layer 4 are in contact to form an electron channel layer 3a (i.e., a two-dimensional electron gas 2DEG). A first metal electrode 6 and a third metal electrode 7 of ohmic contact are formed on the barrier layer 4, and a second metal electrode 8 of Schottky contact is formed on the p-GaN layer 5.

[0033] The inventor believes that the high-barrier second metal electrode 8 will form a Schottky diode D with the p-GaN layer 5. sch , while the channel layer 3, barrier layer 4 and p-GaN layer 5 will form a PIN diode D pin , that is, the corresponding structure will form two back-to-back diodes, such as Figure 2 These two back-to-back diodes cause the potential of the p-GaN layer 5 to float, and charge storage will occur in the p-GaN layer 5 under different gate-drain voltage stresses, causing reliability problems such as device threshold voltage drift, see Figure 3 . Figure 3 This is a measured graph of the threshold voltage drift of a commercial p-GaN gate HEMT product. Figure 4This is a simplified circuit model of an exemplary p-GaN gate HEMT, including the gate resistor between the gate g and the gate node gi, the gate-to-source portion between the source s and the source node si (i.e., source access-resistance, abbreviated as S-ACCRES), and the drain-to-source portion between the drain d and the drain node di (i.e., drain access-resistance, abbreviated as D-ACCRES). This model does not take into account the threshold voltage drift of the device.

[0034] An exemplary GaN HEMT model achieves threshold and current correction under frequency and drain voltage by establishing correction equations for the two parameters of frequency and drain voltage. Another exemplary GaN HEMT model further adds temperature coefficient and AC model fitting, but its essence is still to correct traditional model parameters. This type of method needs to consider whether the influencing factors of threshold drift are comprehensive, and most of the fitting coefficients have no physical meaning. However, since some traditional models do not have the parameter of threshold voltage, the model of the correction coefficient method is not compatible. In addition, in transient simulation, due to the influence of the correction coefficient, the threshold voltage only changes from one value to another, and cannot reflect the dynamic change of the threshold voltage during the transient process.

[0035] The present application proposes a p-GaN gate high electron mobility transistor model, which simulates the threshold voltage drift caused by the charge storage phenomenon of the p-GaN layer 5 of the device by establishing a threshold voltage drift sub-model connected between the gate g and the gate node gi of the basic model, or between the gate signal source and the gate g, so as to effectively and simply solve the problem of inaccurate simulation of the threshold voltage drift of the traditional GaN HEMT model.

[0036] Figure 5 It is a simplified circuit diagram of a p-GaN gate high electron mobility transistor model in an embodiment of the present application, including a basic model 10 and a sub-model 20. The basic model 10 includes a GaN HEMT device model, and the GaN HEMT device model includes a source node si, a drain node di, a gate node gi, a gate-to-source portion (S-ACCRES), a drain-to-source portion (D-ACCRES), and a gate resistor (Gate Resistor) located between the gate node gi and the gate g. The GaN HEMT device model can adopt a traditional p-GaN HEMT model, and its structure is not described in detail here. In one embodiment of the present application, the GaN HEMT device model is a GaN HEMT device model with a gate leakage model.

[0037] The sub-model 20 includes a first sub-circuit, a second sub-circuit and a third sub-circuit located between the first terminal a and the second terminal b of the sub-model 20 and connected in series with each other. The first sub-circuit includes a diode D1 and a gate-source voltage-controlled resistor R2 connected in parallel, the second sub-circuit includes a resistor R1 and a capacitor C1 connected in parallel, and the third sub-circuit includes a diode D2 and a gate-drain voltage-controlled resistor R3 connected in parallel. The diode D1 is used as a charge discharge diode, and the diode D2 is used as a charge injection diode. The anode and cathode of the diode D2 are closer to the first terminal a, and the cathode is closer to the second terminal b. The anode and cathode of the diode D1 are closer to the second terminal b, and the cathode is closer to the first terminal a. "Close" here means that the components (component models) are closer in the connection relationship of the circuit, rather than the distance of the spatial position of the device. Among them, the first sub-circuit determines the storage charge discharge capacity, and the third sub-circuit determines the storage charge injection capacity, and both affect the gate current value Ig together. The gate current value Ig and the resistance value of the resistor R1 determine the threshold voltage drift of the overall model, and the resistance value of the resistor R1 and the capacitance value of the capacitor C1 determine the time constant of the threshold voltage drift of the overall model.

[0038] Sub-model 20 is connected in series with the gate resistor of the GaN HEMT device model. Figure 5 In the illustrated embodiment, the sub-model 10 is located between the gate g and the gate node gi in the GaN HEMT device model, the first terminal a is used to connect the gate g, and the second terminal b is used to connect the gate node gi. In other embodiments, the sub-model 20 may also be located between the gate signal source and the gate g in the GaN HEMT device model, the first terminal a is used to connect the gate signal source, and the second terminal b is used to connect the gate g.

[0039] The above-mentioned p-GaN gate high electron mobility transistor model (hereinafter referred to as the overall model) is used to simulate the enhancement mode (i.e., the gate turn-on voltage is greater than 0V) p-GaN gate HEMT. It adds a sub-model 20 that can simulate defects and traps that cause threshold voltage drift on the basis of the basic model 10. The sub-model 20 is mainly composed of component models such as RC networks, so it has practical physical significance. Among them, the first sub-circuit determines the storage charge discharge capability, and the third sub-circuit determines the storage charge injection capability, and the two jointly affect the gate current value Ig. The gate current value Ig and the resistance value of the resistor R1 determine the threshold voltage drift of the overall model, and the resistance value of the resistor R1 and the capacitance value of the capacitor C1 determine the time constant of the threshold voltage drift of the overall model. It can effectively solve the problem that the device model of the traditional p-GaN gate HEMT does not adequately model the threshold voltage drift, prevent the potential risk of circuit function failure caused by the threshold voltage drift, and greatly reduce the risk and cost of integrated circuit design. The present application adopts a sub-model 20 for simulating threshold voltage drift based on an RC network, which essentially simulates the defects and traps that cause threshold voltage drift, is physically meaningful and compatible with traditional models. It can effectively and simply solve the problems of insufficient modeling of threshold voltage drift, lack of physical meaning, and incompatibility of the device model of traditional p-GaN gate HEMT.

[0040] In one embodiment of the present application, the gate leakage model of the device in the overall model is provided by combining the basic model 10 and the sub-model 20 .

[0041] exist Figure 5 As shown, the sub-model 20 is connected in the order of the first sub-circuit, the second sub-circuit, and the third sub-circuit from the first terminal a to the second terminal b.

[0042] In one embodiment of the present application, the resistance value of the gate-source voltage-controlled resistor R2 is m×(Vgs+0.001) -1 . Where m is the gate-source voltage control coefficient, and Vgs is the gate-source voltage.

[0043] In one embodiment of the present application, the resistance value of the gate-drain voltage-controlled resistor R3 is n×(Vdg+0.001) -1 ; Where n is the drain-gate voltage control coefficient, and Vdg is the drain-gate voltage.

[0044] In one embodiment of the present application, the overall model includes a gate current model.

[0045] In one embodiment of the present application, the sub-model 20 may be defined using Verilog-A code, or may be defined using SPICE code or a circuit netlist.

[0046] The present application accordingly provides a modeling method for a p-GaN gate high electron mobility transistor model. Figure 6 : is a flow chart of a modeling method of a p-GaN gate high electron mobility transistor model in an embodiment of the present application, comprising the following steps:

[0047] S610, establishing a p-GaN gate HEMT model.

[0048] A p-GaN gate high electron mobility transistor model as described in any of the above embodiments is established.

[0049] S620, acquiring electrical characteristic data of the p-GaN gate HEMT, and extracting parameters of the basic model in combination with device structure parameters of the p-GaN gate HEMT.

[0050] In one embodiment of the present application, the acquired electrical characteristic data includes at least one of a transfer curve, an output curve and a leakage curve, and the basic model parameters are fitted and extracted. Step S620 can adopt conventional technology, which is not described here.

[0051] S630 , obtaining the drift data of the threshold voltage of the p-GaN gate HEMT over time, and extracting parameters of the sub-model.

[0052] The threshold voltage drift data of p-GaN gate high electron mobility transistors with different gate-drain voltages is obtained, and the parameters of the sub-model are extracted.

[0053] In one embodiment of the present application, the drift data of the threshold voltage over time is obtained by performing a threshold voltage drift test, which is a test under static stress and / or transient stress. The threshold voltage drift test is performed according to demand, and the threshold voltage drift amount under different test conditions will be inconsistent. In practice, the test conditions can be set according to the application requirements for testing, and then the parameters can be extracted.

[0054] The modeling method of the p-GaN gate high electron mobility transistor model adds a sub-model that can simulate defects and traps that cause threshold voltage drift to the basic model, and then extracts model parameters for the basic model and the sub-model. This can effectively solve the problem that the traditional p-GaN gate HEMT device model is insufficient in modeling threshold voltage drift, prevent the potential risk of circuit function failure caused by threshold voltage drift, and greatly reduce the risk and cost of integrated circuit design.

[0055] In one embodiment of the present application, the parameter extraction in steps S620 and S630 can be implemented by commercial software such as Agilent's MBP (Model Builder Programmer) or Agilent's IC-CAP. By extracting the basic model parameters and sub-model parameters, accurate modeling of the threshold voltage drift of the p-GaN gate HEMT is achieved. Figure 7 This is the circuit simulation result of the p-GaN gate high electron mobility transistor model in an embodiment of the present application. It can be seen that the present application can achieve dynamic changes in transient state to simulate the actual situation.

[0056] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0057] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0058] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A p-GaN gate high electron mobility transistor model, characterized in that: include: A basic model, including a GaN HEMT device model, wherein the GaN HEMT device model includes a gate-to-source portion, a drain-to-source portion, and a gate resistor between a gate node and a gate; A sub-model, comprising a first sub-circuit, a second sub-circuit and a third sub-circuit located between a first end and a second end and connected in series with each other, wherein the first sub-circuit comprises a diode D1 and a gate-source voltage-controlled resistor R2 connected in parallel with each other, the second sub-circuit comprises a resistor R1 and a capacitor C1 connected in parallel with each other, and the third sub-circuit comprises a diode D2 and a gate-drain voltage-controlled resistor R3 connected in parallel with each other; the anode and the cathode of the diode D2 are closer to the first end and the cathode is closer to the second end, and the anode and the cathode of the diode D1 are closer to the second end and the cathode is closer to the first end; the sub-model is connected in series with the gate resistor; The sub-model is located between the gate and the gate node in the GaN HEMT device model, the first end is used to connect the gate, and the second end is used to connect the gate node; or the sub-model is located between the gate signal source and the gate in the GaN HEMT device model, the first end is used to connect the gate signal source, and the second end is used to connect the gate.

2. The p-GaN gate high electron mobility transistor model according to claim 1, characterized in that: The sub-models are connected in a first sub-circuit, a second sub-circuit, and a third sub-circuit in a connection order from the first end to the second end.

3. The p-GaN gate high electron mobility transistor model according to claim 1, characterized in that: The resistance value of the gate-source voltage-controlled resistor R2 is m×(Vgs+0.001) -1 ; Where m is the gate-source voltage control coefficient, and Vgs is the gate-source voltage.

4. The p-GaN gate high electron mobility transistor model according to claim 1, characterized in that: The resistance value of the gate-drain voltage-controlled resistor R3 is n×(Vdg+0.001) -1 ; Where n is the drain-gate voltage control coefficient, and Vdg is the drain-gate voltage.

5. The p-GaN gate high electron mobility transistor model according to claim 1, characterized in that: A gate current model is also included.

6. The p-GaN gate high electron mobility transistor model according to claim 1, characterized in that: The GaN HEMT device model is a GaN HEMT device model with a gate leakage model.

7. A modeling method for a p-GaN gate high electron mobility transistor model, comprising: Establishing a p-GaN gate high electron mobility transistor model as described in any one of claims 1 to 6; Acquiring electrical characteristic data of a p-GaN gate high electron mobility transistor, and extracting parameters of the basic model in combination with device structure parameters of the p-GaN gate high electron mobility transistor; The threshold voltage drift data over time of the p-GaN gate high electron mobility transistor under different gate-drain voltages is obtained, and parameters of the sub-model are extracted.

8. The modeling method of the p-GaN gate high electron mobility transistor model according to claim 7, characterized in that: The sub-model is defined by using Verilog-A code, SPICE code, or circuit netlist.

9. The modeling method of the p-GaN gate high electron mobility transistor model according to claim 7, characterized in that: The electrical characteristic data includes at least one of a transfer curve, an output curve and a leakage curve.

10. The modeling method of the p-GaN gate high electron mobility transistor model according to claim 7, characterized in that: The step of acquiring the threshold voltage drift data over time includes: performing a threshold voltage drift test, wherein the threshold voltage drift test is a test under static stress and / or transient stress.

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