Analog-to-digital conversion device, digital signal calibration method and device

Abstract

The present specification provides an analog-to-digital conversion device, a calibration method and an apparatus for digital signals. The analog-to-digital conversion device includes a multi-stage analog-to-digital conversion module. A comparison module is connected between each stage of the analog-to-digital conversion module. The voltage analog signal that cannot be accurately processed by the previous stage of the analog-to-digital conversion module is calculated by the comparison module, and is input into the next stage of the analog-to-digital conversion module for further processing. The calibration coefficient of the previous analog-to-digital conversion module is determined based on the subsequent analog-to-digital conversion module by utilizing the characteristics of the pulse signal. The calibrated conversion numbers output by all analog-to-digital conversion modules are calculated in the digital logic processing module as the digital representation corresponding to the voltage analog signal. Finally, it is ensured that the digital representation effect of a single analog-to-digital converter with high resolution can be achieved by using multiple low-resolution analog-to-digital conversion modules, and the accuracy of the calibrated digital representation can also reach the accuracy level of the single analog-to-digital converter.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to analog-to-digital conversion equipment, and digital signal calibration methods and devices. Background Art

[0002] Analog-to-Digital Converter (ADC) is an electronic device that converts continuous analog signals (such as voltage, current, sound signal, etc.) into discrete digital signals. By sampling and quantizing analog signals into digital signals, computers or digital processing systems can process and store these digital signals.

[0003] The key performance of an analog-to-digital converter is resolution. The higher the resolution, the more accurately the analog-to-digital converter can capture subtle voltage changes and provide a more precise digital representation. Related technologies generally improve the processing accuracy of the analog-to-digital converter by increasing the resolution of the analog-to-digital converter. However, the resolution of the analog-to-digital converter is positively correlated with its circuit scale and design complexity. Therefore, although increasing the resolution of the analog-to-digital converter can improve the processing accuracy to a certain extent, there are also problems such as cumbersome design and high cost. Summary of the invention

[0004] In order to overcome the problems existing in the related art, this specification provides an analog-to-digital conversion device, a digital signal calibration method and an apparatus.

[0005] According to a first aspect of an embodiment of this specification, an analog-to-digital conversion device is provided, the device comprising a pulse output module, at least one adjustable delay circuit, at least two analog-to-digital conversion modules and at least one comparison module, each analog-to-digital conversion module is arranged in sequence and the least significant bit value LSB of the subsequent analog-to-digital conversion module is less than the LSB of the previous analog-to-digital conversion module, when any analog-to-digital conversion module calibrates its previous analog-to-digital conversion module, the any analog-to-digital conversion module is used as a reference module and its previous analog-to-digital conversion module is used as a module to be calibrated, wherein:

[0006] The pulse output module outputs the pulse signal to each analog-to-digital conversion module connected thereto;

[0007] Any adjustable delay circuit adjusts its delay interval parameter in each calibration cycle, and simultaneously sends an enable signal to the module to be calibrated and the reference module connected thereto, so that the two modules receive the pulse signal simultaneously;

[0008] Any analog-to-digital conversion module receives the voltage analog signal and the pulse signal, and outputs the conversion digital corresponding to the voltage analog signal and the synchronization digital corresponding to the pulse signal to the digital logic processing module connected thereto, and outputs the voltage conversion signal corresponding to the conversion digital to the comparison module connected thereto;

[0009] Any comparison module receives the voltage analog signal and the voltage conversion signal output by the analog-to-digital conversion module connected thereto, and outputs the difference between the voltage analog signal and the voltage conversion signal as a new voltage analog signal to the comparison module and the analog-to-digital conversion module connected thereto;

[0010] The digital logic processing module receives the first synchronization number outputted by the module to be calibrated for the first time in any calibration cycle and the second synchronization number outputted by the reference module for the first time in any calibration cycle; and, for the first first synchronization number greater than zero, determines the calibration coefficient of the module to be calibrated based on the first synchronization number and the corresponding second synchronization number, and performs calibration processing on the conversion number outputted by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion number corresponding to the module to be calibrated;

[0011] After determining the calibrated conversion numbers corresponding to the modules to be calibrated, the digital logic processing module uses the sum of the calibrated conversion numbers and the corresponding conversion numbers as the digital representation corresponding to the voltage analog signal.

[0012] According to a second aspect of an embodiment of this specification, a digital signal calibration method is provided, the method being applied to a digital logic processing module in the analog-to-digital conversion device as described in the first aspect, the method comprising:

[0013] Acquire a first synchronization number outputted for the first time by the module to be calibrated in any calibration period and a second synchronization number outputted for the first time by the reference module in any calibration period;

[0014] For a first synchronization number greater than zero, determining a calibration coefficient of the module to be calibrated based on the first synchronization number and a corresponding second synchronization number;

[0015] Based on the calibration coefficient, the conversion digital output by the module to be calibrated is calibrated to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

[0016] According to a third aspect of the embodiments of this specification, a digital signal calibration device is provided, the device is applied to a digital logic processing module in the analog-to-digital conversion device as described in the first aspect, and the device includes:

[0017] An acquisition module, used for acquiring a first synchronization number outputted for the first time by the module to be calibrated in any calibration period and a second synchronization number outputted for the first time by the reference module in any calibration period;

[0018] A calibration coefficient determination module, configured to determine, for a first synchronization number greater than zero, a calibration coefficient of the module to be calibrated based on the first synchronization number and a corresponding second synchronization number;

[0019] The digital representation calibration module is used to calibrate the conversion digital output by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

[0020] According to a fourth aspect of an embodiment of this specification, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method described in the second aspect are implemented.

[0021] According to a fifth aspect of the embodiments of this specification, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the steps of the method described in the second aspect are implemented.

[0022] The technical solutions provided by the embodiments of this specification may have the following beneficial effects:

[0023] The analog-to-digital conversion device designed in this scheme includes a multi-stage analog-to-digital conversion module, and a comparison module is connected between each stage of the analog-to-digital conversion module. The voltage analog signal that cannot be accurately processed by the previous stage of the analog-to-digital conversion module is calculated by the comparison module, and is input into the next stage of the analog-to-digital conversion module for further processing. In addition, by utilizing the characteristics of the pulse signal, the calibration coefficient of the previous analog-to-digital conversion module is determined based on the subsequent analog-to-digital conversion module. The calibrated conversion numbers output by all analog-to-digital conversion modules are calculated in the digital logic processing module as the digital representation corresponding to the voltage analog signal. Finally, it is ensured that the digital representation effect of a single analog-to-digital converter with high resolution can be achieved by using multiple low-resolution analog-to-digital conversion modules, and the accuracy of the calibrated digital representation can also reach the accuracy level of the single analog-to-digital converter.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0026] Figure 1 It is a structural schematic diagram of an analog-to-digital conversion device including two analog-to-digital conversion modules according to an exemplary embodiment of this specification.

[0027] Figure 2 This is a schematic diagram of an analog-to-digital conversion device including two analog-to-digital conversion modules performing analog-to-digital conversion processing according to an exemplary embodiment of this specification.

[0028] Figure 3 It is a schematic diagram of determining a calibration coefficient of an analog-to-digital conversion device including two analog-to-digital conversion modules according to an exemplary embodiment of this specification.

[0029] Figure 4 It is a schematic diagram of a calibration principle shown in this specification according to an exemplary embodiment.

[0030] Figure 5 It is a structural schematic diagram of an analog-to-digital conversion device including three analog-to-digital conversion modules according to an exemplary embodiment of this specification.

[0031] Figure 6 This is a schematic diagram of an analog-to-digital conversion device including three analog-to-digital conversion modules performing analog-to-digital conversion processing according to an exemplary embodiment of this specification.

[0032] Figure 7 It is a schematic diagram of determining a calibration coefficient of an analog-to-digital conversion device including three analog-to-digital conversion modules according to an exemplary embodiment of this specification.

[0033] Figure 8 It is a schematic diagram of determining a calibration coefficient of another analog-to-digital conversion device including three analog-to-digital conversion modules according to an exemplary embodiment of this specification.

[0034] Fig. 9 The flowchart of a digital signal calibration method is shown in this specification according to an exemplary embodiment.

[0035] Fig.10 It is a structural schematic diagram of an electronic device according to an exemplary embodiment of the present specification.

[0036] Fig.11 It is a block diagram of a digital signal calibration device shown in this specification according to an exemplary embodiment. DETAILED DESCRIPTION

[0037] The key performance of an analog-to-digital converter is resolution. The higher the resolution, the more accurately the analog-to-digital converter can capture subtle voltage changes and provide a more precise digital representation. Related technologies generally improve the processing accuracy of the analog-to-digital converter by increasing the resolution of the analog-to-digital converter. However, the resolution of the analog-to-digital converter is positively correlated with its circuit scale and design complexity. Therefore, although increasing the resolution of the analog-to-digital converter can improve the processing accuracy to a certain extent, there are also problems such as cumbersome design and high cost.

[0038] In view of the above technical problems, the present invention proposes an analog-to-digital conversion device, which realizes the high conversion accuracy of a single high-resolution analog-to-digital converter by cooperating with multiple levels of coarse-resolution analog-to-digital converters.

[0039] Specifically, the analog-to-digital conversion device includes a pulse output module, at least one adjustable delay circuit, at least two analog-to-digital conversion modules and at least one comparison module. The analog-to-digital conversion modules are arranged in sequence and the least significant bit value LSB of the subsequent analog-to-digital conversion module is less than the LSB of the previous analog-to-digital conversion module. When any analog-to-digital conversion module calibrates its previous analog-to-digital conversion module, the any analog-to-digital conversion module is used as a reference module and its previous analog-to-digital conversion module is used as a module to be calibrated, wherein:

[0040] The pulse output module outputs the pulse signal to each analog-to-digital conversion module connected thereto;

[0041] Any adjustable delay circuit adjusts its delay interval parameter in each calibration cycle, and simultaneously sends an enable signal to the module to be calibrated and the reference module connected thereto, so that the two modules receive the pulse signal simultaneously;

[0042] Any analog-to-digital conversion module receives the voltage analog signal and the pulse signal, and outputs the conversion digital corresponding to the voltage analog signal and the synchronization digital corresponding to the pulse signal to the digital logic processing module connected thereto, and outputs the voltage conversion signal corresponding to the conversion digital to the comparison module connected thereto;

[0043] Any comparison module receives the voltage analog signal and the voltage conversion signal output by the analog-to-digital conversion module connected thereto, and outputs the difference between the voltage analog signal and the voltage conversion signal as a new voltage analog signal to the comparison module and the analog-to-digital conversion module connected thereto;

[0044] The digital logic processing module receives the first synchronization number outputted by the module to be calibrated for the first time in any calibration cycle and the second synchronization number outputted by the reference module for the first time in any calibration cycle; and, for the first first synchronization number greater than zero, determines the calibration coefficient of the module to be calibrated based on the first synchronization number and the corresponding second synchronization number, and performs calibration processing on the conversion number outputted by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion number corresponding to the module to be calibrated;

[0045] After determining the calibrated conversion numbers corresponding to the modules to be calibrated, the digital logic processing module uses the sum of the calibrated conversion numbers and the corresponding conversion numbers as the digital representation corresponding to the voltage analog signal.

[0046] In order to make it easier for those skilled in the art to understand the inventive concept of the present scheme, the following will provide examples of analog-to-digital conversion devices including two analog-to-digital conversion modules and three analog-to-digital conversion modules, so that those skilled in the art can undoubtedly infer the design structure of the analog-to-digital conversion device including n analog-to-digital conversion modules based on this structure, where n is greater than or equal to 4.

[0047] like Figure 1 As shown, Figure 1 It is a structural schematic diagram of an analog-to-digital conversion device including two analog-to-digital conversion modules shown in an embodiment of this specification. The analog-to-digital conversion device 1 includes a pulse output module 10, an adjustable delay circuit 11, a comparison module 14A and a digital logic processing module 13, and an analog-to-digital conversion module 12A and an analog-to-digital conversion module 12B arranged in sequence. The least significant bit value LSB of the analog-to-digital conversion module 12B is less than the LSB of the previous analog-to-digital conversion module 12A. The first output end of the pulse output module 10 outputs the pulse signal 01 to the first input end of the analog-to-digital conversion module 12A. The second output end of the pulse output module 10 outputs the pulse signal 01 to the first input end of the analog-to-digital conversion module 12B. The third output end of the pulse output module 10 is connected to the input end of the adjustable delay circuit 11, and an adjustment signal can be sent to the adjustable delay circuit 11 to adjust the delay interval parameter of the adjustable delay circuit 11. Of course, the adjustable delay circuit 11 itself can be configured with a code for adjusting the delay interval parameter, which is used to adjust the delay interval parameter regularly with the change of the calibration cycle. The first output end of the adjustable delay circuit 11 outputs the enable signal 02 to the second input end of the analog-to-digital conversion module 12A, and at the same time, the second output end outputs the enable signal 02 to the second input end of the analog-to-digital conversion module 12B. The third input end of the analog-to-digital conversion module 12A receives the external input voltage analog signal 03 that needs to be converted into a digital signal; the first output end outputs the conversion number 05 corresponding to the voltage analog signal 03 or the synchronization number 06 corresponding to the pulse signal 01 to the first input end of the digital logic processing module 13; the second output end outputs the voltage conversion signal 04 corresponding to the generated conversion number 05 to the first input end of the comparison module 14A. The second input end of the comparison module 14A receives the voltage analog signal 03; the first output end outputs the difference between the voltage analog signal 03 and the voltage conversion signal 04 as a new voltage analog signal 07 to the third input end of the analog-to-digital conversion module 12B. The output end of the analog-to-digital conversion module 12B outputs the conversion number 09 corresponding to the voltage analog signal 07 or the synchronization number 08 corresponding to the pulse signal 01 to the second input end of the digital logic processing module 13. The LSB mentioned in this specification stands for Least Significant Bit, which is the least significant bit and is the bit representing the lowest value in binary.

[0048] It is understandable that although Figure 1The working process of the analog-to-digital conversion device 1 includes two working logic parts: calculating the calibration coefficient of the analog-to-digital conversion module 12A to be calibrated and converting the voltage analog signal 03 into a digital representation. In fact, the above two working logic parts can be performed independently of each other, and the workflow of calculating the calibration coefficient does not depend on the workflow of the analog-to-digital conversion. Therefore, the calibration coefficient of the analog-to-digital conversion module 12A to be calibrated can be calculated first, and then stored in the digital logic processing module 13. When executing the workflow of converting the voltage analog signal 03 into a digital representation, the stored calibration coefficient can be directly obtained without the need to synchronously execute the workflow of calculating the calibration coefficient of the analog-to-digital conversion module 12A to be calibrated.

[0049] In order to facilitate the understanding of this solution, this manual will introduce the processing logic of these two parts separately:

[0050] like Figure 2 As shown, assuming that the calibration coefficient of the analog-to-digital conversion module 12A to be calibrated has been calculated in advance and stored in the digital logic processing module 13, the working process of the analog-to-digital conversion device 1 converting the sampled voltage analog signal 03 into a digital representation can be as follows:

[0051] The analog-to-digital conversion module 12A receives the voltage analog signal 03 to be converted into a digital representation, and outputs the conversion number 05 corresponding to the voltage analog signal 03 to the digital logic processing module 13, and outputs the voltage conversion signal 04 corresponding to the conversion number 05 to the comparison module 14A. It can be understood that the voltage analog signal 03 is a discrete voltage signal obtained by sampling, and the discrete voltage signal can be converted into a corresponding digital signal for representation by the analog-to-digital conversion module 12A. Of course, a follower can be set on the analog-to-digital conversion device 1 to receive the original voltage analog signal, and the original voltage analog signal is processed by the follower to obtain the voltage analog signal 03. This specification does not limit the method of obtaining the voltage analog signal 03.

[0052] The meaning of the conversion number output by any analog-to-digital conversion module involved in this specification can be the digital representation obtained by the analog-to-digital conversion module converting the input voltage signal. The meaning of the voltage conversion signal can be the voltage analog signal generated by the analog-to-digital conversion module to represent the voltage represented by the conversion number. For example, the meaning of the conversion number 05 in this solution can be the digital representation output by the analog-to-digital conversion module 12A for the voltage analog signal 03. The voltage conversion signal 04 can be a voltage analog signal of the voltage represented by the conversion number 05 generated by the analog-to-digital conversion module 12A.

[0053] Exemplarily, taking the analog-to-digital conversion module as a successive approximation register analog-to-digital converter as an example, the successive approximation register analog-to-digital converter (or successive approximation type ADC) internally includes an analog-to-digital converter DAC and a SAR register. The DAC generates a corresponding voltage conversion signal according to the conversion number of the SAR register, and compares it with the voltage analog signal. According to the comparison result, the conversion number in the SAR register is continuously adjusted to obtain the conversion number corresponding to the voltage analog signal. For example, the value of the voltage analog signal is 2.1V, the current conversion number in the SAR register is 001, and the voltage conversion signal output by the current corresponding DAC is 1V. Since 1V is less than 2V, the conversion number of the SAR register is increased to 010, and the voltage conversion signal output by the DAC is increased to 2V. Since 2V is less than 2.1V, the bit value of the current conversion number of the SAR register is further adjusted to 011, and the voltage conversion signal output by the DAC is further increased to 3V. Since 3V is greater than 2.1V, the conversion number output by the SAR register can be 010, and the value of the voltage conversion signal corresponding to the conversion number output by the DAC is 2V.

[0054] The comparison module 14A receives the voltage analog signal 03 and the voltage conversion signal 04 output by the analog-to-digital conversion module 12A, and outputs the difference between the voltage analog signal 03 and the voltage conversion signal 04 as a new voltage analog signal 07 to the analog-to-digital conversion module 12B. It can be understood that the difference between the voltage analog signal 03 and the voltage conversion signal 04 is always within the LSB range of an error unit of the analog-to-digital conversion module 12A. By performing a difference operation, the voltage analog signal 07 within the error range that the analog-to-digital conversion module 12A cannot accurately process can be continuously output to the analog-to-digital conversion module 12B with a higher conversion accuracy for further processing. Similarly, the analog-to-digital conversion module 12B can continue to output the new voltage analog signal within the error range that it cannot accurately process to the next analog-to-digital conversion module for further processing. By analogy, the next analog-to-digital conversion module can also continue to output the new voltage analog signal within the error range that it cannot accurately process to the next analog-to-digital conversion module for further processing. By combining multiple analog-to-digital conversion modules, it is possible to achieve hierarchical conversion of the same voltage analog signal into a digital representation.

[0055] The LSB of the analog-to-digital conversion module 12B can be smaller than the LSB of the analog-to-digital conversion module 12A, so that the analog-to-digital conversion module 12B can more accurately process the voltage analog signal 07 that the analog-to-digital conversion module 12A cannot accurately convert. The analog-to-digital conversion module 12B outputs the conversion number 09 corresponding to the voltage analog signal 07 to the digital logic processing module 13.

[0056] The digital logic processing module 13 can determine the digital representation corresponding to the voltage analog signal 03 based on the received conversion number 05 and conversion number 09, that is, conversion number 05*calibration coefficient+conversion number 09. The specific calculation method of the calibration coefficient is not introduced in this embodiment, and please refer to the embodiment specifically introducing the calibration coefficient.

[0057] For example, it is assumed that the voltage of the voltage analog signal 03 is 9.77V. The calibration coefficient of the analog-to-digital conversion module 12A stored in the digital logic processing module 13 is 1.11. The voltage range that the analog-to-digital conversion module 12A can process is [0, 10V], and the LSB is 1V. The voltage range that the analog-to-digital conversion module 12B can process is [0, 2V], and the LSB is 0.01V. The conversion number 05 output by the analog-to-digital conversion module 12A can be a digital representation of a size of 9V, and the voltage conversion signal 04 corresponding to the generated conversion number 05 is output to the comparison module 14A. The comparison module 14A can output the difference 0.77V between the voltage analog signal 03 of 9.77V and the voltage conversion signal 04 of the simulated 9V size as a new voltage analog signal 07 to the analog-to-digital conversion module 12B. The conversion number 09 output by the analog-to-digital conversion module 12B can be a digital representation of a size of 0.77V. Finally, the digital logic processing module 13 determines that the size of the digital representation corresponding to the voltage analog signal 03 is 9V*1.11+0.77V.

[0058] In the above-mentioned example, the analog-to-digital conversion module 12A may be affected by factors such as external extreme temperature or component aging, which may cause the size of the voltage conversion signal 04 generated by the analog-to-digital conversion module 12A to be different from the size represented by the corresponding conversion number 05. For example, the conversion number 05 represents a voltage of 9V, and the voltage conversion signal 04 actually generated based on the conversion number 05 drifts, which may be 8.9V, 9.2V, etc., which is not the same as the 9V voltage represented by the conversion number 05. Therefore, the error size of the conversion number 05 determined after comparing the voltage conversion signal 04 with the voltage analog signal 03 is within the LSB range of the analog-to-digital conversion module 12A, that is, within the 1V range. Therefore, if the conversion number 05 is not calibrated, even if the error range of the conversion number of the analog-to-digital conversion module 12B is within the 0.01V range, the digital representation after the combination of the two still cannot reach the accuracy of 0.01V, causing the error range of the digital representation corresponding to the voltage analog signal 03 determined by the digital logic processing module 13 after combining the conversion numbers output by the two is still within the 1V range. The present solution further calibrates the conversion number 05 of the analog-to-digital conversion module 12A with an error range of 1V through the analog-to-digital conversion module 12B with an error range of 0.01V, so that its error range is adjusted to 0.01V, and finally the total error range of the digital representation corresponding to the voltage analog signal 03 is within 0.01V.

[0059] Assume that you want to design a single analog-to-digital converter with an LSB of 0.01V and a voltage range of [0, 11V], and the required resolution must reach 1100 levels. The LSB of the analog-to-digital conversion module 12A of the analog-to-digital conversion device 1 in this example is 1V, and the voltage range is [0, 10V], so its resolution is 10 levels. The LSB of the analog-to-digital conversion module 12B is 0.01, and the voltage range is [0, 2V], so its resolution is 200 levels. It can be understood that the analog-to-digital conversion device 1 uses a total of two low-resolution analog-to-digital conversion modules with a total resolution of 210 levels to achieve the digital representation effect of a single high-resolution analog-to-digital converter with a resolution of 1100 levels, and the accuracy of the digital representation after calibration also reaches the accuracy level of the single analog-to-digital converter.

[0060] Next, how to determine the calibration coefficient of the analog-to-digital conversion module 10A is described:

[0061] like Figure 4 As shown, in the calibration phase, the pulse output module 10 can output the pulse signal 01 to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B; and in the analog-to-digital conversion phase, the pulse output module 10 can stop outputting the pulse signal 01. The adjustable delay circuit 11 outputs the enable signal 02 to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B based on the delay interval parameter, so that both receive the pulse signal 01 at the same time, and then the analog-to-digital conversion module 12A outputs the synchronous number 06 obtained by converting the received pulse signal 01 to the digital logic processing module 13, and the analog-to-digital conversion module 12B outputs the synchronous number 08 obtained by converting the received pulse signal 01 to the digital logic processing module 13.

[0062] like Figure 3As shown, the level characteristic of the pulse signal is that it gradually rises / falls, and the slope of the rise / fall of each pulse cycle remains basically unchanged. Therefore, when the pulse output module 10 outputs the pulse signal 01 at the beginning time T1 of each calibration cycle (composed of one or more pulse cycles), since the adjustable delay circuit 11 has a delay interval parameter, by gradually increasing the delay interval parameters (T2-T1), (T3-T1) and (T4-T1), the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B can be controlled to simultaneously receive the pulse signal 01 at different times such as T2, T3 or T4..., and convert the pulse signal 01 into the synchronous number 06 and the synchronous number 08 respectively and output them to the digital logic processing module 13. Since the LSB of the analog-to-digital conversion module 12A is large and the delay interval represented by the delay interval parameter is small, the synchronous number output by the analog-to-digital conversion module 12A may be 0 at the time T2 or T3, and the synchronous number output at the time T4 is greater than 0 for the first time. For example, assume that the LSB of the analog-to-digital conversion module 12A is 1V, and the LSB of the analog-to-digital conversion module 12B is 0.01V. At T2 and T3, the levels of the pulse signal are 0.6V and 0.9V respectively, and the synchronization number converted by the analog-to-digital conversion module 12A is 0. At T4, the level of the pulse signal is 1.1V, which is greater than 1LSB of the analog-to-digital conversion module 12A. At this time, the synchronization number converted by the analog-to-digital conversion module 12A is 1V, and the synchronization number output by the analog-to-digital conversion module 12B is 1.1V. Since both are converting pulse signals at the same time, the output accuracy of the analog-to-digital conversion module 12A can be calibrated by the synchronization number representing the size of 1.1V output by the analog-to-digital conversion module 12B and the synchronization number representing the size of 1V output by the analog-to-digital conversion module 12A. Specifically, by adjusting the delay interval parameters of the adjustable delay circuit 11 in each calibration cycle, the adjustable delay circuit 11 enables the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B to receive the pulse signal 01 at times such as T2, T3 or T4, and outputs the synchronous digital corresponding to the pulse signal 01 to the digital logic processing module 13. The digital logic processing module 13 receives the first synchronous digital output by the analog-to-digital conversion module 12A for the first time in any calibration cycle and the second synchronous digital output by the analog-to-digital conversion module 12B for the first time in any calibration cycle, and determines the calibration coefficient of the analog-to-digital conversion module 12A based on the first synchronous digital and the corresponding second synchronous digital for the first first synchronous digital greater than zero.

[0063] In this embodiment, by utilizing the smooth change trend and periodic change characteristics of the pulse signal, the reference module and the module to be calibrated can be controlled to convert the same pulse signal at the same time, so that the conversion number output by the reference module can be used to calibrate the conversion number output by the module to be calibrated to obtain the calibration coefficient.

[0064] Among them, the analog-to-digital conversion device 1 can be assembled to a neurostimulator, and the type of the pulse signal can specifically be an electrical stimulation signal generated by the neurostimulator. Of course, if the analog-to-digital conversion device 1 is assembled to an electronic device capable of outputting other types of pulse signals, the pulse signal may not be limited to the electrical stimulation signal, and this specification does not limit the specific type of the pulse signal. The pulse output module 10 can generate a pulse signal, and can also receive a pulse signal input by other pulse signal generation modules, and output it to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B for calibration of the accuracy of the analog-to-digital conversion module 12A.

[0065] In an illustrated embodiment, optionally, the system may perform the following operations at predetermined intervals: Figure 3 The calibration coefficient of the analog-to-digital conversion module 12A is re-determined in the manner shown, and the calibration coefficient is updated and stored in the digital logic processing module 13. Optionally, the calibration coefficient of the analog-to-digital conversion module 12A can be determined each time the analog-to-digital conversion device 1 is started, and it is updated and stored in the digital logic processing module 13. This specification does not limit the timing of determining the calibration coefficient of the analog-to-digital conversion module 12A.

[0066] Next, we will continue to introduce the structure of an analog-to-digital conversion device that includes three or more analog-to-digital conversion modules:

[0067] like Figure 5 As shown, Figure 5 It is a structural schematic diagram of an analog-to-digital conversion device including three analog-to-digital conversion modules shown in an embodiment of this specification. The analog-to-digital conversion device 2 includes a pulse output module 10, an adjustable delay circuit 11, an analog-to-digital conversion module 12A, an analog-to-digital conversion module 12B, an analog-to-digital conversion module 12C, a digital logic processing module 13, a comparison module 14A and a comparison module 14B. Each analog-to-digital conversion module is arranged in sequence and the least significant bit value LSB of the subsequent analog-to-digital conversion module is less than the LSB of the previous analog-to-digital conversion module.

[0068] Specifically, the first output end of the pulse output module 10 outputs the pulse signal 01 to the first input end of the analog-to-digital conversion module 12A, the second output end outputs the pulse signal 01 to the first input end of the analog-to-digital conversion module 12B, the third output end outputs the pulse signal 01 to the first input end of the analog-to-digital conversion module 12C, and the fourth output end outputs the adjustment signal to the first input end of the adjustable delay circuit 11 to adjust the delay interval parameter of the adjustable delay circuit 11. The first output end of the adjustable delay circuit 11 outputs the enable signal 02 to the second input end of the analog-to-digital conversion module 12A, the second output end of the adjustable delay circuit 11 outputs the enable signal 02 to the second input end of the analog-to-digital conversion module 12B, and the third output end of the adjustable delay circuit 11 outputs the enable signal 03 to the second input end of the analog-to-digital conversion module 12C. The third input terminal of the analog-to-digital conversion module 12A receives the voltage analog signal 03A to be converted into digital representation, the first output terminal outputs the conversion number 05A corresponding to the voltage analog signal 03A or the synchronization number 06A corresponding to the pulse signal 01 to the digital logic processing module 13, and the second output terminal outputs the voltage conversion signal 04A corresponding to the conversion number 05A to the comparison module 14A. The second input terminal of the comparison module 14A receives the voltage analog signal 03A, the first output terminal outputs the difference between the voltage conversion signal 04A and the voltage analog signal 03A as a new voltage analog signal 03B to the third input terminal of the analog-to-digital conversion module 12B, and the second output terminal outputs the voltage analog signal 03B to the first input terminal of the comparison module 14B. The first output terminal of the analog-to-digital conversion module 12B outputs the conversion number 05B corresponding to the voltage analog signal 03B or the synchronization number 06B corresponding to the pulse signal 01 to the second input terminal of the digital logic processing module 13, and the second output terminal outputs the voltage conversion signal 04B corresponding to the conversion number 05B to the second input terminal of the comparison module 14B. The first output terminal of the comparison module 14B outputs the difference between the voltage conversion signal 04B and the voltage analog signal 03B as a new voltage analog signal 03C to the third input terminal of the analog-to-digital conversion module 12C. The first output terminal of the analog-to-digital conversion module 12C outputs the conversion number 05C corresponding to the voltage analog signal 03C or the synchronization number 06C corresponding to the pulse signal 01 to the digital logic processing module 13.

[0069] Similar to the introduction process of the analog-to-digital conversion device 1 described above, this specification will separately introduce the analog-to-digital conversion process and the calibration process of the analog-to-digital conversion device 2:

[0070] Since the analog-to-digital conversion modules are arranged in sequence and the LSB of the analog-to-digital conversion module of the next stage is smaller than the LSB of the analog-to-digital conversion module of the previous stage, the analog-to-digital conversion module of the next stage can be used to calibrate the conversion numbers output by all the analog-to-digital conversion modules in front of it. For example, the analog-to-digital conversion module 12C can be used to calibrate the conversion number 05B output by the analog-to-digital conversion module 12B, and the analog-to-digital conversion module 12B and / or the analog-to-digital conversion module 12C can be used to calibrate the conversion number 05A output by the analog-to-digital conversion module 12A.

[0071] like Figure 6 As shown, assuming that the calibration coefficients of the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B to be calibrated have been calculated in advance and stored in the digital logic processing module 13, the working process of the analog-to-digital conversion device 2 converting the sampled voltage analog signal 03 into a digital representation can be as follows:

[0072] The analog-to-digital conversion module 12A receives the sampled voltage analog signal 03A and outputs the corresponding conversion number 05A to the digital logic processing module 13, and outputs the voltage conversion signal 04A corresponding to the conversion number 05A to the comparison module 14A. The comparison module 14A receives the sampled voltage analog signal 03A and the voltage conversion signal 04A, and outputs the difference between the voltage analog signal 03A and the voltage conversion signal 04A as a new voltage analog signal 03B to the analog-to-digital conversion module 12B and the comparison module 14B. The analog-to-digital conversion module 12B outputs the conversion number 05B corresponding to the voltage analog signal 03B to the digital logic processing module 13, and outputs the voltage conversion signal 04B corresponding to the conversion number 05B to the comparison module 14B. The comparison module 14B outputs the difference between the voltage analog signal 03B and the voltage conversion signal 04B as a new voltage analog signal 03C to the analog-to-digital conversion module 12C. The analog-to-digital conversion module 12C outputs the conversion number 05C corresponding to the voltage analog signal 03C to the digital logic processing module 13.

[0073] The digital logic processing module 13 obtains the stored calibration coefficient corresponding to the analog-to-digital conversion module 12A, calibrates the conversion number 05A to obtain the calibrated conversion number 05A, obtains the calibration coefficient corresponding to the analog-to-digital conversion module 12B, calibrates the conversion number 05B to obtain the calibrated conversion number 05B, and then uses the sum of the calibrated conversion number 05A, the calibrated conversion number 05B and the conversion number 05C as the digital representation corresponding to the voltage analog signal 03A received by the analog-to-digital conversion device 2.

[0074] For example, assuming that the voltage magnitude of the voltage analog signal 03A is 9.77V, the calibration coefficient of the analog-to-digital conversion module 12A stored in the digital logic processing module 13 is 1.1, and the calibration coefficient of the analog-to-digital conversion module 12B is 1.2. The voltage range that the analog-to-digital conversion module 12A can process is [0, 10V], and the LSB is 1V. The voltage range that the analog-to-digital conversion module 12B can process is [0, 2V], and the LSB is 0.1V. The voltage range that the analog-to-digital conversion module 12C can process is [0, 0.2V], and the LSB is 0.01V. The conversion number 05A output by the analog-to-digital conversion module 12A is a digital representation representing a magnitude of 9V, and the voltage conversion signal 04A represents an analog voltage signal of a magnitude of 9V. The comparison module 14A outputs the difference 0.77V between the received voltage analog signal 03A of 9.77V and the voltage conversion signal 04A of 9V as a new voltage analog signal 03B to the analog-to-digital conversion module 12B and the comparison module 14B respectively. The analog-to-digital conversion module 12B outputs the conversion number 05B corresponding to the voltage analog signal 03B of 0.77V to the digital logic processing module 13, and outputs the voltage conversion signal 04B representing the magnitude of 0.7V to the comparison module 14B. The comparison module 14B outputs the difference 0.07V between the received voltage analog signal 03B of 0.77V and the conversion voltage signal 04B of 0.7V as a new voltage analog signal 03C to the analog-to-digital conversion module 12C. The analog-to-digital conversion module 12C outputs the generated conversion number 05C corresponding to the voltage analog signal 03C to the digital logic processing module 13. The digital logic processing module 13 can finally determine that the digital representation corresponding to the voltage analog signal 03A is 9V*1.1+0.7V*1.2+0.07V.

[0075] Assuming that you want to design a single analog-to-digital converter with an LSB of 0.01V and a voltage range of [0, 11V], the required resolution must reach 1100 levels. The resolutions of the analog-to-digital conversion module 10A, the analog-to-digital conversion module 10B, and the analog-to-digital conversion module 10C of the analog-to-digital conversion device 2 in this example are 10 levels, 20 levels, and 20 levels, respectively. It can be understood that the analog-to-digital conversion device 2 uses a total of three low-resolution analog-to-digital conversion modules with a total resolution of 50 levels to achieve the digital representation effect of a single high-resolution analog-to-digital converter with a resolution of 1100 levels, and the accuracy after calibration reaches the accuracy level of the single high-resolution analog-to-digital converter.

[0076] It should be noted that, as for the design structures of the aforementioned analog-to-digital conversion device 1 and the analog-to-digital conversion device 2, both meet the accuracy requirement of 0.01V, the number of analog-to-digital conversion modules of the analog-to-digital conversion device 2 is more than that of the analog-to-digital conversion device 1, but the total resolution of the analog-to-digital conversion device 2 is lower than the total resolution of the analog-to-digital conversion device 1. Therefore, those skilled in the art can determine the number and resolution requirements of the analog-to-digital conversion modules in the analog-to-digital conversion device according to actual application requirements, and this specification does not impose any restrictions on this.

[0077] Next, how to determine the calibration coefficients of the analog-to-digital conversion module 10A and the analog-to-digital conversion module 10B is described:

[0078] In one illustrated embodiment, Figure 7 As shown, the analog-to-digital conversion device is equipped with an adjustable delay circuit. The analog-to-digital conversion module 12A, the analog-to-digital conversion module 12B and the analog-to-digital conversion module 12C are arranged in sequence. When any analog-to-digital conversion module calibrates its previous analog-to-digital conversion module, any analog-to-digital conversion module serves as a reference module and its previous analog-to-digital conversion module serves as a module to be calibrated. For example, when the analog-to-digital conversion module 12B is used to calibrate the analog-to-digital conversion module 12A, the analog-to-digital conversion module 12B serves as a reference module and the analog-to-digital conversion module 12A serves as a module to be calibrated; and when the analog-to-digital conversion module 12C is used to calibrate the analog-to-digital conversion module 12B, the analog-to-digital conversion module 12B serves as a module to be calibrated and the analog-to-digital conversion module 12C serves as a reference module.

[0079] If the device, such as the analog-to-digital conversion device 2, contains no less than two modules to be calibrated, then an adjustable delay circuit can be used for calibration of a pair of modules to be calibrated and a reference module at a time during the calibration phase, so as to calibrate each module to be calibrated independently. For example, in the calibration phase of the analog-to-digital conversion module 12A, the pulse output module 10 outputs the pulse signal 01 to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B, and the adjustable delay circuit 11 adjusts its delay interval parameter in each calibration cycle, and sends an enable signal to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B connected thereto, so that the two receive the pulse signal at the same time, and the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B respectively output the synchronous digital 06A and the synchronous digital 06B corresponding to the pulse signal 01 to the digital logic processing module 13.

[0080] The digital logic processing module 13 will receive the synchronization numbers output by the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B in multiple calibration cycles. For the first synchronization number output by the analog-to-digital conversion module 12A (i.e., the module to be calibrated) for the first time in any calibration cycle and the second synchronization number output by the analog-to-digital conversion module 12B (i.e., the reference module) for the first time in any calibration cycle, the calibration coefficient of the analog-to-digital conversion module 12A is determined based on the first synchronization number and the second synchronization number of the same calibration cycle for the first synchronization number greater than zero. For example, the calibration cycle can be composed of one or more pulse cycles. At the pulse output start time of the first calibration cycle, the pulse output module 10 simultaneously outputs a pulse signal to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B, and adjusts the delay interval parameter of the adjustable delay circuit to △T1, so that the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B receive the pulse signal after △T1 at the pulse output start time and convert it into a synchronous digital; at the pulse output start time of the second calibration cycle, the pulse output module 10 simultaneously outputs a pulse signal to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B, and adjusts the delay interval parameter of the adjustable delay circuit to △T2, so that the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B receive the pulse signal after △T2 at the pulse output start time and convert it into a synchronous digital. By analogy, the delay interval parameter is continuously increased until the first synchronous digital output by the analog-to-digital conversion module 12A received by the digital logic processing module 13 in a certain calibration cycle is greater than 0. After calibrating the analog-to-digital conversion module 12A, the analog-to-digital conversion module 12B may be calibrated based on the analog-to-digital conversion module 12C. The basic principle is the same as that of calibrating the analog-to-digital conversion module 12A, and will not be repeated here.

[0081] In another illustrated embodiment, the number of adjustable delay circuits installed in the analog-to-digital conversion device can be the same as the number of modules to be calibrated. If the analog-to-digital conversion device contains n analog-to-digital conversion modules, the first analog-to-digital conversion module, the second analog-to-digital conversion module, ..., the n-2th analog-to-digital conversion module, the n-1th analog-to-digital conversion module and the nth analog-to-digital conversion module are arranged in sequence, the nth analog-to-digital conversion module is used to calibrate the n-1th analog-to-digital conversion module, the n-1th analog-to-digital conversion module is used to calibrate the n-2th analog-to-digital conversion module, ..., the second analog-to-digital conversion module is used to calibrate the first analog-to-digital conversion module, then the number of modules to be calibrated is n-1, and n-1 adjustable delay circuits can be set. For example, Figure 8As shown, for the analog-to-digital conversion device 2, since the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B need to be calibrated, the adjustable delay circuit 11A and the adjustable delay circuit 11B can be set to be connected to the pulse output module 10, the adjustable delay circuit 11A is connected to the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B, and the adjustable delay circuit 11B is connected to the analog-to-digital conversion module 12B and the analog-to-digital conversion module 12C, so as to determine the calibration coefficients of the analog-to-digital conversion module 12A and the analog-to-digital conversion module 12B in parallel. For example, the adjustable delay circuit 11A and the adjustable delay circuit 11B independently adjust their respective delay interval parameters in each calibration cycle, and the delay interval parameters adjusted by the two are different in size.

[0082] In an illustrated embodiment, for the first synchronization number output for the first time by the module to be calibrated in any calibration cycle and the second synchronization number output for the first time by the reference module in any calibration cycle received by the digital logic processing module, as well as for the first first synchronization number greater than zero, the ratio of the second synchronization number belonging to the same calibration cycle as the first synchronization number to the first synchronization number can be determined as the calibration coefficient of the module to be calibrated.

[0083] In an illustrated embodiment, the product of the calibration coefficient and the conversion number output by the module to be calibrated may be determined as the calibrated conversion number corresponding to the module to be calibrated.

[0084] The above is only an exemplary introduction of an analog-to-digital conversion device 1 comprising two analog-to-digital conversion modules and an analog-to-digital conversion device 2 comprising three analog-to-digital conversion modules. It can be understood that a person skilled in the art can undoubtedly infer an analog-to-digital conversion device comprising n analog-to-digital conversion modules on this basis, where n is greater than or equal to 4.

[0085] In an illustrated embodiment, since other analog-to-digital conversion modules except the last analog-to-digital conversion module need to output voltage conversion signals, all analog-to-digital conversion modules or modules except the last analog-to-digital conversion module can be analog-to-digital converters with the function of outputting voltage conversion signals. For example, the DAC of a successive approximation register analog-to-digital converter has the function of outputting voltage conversion signals. Therefore, the type of the analog-to-digital conversion module can be selected as a successive approximation register analog-to-digital converter.

[0086] In an embodiment shown, the comparison module in this solution is mainly used to perform a subtraction function, that is, to perform a subtraction operation on two received voltage signals, so a subtractor can be selected as the comparison module. Of course, a comparator other than a comparator with a subtraction function can also be selected as the comparison module, and this specification does not impose any restrictions on this.

[0087] In an illustrated embodiment, the maximum value of the reference voltage of each analog-to-digital conversion module except the first analog-to-digital conversion module is not less than twice the least significant bit value of the previous analog-to-digital conversion module, so as to ensure that the subsequent analog-to-digital conversion module can calibrate the error of the previous comparison module. Since the voltage range that the subsequent analog-to-digital conversion module can handle depends on the least significant bit value of the previous analog-to-digital conversion module, preferably, the maximum value of the reference voltage of each analog-to-digital conversion module except the first analog-to-digital conversion module can be set equal to twice the least significant bit value of the previous analog-to-digital conversion module.

[0088] like Fig. 9 As shown, Fig. 9 is a flow chart of a digital signal calibration method according to an exemplary embodiment of the present specification. The calibration method can be applied to Figure 1 or Figure 2 The digital logic processing module 13 comprises the following steps 901-903:

[0089] Step 901: Acquire a first synchronization number outputted for the first time by the module to be calibrated in any calibration cycle and a second synchronization number outputted for the first time by the reference module in any calibration cycle.

[0090] Step 902: For a first synchronization number greater than zero, determine a calibration coefficient of the module to be calibrated based on the first synchronization number and a corresponding second synchronization number.

[0091] Step 903: Calibrate the conversion digital output by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

[0092] In this embodiment, by calibrating the conversion numbers output by the low-precision analog-to-digital conversion module based on the high-precision analog-to-digital conversion module, the error in the conversion numbers indirectly caused by the offset error of the voltage conversion signal generated by the low-precision analog-to-digital conversion module can be eliminated, thereby improving the accuracy of the conversion numbers output by the low-precision analog-to-digital conversion module, thereby improving the overall accuracy of the digital representation determined based on the conversion numbers output by each analog-to-digital conversion module.

[0093] Corresponding to the embodiments of the aforementioned method, this specification also provides embodiments of a device and a terminal to which it is applied.

[0094] like Fig.10 As shown, Fig.10It is a structural diagram of an electronic device 1000 shown in this specification according to an exemplary embodiment. At the hardware level, the device includes a processor 1002, an internal bus 1004, a network interface 1006, a memory 1008 and a non-volatile memory 1010, and of course may also include hardware required for other services. One or more embodiments of this specification can be implemented based on software, such as the processor 1002 reading the corresponding computer program from the non-volatile memory 1010 into the memory 1008 and then running it. Of course, in addition to the software implementation, one or more embodiments of this specification do not exclude other implementations, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic module, but can also be hardware or logic devices.

[0095] like Fig.11 As shown, Fig.11 This specification is a digital signal calibration device according to an exemplary embodiment, which can be applied to Fig.10 In the electronic device 1000 shown in the figure, the technical solution of this specification is implemented. The device includes:

[0096] The acquisition module 1102 is used to acquire the first synchronization number outputted for the first time by the module to be calibrated in any calibration period and the second synchronization number outputted for the first time by the reference module in any calibration period.

[0097] The calibration coefficient determination module 1104 is used to determine the calibration coefficient of the module to be calibrated based on the first synchronization number and the corresponding second synchronization number for the first synchronization number greater than zero.

[0098] The digital representation calibration module 1106 is used to calibrate the conversion digital output by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

[0099] The implementation process of the functions and effects of each module in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, which will not be repeated here.

[0100] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only schematic, wherein the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place, or they may be distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. Ordinary technicians in this field can understand and implement it without paying creative work.

[0101] The present specification also provides a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the steps of the aforementioned digital signal calibration method provided in the present application are implemented.

[0102] Specifically, computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including, for example, semiconductor memory devices (such as EPROM, EEPROM and flash memory devices), magnetic disks (such as internal hard disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks.

Claims

1. An analog-to-digital conversion device, characterized in that: The device comprises a pulse output module, at least one adjustable delay circuit, at least two analog-to-digital conversion modules and at least one comparison module. The analog-to-digital conversion modules are arranged in sequence and the least significant bit value LSB of the subsequent analog-to-digital conversion module is less than the LSB of the previous analog-to-digital conversion module. When any analog-to-digital conversion module calibrates the previous analog-to-digital conversion module, the analog-to-digital conversion module is used as a reference module and the previous analog-to-digital conversion module is used as a module to be calibrated, wherein: The pulse output module outputs the pulse signal to each analog-to-digital conversion module connected thereto; Any adjustable delay circuit adjusts its delay interval parameter in each calibration cycle, and simultaneously sends an enable signal to the module to be calibrated and the reference module connected thereto, so that the two modules receive the pulse signal simultaneously; Any analog-to-digital conversion module receives the voltage analog signal and the pulse signal, and outputs the conversion digital corresponding to the voltage analog signal and the synchronization digital corresponding to the pulse signal to the digital logic processing module connected thereto, and outputs the voltage conversion signal corresponding to the conversion digital to the comparison module connected thereto; Any comparison module receives the voltage analog signal and the voltage conversion signal output by the analog-to-digital conversion module connected thereto, and outputs the difference between the voltage analog signal and the voltage conversion signal as a new voltage analog signal to the comparison module and the analog-to-digital conversion module connected thereto; The digital logic processing module receives the first synchronization number outputted by the module to be calibrated for the first time in any calibration cycle and the second synchronization number outputted by the reference module for the first time in any calibration cycle; and, for the first first synchronization number greater than zero, determines the calibration coefficient of the module to be calibrated based on the first synchronization number and the corresponding second synchronization number, and performs calibration processing on the conversion number outputted by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion number corresponding to the module to be calibrated; After determining the calibrated conversion numbers corresponding to the modules to be calibrated, the digital logic processing module uses the sum of the calibrated conversion numbers and the corresponding conversion numbers as the digital representation corresponding to the voltage analog signal.

2. The device according to claim 1, characterized in that The type of the comparison module is a subtractor.

3. The device according to claim 1, characterized in that The maximum value of the reference voltage of each analog-to-digital conversion module except the first analog-to-digital conversion module is not less than twice the LSB of the previous analog-to-digital conversion module.

4. The device according to claim 1, characterized in that The step of determining the calibration coefficient of the module to be calibrated based on the first synchronization number and the corresponding second synchronization number includes: The ratio of the second synchronization number to the first synchronization number is determined as a calibration coefficient of the module to be calibrated.

5. The device according to claim 4, characterized in that The step of calibrating the conversion number output by the module to be calibrated based on the calibration coefficient to obtain a calibrated conversion number corresponding to the module to be calibrated includes: The product of the calibration coefficient and the conversion number output by the module to be calibrated is determined as the calibrated conversion number corresponding to the module to be calibrated.

6. The device according to any one of claims 1 to 5, characterized in that The types of all analog-to-digital conversion modules or other analog-to-digital conversion modules except the last analog-to-digital conversion module are successive approximation register analog-to-digital converters.

7. A method for calibrating a digital signal, characterized in that: The method is applied to a digital logic processing module in an analog-to-digital conversion device according to any one of claims 1 to 6, and the method comprises: Acquire a first synchronization number outputted for the first time by the module to be calibrated in any calibration period and a second synchronization number outputted for the first time by the reference module in any calibration period; For a first synchronization number greater than zero, determining a calibration coefficient of the module to be calibrated based on the first synchronization number and a corresponding second synchronization number; Based on the calibration coefficient, the conversion digital output by the module to be calibrated is calibrated to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

8. A digital signal calibration device, characterized in that: The device is applied to a digital logic processing module in an analog-to-digital conversion device according to any one of claims 1 to 6, and the device comprises: An acquisition module, used for acquiring a first synchronization number outputted for the first time by the module to be calibrated in any calibration period and a second synchronization number outputted for the first time by the reference module in any calibration period; A calibration coefficient determination module, configured to determine, for a first synchronization number greater than zero, a calibration coefficient of the module to be calibrated based on the first synchronization number and a corresponding second synchronization number; The digital representation calibration module is used to calibrate the conversion digital output by the module to be calibrated based on the calibration coefficient to obtain the calibrated conversion digital corresponding to the module to be calibrated. After determining the calibrated conversion digital corresponding to each module to be calibrated, the sum of each calibrated conversion digital and the corresponding conversion digital is used as the digital representation corresponding to the voltage analog signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to claim 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to claim 7 are implemented.

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