An anti-interference circuit for an industrial control screen mainboard

Abstract

The invention discloses an anti-interference circuit for an industrial control screen mainboard, comprising a processor, an initial configuration module and a detection module. The processor inputs a high-level Input signal to the initial configuration module when a program is first run, and inputs a low-level Input signal after the program is run. The initial configuration module comprises a plurality of configuration units, which are connected in series, and the number of the configuration units is consistent with the number of programs. The configuration unit is used to convert the program running time into a Vsen signal, and start the corresponding configuration unit to start and stop when the program is switched, and automatically shield the regulation of the current configuration unit by the subsequent Input signal. The Vsen signal of the configuration unit is fed back to the detection module, and the processor calls the dog feeding signal port to the detection module when the program is run. The detection module performs detection according to different Vsen signals and Port signals, and feeds back a Vout reset signal when an abnormality occurs.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an anti-interference circuit for an industrial control screen mainboard. Background Art

[0002] Industrial control screens are designed for the field of industrial automation and control and can operate normally in harsh industrial environments. Industrial control screens are usually equipped with specific interfaces and communication protocols for connecting and interacting with various control devices and automation systems, such as PLCs (programmable logic controllers), sensors, actuators, etc. As the core of industrial control screens, the motherboard processor is susceptible to external signal crosstalk when operating in a complex environment, affecting the accuracy and stability of signal transmission. Although traditional inner layer routing can alleviate this problem, it is still difficult to completely shield the signal interaction between line layers, resulting in hidden dangers such as transmission errors and data loss, which in turn causes program abnormalities, such as runaway, dead loops and other unfavorable conditions.

[0003] To solve this problem, watchdog (anti-interference circuit) technology came into being and became an important anti-interference strategy. Its typical implementation relies on the combination of 555 oscillator and counter. Through clever logic control, it ensures that the processor automatically resets in abnormal situations to prevent the program from getting out of control. Specifically, when there is no dog feeding signal, the counter triggers the oscillator to start oscillating and sends a reset signal to the processor; after receiving the dog feeding instruction, the counter is reset to maintain the normal operation of the system. It is worth noting that the embedding of the dog feeding instruction needs to be carefully considered. When a program is longer than the watchdog reset cycle, it needs to be inserted at the appropriate position in the assembly code, or the reset cycle of the watchdog is adjusted to the maximum time of the program. Summary of the invention

[0004] In view of the above technical problems, the purpose of the present invention is to provide an anti-interference circuit for an industrial control screen mainboard, including a processor, an initial configuration module, and a detection module. The processor inputs a high-level Input signal to the initial configuration module when running the program for the first time, and inputs a low-level Input signal after the program is completed. The initial configuration module includes multiple configuration units, which are connected in series, and the number of which is consistent with the number of programs. The configuration unit is used to convert the program running time into a Vsen signal, and start the corresponding configuration unit to start and stop when the program is switched, and automatically shield the subsequent Input signal from regulating the current configuration unit. The Vsen signal of the configuration unit is fed back to the detection module, and the processor calls the dog feeding signal port to the detection module at the end of the program running. The detection module performs detection according to different Vsen signals and Port signals, and feeds back a Vout reset signal in case of abnormality.

[0005] Further, the configuration unit includes a first trigger U1, a second digital potentiometer U2, a third inverter U3, a fourth AND gate U4, a first resistor R1, and a first diode D1;

[0006] The first pin of the first trigger U1, the eighth pin of the second digital potentiometer U2, and one end of the first resistor R1 are connected to the power supply, the second pin of the first trigger U1, the sixth pin of the first trigger U1 are connected to the anode of the first diode D1, the third pin of the first trigger U1 is connected to the second pin of the second digital potentiometer U2, and the second pin of the third inverter U3 are connected, the fourth pin of the first trigger U1 is connected to the cathode of the first diode D1, the fifth pin of the first trigger U1, the seventh pin of the second digital potentiometer U2, and the second connection end of the fourth AND gate U4 are connected, the first pin of the second digital potentiometer U2 is connected to the CLK clock source, the third pin of the second digital potentiometer U2, the other end of the first resistor R1 are connected to the Vsen end, the first pin of the third inverter U3, the first connection end of the fourth AND gate U4 are connected to the Input end, the output end of the fourth AND gate U4 is connected to the Vput end, the fourth pin of the second digital potentiometer U2, the fifth pin of the second digital potentiometer U2, and the sixth pin of the second digital potentiometer U2 are connected to the ground end.

[0007] Further, the detection module includes a fifth trigger U5, a sixth trigger U6, a seventh trigger U7, an eighth inverter U8, a ninth operational amplifier U9, a tenth multiplexer U10, a first transistor Q1, a sixth resistor R6, an eighth resistor R8, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first capacitor C1, and a first connector P1;

[0008] The fourth pin of the fifth trigger U5, the fourth pin of the sixth trigger U6, the fourth pin of the seventh trigger U7, the sixteenth pin of the tenth multiplexer U10, and one end of the eleventh resistor R11 are connected to the power supply, the first pin of the fifth trigger U5, the first pin of the sixth trigger U6, the first pin of the seventh trigger U7 are connected to one end of the eighth resistor R8 and the second pin of the eighth inverter U8, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, the second pin of the sixth trigger U6 is connected to the sixth pin of the sixth trigger U6, the second pin of the seventh trigger U7 is connected to the sixth pin of the seventh trigger U7, the third pin of the fifth trigger U5, one end of the sixth resistor R6 is connected to the Port end, the fifth pin of the fifth trigger U5 is connected to the third pin of the sixth trigger U6, and the ninth pin of the tenth multiplexer U10, the fifth pin of the sixth trigger U6 is connected to the third pin of the seventh trigger U7, and the tenth pin of the tenth multiplexer U10, and the fifth pin of the seventh trigger U7 is connected to the eleventh pin of the tenth multiplexer U10 The first pin of the eighth inverter U8, one end of the fourteenth resistor R14 and the first pin of the first connector P1 are connected, the in-phase end of the ninth operational amplifier U9 and the other end of the eleventh resistor R11, one end of the twelfth resistor R12, the collector of the first transistor Q1, and one end of the first capacitor C1 are connected, the inverting end of the ninth operational amplifier U9 and one end of the thirteenth resistor R13 and the third pin of the tenth multiplexer U10 are connected, the output end of the ninth operational amplifier U9 and the Vout end are connected, and the fourth end of the tenth multiplexer U10 is connected. The pin is connected to the second pin of the first connector P1, the thirteenth pin of the tenth multiplexer U10 is connected to the Vsen end, the base of the first transistor Q1 is connected to the Port end, the sixth pin of the tenth multiplexer U10, the seventh pin of the tenth multiplexer U10, the eighth pin of the tenth multiplexer U10, the emitter of the first transistor Q1, the other end of the sixth resistor R6, the other end of the eighth resistor R8, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14 and the ground end are connected.

[0009] Furthermore, the configuration unit further includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5;

[0010] One end of the second resistor R2 is connected to the first pin of the third inverter U3, one end of the third resistor R3 is connected to the fourth pin of the first trigger U1, one end of the fourth resistor R4 is connected to the second connection end of the fourth AND gate U4, one end of the fifth resistor R5 is connected to the second pin of the second digital potentiometer U2, and the other end of the second resistor R2, the other end of the third resistor R3, the other end of the fourth resistor R4, and the other end of the fifth resistor R5 are connected to the ground.

[0011] Furthermore, the detection module further includes a seventh resistor R7, a ninth resistor R9, and a tenth resistor R10;

[0012] One end of the seventh resistor R7 is connected to the fifth pin of the sixth trigger U6, one end of the ninth resistor R9 is connected to the fifth pin of the fifth trigger U5, one end of the tenth resistor R10 is connected to the fifth pin of the seventh trigger U7, and the other ends of the seventh resistor R7, the ninth resistor R9, and the tenth resistor R10 are connected to the ground.

[0013] Furthermore, the first transistor Q1 is an N-type transistor.

[0014] Furthermore, the eleventh resistor R11 is an adjustable resistor or the first capacitor C1 is a variable capacitor, which is used to match the integration rate of the eleventh resistor R11 and the first capacitor C1 with the inverting terminal of the ninth operational amplifier U9.

[0015] The beneficial effects of the present invention compared with the prior art are:

[0016] The present invention replaces the traditional maximum time-consuming setting, responds faster when the program is abnormal, effectively avoids the extra occupation of the port through serial input, and ensures the reasonable allocation of system resources.

[0017] Compared with software and mixed detection methods, there is no need to reinsert cumbersome dog feeding instructions when changing programs. When changing or setting new programs, only simple initialization matching is required, that is, initialization is completed by uniformly calling the dog feeding instruction at the end of program operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 The present invention provides an overall structural diagram.

[0020] Figure 2 This is a schematic diagram of the configuration unit structure provided by the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of the detection module provided by the present invention. DETAILED DESCRIPTION

[0022] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0023] The invention discloses an anti-interference circuit for an industrial control screen mainboard, comprising a processor, an initial configuration module and a detection module. The processor inputs a high-level Input signal to the initial configuration module when a program is first run, and inputs a low-level Input signal after the program is run. The initial configuration module comprises a plurality of configuration units, which are connected in series, and the number of the configuration units is consistent with the number of programs. The configuration unit is used to convert the program running time into a Vsen signal, and start the corresponding configuration unit to start and stop when the program is switched, and automatically shield the regulation of the current configuration unit by the subsequent Input signal. The Vsen signal of the configuration unit is fed back to the detection module, and the processor calls the dog feeding signal port to the detection module when the program is run. The detection module performs detection according to different Vsen signals and Port signals, and feeds back a Vout reset signal when an abnormality occurs.

[0024] Specifically, the configuration unit includes a first trigger U1, a second digital potentiometer U2, a third inverter U3, a fourth AND gate U4, a first resistor R1, and a first diode D1;

[0025] The first pin of the first trigger U1, the eighth pin of the second digital potentiometer U2, and one end of the first resistor R1 are connected to the power supply, the second pin of the first trigger U1, the sixth pin of the first trigger U1 are connected to the anode of the first diode D1, the third pin of the first trigger U1 is connected to the second pin of the second digital potentiometer U2, and the second pin of the third inverter U3 are connected, the fourth pin of the first trigger U1 is connected to the cathode of the first diode D1, the fifth pin of the first trigger U1, the seventh pin of the second digital potentiometer U2, and the second connection end of the fourth AND gate U4 are connected, the first pin of the second digital potentiometer U2 is connected to the CLK clock source, the third pin of the second digital potentiometer U2, the other end of the first resistor R1 are connected to the Vsen end, the first pin of the third inverter U3, the first connection end of the fourth AND gate U4 are connected to the Input end, the output end of the fourth AND gate U4 is connected to the Vput end, the fourth pin of the second digital potentiometer U2, the fifth pin of the second digital potentiometer U2, and the sixth pin of the second digital potentiometer U2 are connected to the ground end.

[0026] Specifically, the detection module includes a fifth trigger U5, a sixth trigger U6, a seventh trigger U7, an eighth inverter U8, a ninth operational amplifier U9, a tenth multiplexer U10, a first transistor Q1, a sixth resistor R6, an eighth resistor R8, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first capacitor C1, and a first connector P1;

[0027] The fourth pin of the fifth trigger U5, the fourth pin of the sixth trigger U6, the fourth pin of the seventh trigger U7, the sixteenth pin of the tenth multiplexer U10, and one end of the eleventh resistor R11 are connected to the power supply, the first pin of the fifth trigger U5, the first pin of the sixth trigger U6, the first pin of the seventh trigger U7 are connected to one end of the eighth resistor R8 and the second pin of the eighth inverter U8, the second pin of the fifth trigger U5 is connected to the sixth pin of the fifth trigger U5, the second pin of the sixth trigger U6 is connected to the sixth pin of the sixth trigger U6, the second pin of the seventh trigger U7 is connected to the sixth pin of the seventh trigger U7, the third pin of the fifth trigger U5, one end of the sixth resistor R6 is connected to the Port end, the fifth pin of the fifth trigger U5 is connected to the third pin of the sixth trigger U6, and the ninth pin of the tenth multiplexer U10, the fifth pin of the sixth trigger U6 is connected to the third pin of the seventh trigger U7, and the tenth pin of the tenth multiplexer U10, and the fifth pin of the seventh trigger U7 is connected to the eleventh pin of the tenth multiplexer U10 The first pin of the eighth inverter U8, one end of the fourteenth resistor R14 and the first pin of the first connector P1 are connected, the in-phase end of the ninth operational amplifier U9 and the other end of the eleventh resistor R11, one end of the twelfth resistor R12, the collector of the first transistor Q1, and one end of the first capacitor C1 are connected, the inverting end of the ninth operational amplifier U9 and one end of the thirteenth resistor R13 and the third pin of the tenth multiplexer U10 are connected, the output end of the ninth operational amplifier U9 and the Vout end are connected, and the fourth end of the tenth multiplexer U10 is connected. The pin is connected to the second pin of the first connector P1, the thirteenth pin of the tenth multiplexer U10 is connected to the Vsen end, the base of the first transistor Q1 is connected to the Port end, the sixth pin of the tenth multiplexer U10, the seventh pin of the tenth multiplexer U10, the eighth pin of the tenth multiplexer U10, the emitter of the first transistor Q1, the other end of the sixth resistor R6, the other end of the eighth resistor R8, the other end of the twelfth resistor R12, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14 and the ground end are connected.

[0028] Specifically, the configuration unit further includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5;

[0029] One end of the second resistor R2 is connected to the first pin of the third inverter U3, one end of the third resistor R3 is connected to the fourth pin of the first trigger U1, one end of the fourth resistor R4 is connected to the second connection end of the fourth AND gate U4, one end of the fifth resistor R5 is connected to the second pin of the second digital potentiometer U2, and the other end of the second resistor R2, the other end of the third resistor R3, the other end of the fourth resistor R4, and the other end of the fifth resistor R5 are connected to the ground.

[0030] Specifically, the detection module further includes a seventh resistor R7, a ninth resistor R9, and a tenth resistor R10;

[0031] One end of the seventh resistor R7 is connected to the fifth pin of the sixth trigger U6, one end of the ninth resistor R9 is connected to the fifth pin of the fifth trigger U5, one end of the tenth resistor R10 is connected to the fifth pin of the seventh trigger U7, and the other ends of the seventh resistor R7, the ninth resistor R9, and the tenth resistor R10 are connected to the ground.

[0032] Specifically, the first transistor Q1 is an N-type transistor.

[0033] Specifically, the eleventh resistor R11 is an adjustable resistor or the first capacitor C1 is a variable capacitor, which is used to match the integration rate of the eleventh resistor R11 and the first capacitor C1 with the inverting terminal of the ninth operational amplifier U9.

[0034] When the program is run for the first time, a high-level Input signal is input to the initial configuration module to automatically match the program running time. There are multiple configuration units in the configuration module, and the number is consistent with the number of programs to be detected. After the program is completed, a low-level Input signal is input, and a high-level Input signal is input again after the second program is started. When the first program is started, the configuration unit converts the program running time into a Vsen signal, and starts the corresponding connected configuration unit after the first program is completed, and automatically shields the subsequent Input signal from regulating the current configuration unit. The corresponding configuration unit will be converted after the second program is started, and each configuration unit will input the converted Vsen signal into the detection module, and so on, until the initialization is completed after the last configuration unit is completed. Subsequently, the dog feeding signal Port fed back by the processor at the end of each program run is input into the detection module. The detection module can automatically detect according to the vsen signal of the corresponding program, and feed back the Vout signal to reset the processor after a fault.

[0035] In the circuit principle of the configuration unit, if serial input is adopted, each configuration unit is connected in series, and the Vput signal of the first configuration unit is connected to the Input of the second configuration unit. The configuration unit needs to automatically shield the regulation of the current configuration unit by subsequent signals after the program ends, and correspond to the start and end during serial input. The signal flow is that when the Input signal is input, the third inverter U3 is cut off, and the second pin of the second digital potentiometer U2 will be pulled down through the fifth resistor R5 and the ground loop, and when the CLK clock signal is at the rising edge, the distance between the fifth pin of the second digital potentiometer U2 and the third pin of the second digital potentiometer U2 is adjusted, and the Vsen voltage rises with the program running. When the program ends, the Input is in a low level state. At this time, the signal output by the third inverter U3 is in a high level again and is fed back to the third pin of the first trigger U1. The fifth pin and the sixth pin of the first trigger U1 are flipped, and the fifth pin of the first trigger U1 will output a signal that is fed back to the second pin of the fourth AND gate U4 one way, and the other way is fed back to the seventh pin of the second digital potentiometer U2 , the sixth pin of the first trigger U1 is cut off, and the signal fed back from the sixth pin of the first trigger U1 to the fourth pin of the first trigger U1 through the first diode D1 in the initial state is removed. The fourth pin of the first trigger U1 will be pulled down by the third resistor R3 and is in a set state, shielding the regulation of the current configuration unit when the subsequent Input signal is input, but does not affect the start and stop correspondence of the second configuration unit. When the second program is started, the Input signal is at a high level again, and there is input at the first pin and the second pin of the fourth AND gate U4. The fourth AND gate U4 outputs a Vput signal to the second configuration unit. The second configuration unit is regulated through the above circuit process until the Input is at a low level after the second program is terminated, and then the third configuration unit is started. The Vsen signal of each configuration unit is fed back to the detection module, and the second resistor R2 to the fifth resistor R5 are removed when external interrupt control is required, and the signal transmission is completed by enabling the pull-down resistor. This method replaces the unified time-consuming setting of the traditional watchdog circuit, responds faster in abnormal situations, and serial input does not occupy additional ports when there are many programs. When there are fewer programs and the I / O port resources are sufficient, a parallel input method is also provided. The parallel connection inputs the program start and stop signals through the processor's I / O port and the Input connection of each configuration unit. There is no need to change the connection of each configuration unit, and initialization is faster.

[0036] The detection module is used for centralized detection. The different Vsen signals of each program running time are controlled by the tenth multiplexer U10 and input to the ninth operational amplifier U9 for detection, wherein the X0 to X7 pins of the tenth multiplexer U10 are connected to the Vsen signals corresponding to the configuration units. The A, B, and C pins of the tenth multiplexer U10 can control the Vsen signals on any pin from X0 to X7 to be fed back to the X pin after input. The X pin signal is input to the inverting end of the ninth operational amplifier U9 for comparison. The in-phase end of the ninth operational amplifier U9 is connected to the first capacitor C1. The first capacitor C1 is used for timing when there is no dog feeding signal Port input. When the processor feeds back the Port dog feeding signal, the first transistor The tube Q1 will be turned on, and the first capacitor C1 releases the charge after passing through the collector, emitter and grounding loop of the first transistor Q1. At this time, there is no voltage on the first capacitor C1. When the first program is in the running state, there is no signal input to the port, and the first transistor Q1 is cut off. The power signal is integrated through the eleventh resistor R11 and the first capacitor C1. When the program is abnormal, the voltage at the end of the first capacitor C1 will be greater than the voltage at the inverting end of the ninth operational amplifier U9. At this time, the ninth operational amplifier U9 outputs a reset signal Vout to the processor for a reset operation. On the contrary, if there is no dead loop or other states, and the program can run normally, after running to the dog feeding instruction, the processor will input a Port signal to reset the detection module; X0 to X10 of the tenth multiplexer U10 The process of inputting the Vsen signal on the 7-pin to the X pin of the tenth multiplexer U10 is completed by the fifth trigger U5 to the seventh trigger U7. The attached figure shows an 8-bit detection example (7-bit output 1-bit reset). The number of bits detected can be selected by connecting the second pin of the first connector P1 and the pins from X0 to X7. The attached figure uses X7 to feedback to the first connector P1 for reset. The third pin of the fifth trigger U5 inputs the port dog feeding signal. Every time the port inputs a signal, the fifth trigger U5, the sixth trigger U6, and the seventh trigger U7 output to the A, B, and C pins of the tenth multiplexer U10 change their states, initially to 000. After the program is run, the true value state of the ABC pins It will make the X7 pin output, at this time the eighth inverter U8 is cut off, the fifth trigger U5, the sixth trigger U6, and the seventh trigger U7 are forced to output the fifth pin again, the sixth pin is reset to the 000 state, the seventh resistor R7, the ninth resistor R9, and the tenth resistor R10 will remove the pin enable pull-down when there is external direct input to the A, B, and C pins of the tenth multiplexer U10. It is also completed by hardware as a whole in the detection module and the initialization configuration module. Compared with software and mixed methods, the detection is more reliable, and there is no need to reinsert the dog feeding instruction into the replaced program. When replacing or setting a new program, the initialization match can be re-performed, so that the instruction output can be directly called after each program ends, and the compatibility is higher.

[0037] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. An anti-interference circuit for an industrial control screen mainboard, characterized in that: It includes a processor, an initial configuration module, and a detection module. The processor inputs a high-level Input signal to the initial configuration module when the program is first run, and inputs a low-level Input signal after the program is completed. The initial configuration module includes multiple configuration units, which are connected in series. The number of configuration units is consistent with the number of programs. After the first program is run, the high-level Input signal fed back by the processor is input to the first configuration unit. The inverter of the first configuration unit inverts the Input signal to pull down the adjustment pin of the digital potentiometer, converts the program running time into a voltage signal of the digital potentiometer output pin Vsen, and when the first program ends, the trigger of the first configuration unit outputs a signal to the wake-up pin of the digital potentiometer to start and stop correspondingly, and blocks subsequent programs when the second program arrives. The Input signal regulates the first configuration unit, and the first configuration unit trigger feedback signal to the AND gate allows the processor to feedback the Input high-level signal when the second program starts to start the second configuration unit. The second configuration unit will be converted after the second program starts until the last configuration unit is completed and initialized; the Vsen signal of each configuration unit is then fed back to the input end of the multiplexer in the detection module. When all programs are run, the processor calls the dog feeding signal port to the trigger of the detection module to change the selection end state of the multiplexer, so that the common output end of the multiplexer outputs different Vsen signals in the input end. The operational amplifier of the detection module performs detection based on the different Vsen signals and Port signal inputs, and feeds back the Vout reset signal to the processor in case of abnormality.

2. The anti-interference circuit of the industrial control screen motherboard according to claim 1 is characterized in that: The configuration unit includes a first trigger, a second digital potentiometer, a third inverter, a fourth AND gate, a first resistor, and a first diode; The first pin of the first trigger, the eighth pin of the second digital potentiometer, and one end of the first resistor are connected to the power supply, the second pin of the first trigger, the sixth pin of the first trigger are connected to the anode of the first diode, the third pin of the first trigger and the second pin of the second digital potentiometer are connected to the second pin of the third inverter, the fourth pin of the first trigger is connected to the cathode of the first diode, the fifth pin of the first trigger and the seventh pin of the second digital potentiometer are connected to the second connection end of the fourth AND gate, the first pin of the second digital potentiometer is connected to the clock source at the CLK end, the third pin of the second digital potentiometer, the other end of the first resistor are connected to the Vsen end, the first pin of the third inverter, the first connection end of the fourth AND gate are connected to the Input end, the output end of the fourth AND gate is connected to the Vput end, the fourth pin of the second digital potentiometer, the fifth pin of the second digital potentiometer, the sixth pin of the second digital potentiometer are connected to the ground end.

3. The anti-interference circuit of the industrial control screen motherboard according to claim 1 is characterized in that: The detection module includes a fifth trigger, a sixth trigger, a seventh trigger, an eighth inverter, a ninth operational amplifier, a tenth multiplexer, a first transistor, a sixth resistor, an eighth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a first capacitor, and a first connector; The fourth pin of the fifth trigger, the fourth pin of the sixth trigger, the fourth pin of the seventh trigger, the sixteenth pin of the tenth multiplexer, and one end of the eleventh resistor are connected to the power supply, the first pin of the fifth trigger, the first pin of the sixth trigger, the first pin of the seventh trigger and one end of the eighth resistor and the second pin of the eighth inverter are connected, the second pin of the fifth trigger and the sixth pin of the fifth trigger are connected, the second pin of the sixth trigger and the sixth pin of the sixth trigger are connected, the second pin of the seventh trigger and the sixth pin of the seventh trigger are connected, the third pin of the fifth trigger and one end of the sixth resistor are connected to the Port end, the fifth pin of the fifth trigger and the third pin of the sixth trigger and the ninth pin of the tenth multiplexer are connected, the fifth pin of the sixth trigger and the third pin of the seventh trigger and the tenth pin of the tenth multiplexer are connected, and the fifth pin of the seventh trigger and the tenth pin of the tenth multiplexer are connected. A pin of the first transistor is connected, a first pin of the eighth inverter, one end of the fourteenth resistor and the first pin of the first connector are connected, a non-inverting end of the ninth operational amplifier and the other end of the eleventh resistor, one end of the twelfth resistor, the collector of the first transistor and one end of the first capacitor are connected, an inverting end of the ninth operational amplifier and one end of the thirteenth resistor and the third pin of the tenth multiplexer are connected, an output end of the ninth operational amplifier and the Vout end are connected, a fourth pin of the tenth multiplexer and the second pin of the first connector are connected, a thirteenth pin of the tenth multiplexer and the Vsen end are connected, a base of the first transistor and the Port end are connected, a sixth pin of the tenth multiplexer, a seventh pin of the tenth multiplexer, an eighth pin of the tenth multiplexer, an emitter of the first transistor, the other end of the sixth resistor, the other end of the eighth resistor, the other end of the twelfth resistor, the other end of the thirteenth resistor, the other end of the fourteenth resistor and the ground end are connected.

4. The anti-interference circuit of the industrial control screen mainboard according to claim 2, characterized in that: The configuration unit further includes a second resistor, a third resistor, a fourth resistor, and a fifth resistor; One end of the second resistor is connected to the first pin of the third inverter, one end of the third resistor is connected to the fourth pin of the first trigger, one end of the fourth resistor is connected to the second connection end of the fourth AND gate, one end of the fifth resistor is connected to the second pin of the second digital potentiometer, and the other ends of the second resistor, the third resistor, the fourth resistor, and the fifth resistor are connected to the ground end.

5. The anti-interference circuit of the industrial control screen mainboard according to claim 3 is characterized in that: The detection module further includes a seventh resistor, a ninth resistor, and a tenth resistor; One end of the seventh resistor is connected to the fifth pin of the sixth trigger, one end of the ninth resistor is connected to the fifth pin of the fifth trigger, one end of the tenth resistor is connected to the fifth pin of the seventh trigger, and the other ends of the seventh resistor, the ninth resistor, and the tenth resistor are connected to the ground.

6. The industrial control screen mainboard anti-interference circuit according to claim 3, characterized in that: The first transistor is an N-type transistor.

7. The industrial control screen mainboard anti-interference circuit according to claim 3, characterized in that: The eleventh resistor is an adjustable resistor or the first capacitor is a variable capacitor, which is used to match the integration rate of the eleventh resistor and the first capacitor with the inverting terminal of the ninth operational amplifier.

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