RAID engine and RAID bridge chip

Abstract

The present invention discloses a RAID engine and a RAID bridge chip. In order to reduce the design and integration difficulty of the off-chip memory to the bridge chip, the RAID engine of the present invention includes an on-chip memory; data is transmitted between the RAID processor and the on-chip memory through a first data interface; data is transmitted between the SATA core and the on-chip memory through a second data interface. The present invention solves the technical problem of high difficulty in designing and integrating the bridge chip, reduces the chip design and integration difficulty in the bridge chip, and avoids the cost of the off-chip memory. The present invention is suitable for the field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a RAID engine and a RAID bridge chip. Background Art

[0002] The reading, writing and storage of a single disk has the risks or defects of limited capacity, low input / output performance and data loss. Redundant Array of Independent Disks (RAID) is a storage technology that was born to overcome the above defects.

[0003] The basic idea of ​​RAID disk array is to use multiple independent disks together to form a large disk system, so as to achieve better storage performance and higher reliability than a single disk. However, for a computer, RAID disk array is like a separate hard disk or logical storage unit. Users can decide how the device processes data by configuring the RAID mode of the device.

[0004] Commonly used RAID modes include RAID-0, RAID-1, RAID-5 and RAID-10. RAID-0 mainly implements striped storage of data, improving disk array performance. RAID-1 mainly implements mirror storage and implements disk data backup. RAID-5 implements disk data recovery and enhances disk data recovery capabilities. RAID-10 combines the characteristics of RAID-0 and RAID-1.

[0005] Depending on the selected mode, RAID disk arrays can enhance data transfer performance, data recovery capabilities, and data backup capabilities compared to a single disk.

[0006] RAID implementation can be divided into two types: soft implementation and hard implementation. Soft RAID refers to the use of the host's central processing unit (CPU) to complete RAID data calculation and processing; hard RAID refers to the use of a dedicated processor, namely the RAID processor, and cache to process RAID data. Obviously, soft RAID is extremely dependent on the computing power of the host's CPU and the RAID data calculation and processing algorithm.

[0007] When the number of disks mounted downstream of the host device is large, more CPU resources and power consumption are required. Relatively speaking, hardware RAID does not consume CPU resources and is more flexible for tasks such as disk monitoring, expansion, backup, and replacement.

[0008] RAID bridge chips can realize data transmission between host devices and disks, and RAID engines are the core of RAID bridge chips. In addition to using dedicated processors, RAID engines in existing technologies also need to use off-chip dual data rate synchronous dynamic random access memory (DDRSDRAM) to cache and move data. In order to make the RAID processor and DDR SDRAM more efficient, the designers of RAID processors have to consider adding additional control logic and interfaces, which makes the data flow interaction, integration, and design and development of RAID processors more complicated.

[0009] How to reduce the difficulty of chip design and integration in bridge chips and avoid the cost of off-chip memory has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0010] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0011] A RAID engine comprises an on-chip memory; data is transmitted between a RAID processor and the on-chip memory via a first data interface; data is transmitted between a SATA core and the on-chip memory via a second data interface.

[0012] Furthermore, the RAID engine is a circuit module in a RAID bridge chip.

[0013] Furthermore, the DMA module in the SATA core is used to transfer data from the physical storage device to the on-chip memory, or / and to transfer data from the on-chip memory to the physical storage device.

[0014] Furthermore, the RAID engine also includes a control register module, and the control register module is used to receive a control signal from a RAID processor.

[0015] Furthermore, the control signal includes information indicating the RAID mode and the number of physical storage devices.

[0016] Furthermore, the first data interface and the second data interface are both AMBA data interfaces.

[0017] Furthermore, the RAID engine also includes a RAID state machine, and the RAID state machine is used to jump to a corresponding RAID data processing mode according to information about the RAID mode and the number of physical storage devices obtained from the control register module.

[0018] Furthermore, the RAID processor transmits a control signal to a control register module via a first control interface; the RAID engine also includes a data processing module, which processes the control signal to obtain a processed control signal; the data processing module transmits the processed control signal to the SATA core via a second control interface.

[0019] Furthermore, both the first control interface and the second control interface are AMBA control interfaces; when determining the corresponding RAID data processing mode, the RAID state machine also uses the information indicated by the data processing module.

[0020] A RAID bridge chip, comprising a RAID processor, a SATA core and a RAID engine as described in any of the preceding items.

[0021] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0022] (1) The RAID engine has its own on-chip DRAM storage that can realize data caching and transmission, eliminating the cost of off-chip storage.

[0023] (2) Since there is no need to add additional DDR SDRAM outside the chip, the corresponding related control logic and interface are also unnecessary, which reduces the difficulty of chip integration and design, as well as the chip area and the number of chip interfaces.

[0024] (3) Supports multi-mode RAID engine, which can realize data storage in various RAID modes.

[0025] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a working schematic diagram of a RAID bridge chip including a RAID engine of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0029] The present invention discloses a RAID engine supporting multiple modes, which can realize the storage of multiple RAID mode data, and the RAID engine has a dynamic random access memory (DRAM) inside, which is used to realize data caching and transmission, and does not require additional off-chip DDR SDRAM, thereby simplifying chip design and integration steps. Specifically, the RAID engine of the present invention is realized by the following technical solution.

[0030] Figure 1 The schematic diagram of the RAID bridge chip including the RAID engine of the present invention is shown. The RAID processor is a special processor for implementing RAID functions. The RAID bridge chip includes a RAID processor, a RAID engine and a SATA core.

[0031] Typically, in a RAID bridge chip, a RAID processor and a Serial Advanced Technology Attachment (SATA) core of a physical storage device are directly connected via a First In First Out (FIFO) interface or an Advanced Microcontroller Bus Architecture (AMBA) interface. To achieve the technical purpose of the present invention, a RAID engine is included between the RAID processor and the SATA core.

[0032] Different from software that can process data in a programmed manner, the RAID engine of the present invention is a hardware-implemented circuit module for implementing data processing between a RAID processor and a SATA core. Obviously, the RAID engine of the present invention can be reused as an intellectual property core in the field of integrated circuits.

[0033] The RAID engine in the present invention includes an on-chip memory; in addition, the RAID engine also includes a first data interface, a second data interface, a first control interface and a second control interface.

[0034] Data is transmitted between the RAID processor and the on-chip memory via the first data interface; data is transmitted between the SATA core and the on-chip memory via the second data interface.

[0035] Preferably, the RAID engine at least includes a first AMBA control interface, a second AMBA control interface, a first AMBA data interface, and a second AMBA data interface. The first AMBA data interface and the second AMBA data interface are used to implement data access and / or transmission between the RAID processor and the physical storage device, which includes reading data from the physical storage device to the RAID processor and the host device, and also includes writing data from the host device and / or the RAID processor to the physical storage device.

[0036] That is to say, in the above specific embodiment, the first data interface is a first AMBA data interface, and the second data interface is a second AMBA data interface; in other words, in this specific embodiment, both the first data interface and the second data interface are AMBA data interfaces. The first control interface is a first AMBA control interface, and the second control interface is a second AMBA control interface; in other words, in this specific embodiment, both the first control interface and the second control interface are AMBA control interfaces.

[0037] Preferably, the physical storage device is a disk. Taking n disks as an example, disk 1, disk 2, ..., disk n are mounted under the host device, and they are connected to the SATA core through SATA interface 1, SATA interface 2, ..., SATA interface n, respectively, where n is a positive integer, such as n is 4.

[0038] The on-chip memory included in the RAID engine may be a memory located in the RAID engine. For example, the on-chip memory is a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0039] Based on the RAID bridge chip including the on-chip memory, there is no need to add an off-chip DDR SDRAM outside the RAID bridge chip, which can reduce the cost on one hand and reduce the design and integration complexity of the RAID bridge chip on the other hand.

[0040] The SATA core also includes a direct memory access (DMA) module, which is used to transfer data from a physical storage device to the on-chip memory, or / and to transfer data from the on-chip memory to a physical storage device.

[0041] In addition, the RAID engine also includes a control register module, a RAID state machine, and a data processing module.

[0042] For the write process, the workflow of the RAID engine is as follows: For example, the user configures the RAID mode and the number of disks or specifies a number of disks according to needs.

[0043] The RAID processor transmits the control signal to the control register module through the first control interface. Specifically, the RAID processor transmits the control signal to the control register module in the RAID engine through the first AMBA control interface.

[0044] The RAID processor stores the data to be written into the on-chip memory through the first AMBA data interface. The control signal includes information indicating the RAID mode and the number of physical storage devices.

[0045] For example, the control register module implements the configuration of the number of disks and the RAID mode according to the control signal. Optionally, the user can also change the number of disks and the RAID mode as needed.

[0046] The RAID state machine combines the information indicated by the data processing module and jumps to the corresponding RAID data processing mode according to the RAID mode and the number of disks configured by the user. For example, the RAID data processing mode can be one of RAID-0, RAID-1, RAID-5 and RAID-10.

[0047] The data processing module processes the control signal to obtain a processed control signal. The data processing module transmits the processed control signal to the SATA core through the second control interface. Specifically, the processed control signal is transmitted to the SATA core through the second AMBA control interface. The DMA module in the SATA core transmits the data to be written in the on-chip memory to the disk through the second AMBA data interface according to the processed control signal.

[0048] For example, if the user selects the RAID-0 mode, the data to be written in the on-chip memory is written to the corresponding multiple disks in a striped manner.

[0049] Similarly, for the read process, the workflow of the RAID engine is as follows: the user determines the RAID mode and the number of enabled disks according to needs. The RAID processor transmits the control signal to the control register module in the RAID engine through the first AMBA control interface.

[0050] The control register module implements the configuration of the number of disks and the RAID mode according to the control signal. The RAID state machine, in conjunction with the data processing module, jumps to the corresponding RAID data processing mode according to the RAID mode and number of disks configured by the user. For example, the RAID data processing mode can be one of RAID-0, RAID-1, RAID-5, and RAID-10.

[0051] The data processing module processes the control signal to obtain a processed control signal, and the processed control signal is transmitted to the SATA core through the second AMBA control interface.

[0052] According to the RAID mode configured by the user, the DMA module in the SATA core transfers the data that needs to be transferred from the disk to the on-chip memory. After the data transfer is completed, the RAID processor receives a notification to read the data from the on-chip memory, and then reads the data back to the RAID processor. Further, the RAID processor transmits the data back to the host device.

[0053] In summary, the present invention realizes data reading and writing of various types of RAID modes through the RAID engine. Compared with the prior art, the present invention can avoid adding additional DDR SDRAM outside the RAID bridge chip, reduce chip area, cost, number of chip interfaces, and reduce chip design and integration complexity.

[0054] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0055] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A RAID engine, characterized in that: The RAID engine includes an on-chip memory; Transmitting data between the RAID processor and the on-chip memory via the first data interface; Data is transmitted between the SATA core and the on-chip memory via the second data interface; The RAID engine is a circuit module in the RAID bridge chip; The DMA module in the SATA core is used to transfer data from the physical storage device to the on-chip memory, or / and to transfer data from the on-chip memory to the physical storage device; The RAID engine also includes a control register module, and the control register module is used to receive a control signal from the RAID processor; The RAID engine also includes a RAID state machine, which is used to jump to a corresponding RAID data processing mode according to the information of the RAID mode and the number of physical storage devices obtained from the control register module; The RAID processor transmits a control signal to the control register module via a first control interface; The RAID engine further includes a data processing module, which processes the control signal to obtain a processed control signal; The data processing module transmits the processed control signal to the SATA core through the second control interface.

2. The RAID engine according to claim 1, wherein: The control signal includes information indicating the RAID mode and the number of physical storage devices.

3. The RAID engine according to claim 2, wherein: The first data interface and the second data interface are both AMBA data interfaces.

4. The RAID engine according to claim 3, characterized in that: The first control interface and the second control interface are both AMBA control interfaces; The RAID state machine also determines the corresponding RAID data processing mode based on the information indicated by the data processing module.

5. A RAID bridge chip, characterized in that: The bridge chip comprises a RAID processor, a SATA core and the RAID engine according to any one of claims 1-4.

Images