Circuit board card and signal generator

Abstract

The present application belongs to the field of electronic circuit technology, and specifically discloses a circuit board card and a signal generator, wherein the circuit board card comprises: a backplane configured with a low-speed bus interface for docking a main card, a high-speed bus interface for docking a main card, a bus expansion interface for docking a bus expansion board, and multiple daughter card interfaces, wherein the communication rate of the high-speed bus is higher than the communication rate of the low-speed bus; the low-speed bus interface is configured with multiple groups of low-speed bus pins, and one group of low-speed bus pins is connected to a daughter card interface; the high-speed bus interface is configured with at least one group of high-speed bus pins; in the case of high-speed bus communication, the bus expansion interface is plugged with a bus expansion board, and each group of high-speed bus pins is expanded into multiple groups of high-speed bus pins, and each group of high-speed bus pins obtained by expansion is connected to a daughter card interface. Through the present application, the main card and the daughter card are supported to communicate using a low-speed bus and / or a high-speed bus, thereby achieving compatibility with multiple bus communication scenarios.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuit technology, and more specifically, relates to a circuit board card and a signal generator. Background Art

[0002] A pattern generator (PG) is a specialized test device used to evaluate and calibrate the performance of display devices. These devices can be liquid crystal displays (LCDs), light-emitting diodes (LEDs), or organic light-emitting diodes (OLEDs). The PG can generate a range of standard or custom image patterns to test the display's resolution, color accuracy, brightness, contrast, response time, and the presence of dead pixels.

[0003] Typically, a PG consists of a main card, multiple daughter cards, and a backplane. The main card communicates with the daughter cards via the backplane, controlling each daughter card. The daughter cards are then connected to the device under test. Communication between the main card and daughter cards can occur over either a high-speed or low-speed bus.

[0004] In the prior art, for situations where a high-speed bus can be used for communication between the main card and the daughter card, corresponding boards (including the main card and backplane, etc.) are designed. For situations where a low-speed bus can be used for communication between the main card and the daughter card, corresponding boards are also designed. The same board only supports one bus communication scenario (low-speed bus communication scenario or high-speed bus communication scenario). For PG boards, how to make them compatible with multiple bus communication scenarios is a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0005] In view of the defects of the existing technology, the purpose of this application is to make the PG board compatible with multiple bus communication scenarios.

[0006] To achieve the above objectives, in a first aspect, the present application provides a circuit board card, comprising: a main card and a backplane;

[0007] The backplane is equipped with a low-speed bus interface for connecting to the main card, a high-speed bus interface for connecting to the main card, a bus expansion interface for connecting to the bus expansion board, and multiple daughter card interfaces. The communication rate of the high-speed bus is higher than that of the low-speed bus.

[0008] The main card is configured with a main control chip slot, a low-speed bus interface for docking the backplane, and a high-speed bus interface for docking the backplane. The main control chip slot is connected to the low-speed bus interface, and the main control chip slot is connected to the high-speed bus interface;

[0009] The low-speed bus interface is configured with multiple groups of low-speed bus pins, one group of low-speed bus pins is used to transmit multiple low-speed bus signals, and one group of low-speed bus pins in the low-speed bus interface is correspondingly connected to a group of low-speed bus pins in a daughter card interface;

[0010] The high-speed bus interface is configured with at least one set of high-speed bus pins, and the set of high-speed bus pins is used to transmit one high-speed bus signal;

[0011] In the case where the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface, and the bus expansion board is configured with at least one high-speed bus switching chip. High-speed bus pins of the same group in the high-speed bus interface are connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins, and each group of the multiple groups of high-speed bus pins obtained after expansion is connected to a corresponding group of high-speed bus pins in a daughter card interface;

[0012] A daughter card interface is connected to a daughter card.

[0013] The board provided in the embodiment of the present application can support communication between the main card and the sub-card using a low-speed bus and / or a high-speed bus, thereby achieving compatibility with multiple bus communication scenarios.

[0014] In a possible implementation, a main control chip is placed in the main control chip slot, the main control chip is configured with a low-speed bus, and the low-speed bus of the main control chip is connected to the low-speed bus interface.

[0015] In a possible implementation, a main control chip is placed in the main control chip slot, the main control chip is configured with a high-speed bus, and the high-speed bus of the main control chip is connected to the high-speed bus interface.

[0016] In a possible implementation, the main control chip is an FPGA or an MCU.

[0017] In a possible implementation, on the backplane, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector;

[0018] On the main card, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector;

[0019] The high-speed bus connector on the backplane is a male socket or a female socket, and correspondingly, the high-speed bus connector on the main card is a female socket or a male socket.

[0020] In a possible implementation, the main card includes: a main control chip carrier board and a low-speed bus interface board;

[0021] The main control chip carrier is configured with a main control chip slot, a high-speed bus interface for docking with a backplane, and a low-speed bus slot for carrying the low-speed bus interface board in a stacked manner;

[0022] The low-speed bus interface board is provided with a low-speed bus interface for docking with the backplane;

[0023] The main control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the main control chip slot is connected to the high-speed bus interface.

[0024] In a possible implementation, the low-speed bus interface is configured with a plurality of pins for transmitting slot status signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting slot status signals;

[0025] On the backplane, a pin for transmitting a slot status signal is correspondingly connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card;

[0026] On the main card, each pin for transmitting a slot status signal is connected to the main control chip slot.

[0027] In a possible implementation, the low-speed bus interface is configured with a plurality of pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting synchronization signals;

[0028] On the backplane, a pin for transmitting a synchronization signal is correspondingly connected to a synchronization signal pin of a daughter card interface;

[0029] On the main card, each pin for transmitting a synchronization signal is connected to a main control chip slot.

[0030] In one possible implementation, the bus expansion interface and the bus expansion board are provided with a first high-speed snap connector, and each group of high-speed bus pins in the high-speed bus interface of the backplane is connected to the high-speed bus switch chip through the first high-speed snap connector;

[0031] The bus expansion interface and the bus expansion board are provided with a second high-speed snap connector, and the high-speed bus pins in each daughter card interface are connected to the high-speed bus switching chip through the second high-speed snap connector.

[0032] In a possible implementation, the high-speed bus is a PCIe bus.

[0033] In a possible implementation, the low-speed bus is an SPI bus or an I2C bus.

[0034] In a second aspect, the present application further provides a signal generator, comprising: a daughter card and any one of the above-mentioned circuit board cards.

[0035] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0036] (1) Improve R&D and production efficiency: During the R&D process, only one universal board needs to be developed and iterated instead of multiple different boards, which simplifies the R&D process and improves R&D work efficiency. During the production process, only one universal board needs to be operated instead of multiple different boards, which simplifies the training process for production personnel, reduces the difficulty of operation for production personnel, and improves the work efficiency of production personnel.

[0037] (2) Improved test flexibility: During the test, flexible switching between high-speed bus communication and low-speed bus communication can be achieved without replacing the board. It can also support test scenarios where the main card and multiple sub-cards use both low-speed and high-speed buses for communication, expanding the application range of the board.

[0038] (3) Reduction of spare parts: Since one board can be applied to multiple bus communication scenarios, there is no need to prepare multiple dedicated boards for different bus communication requirements. This can reduce the inventory of spare parts and reduce management costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the structure of the backplane provided in an embodiment of the present application;

[0040] Figure 2 This is a schematic diagram of the structure of the main card provided in an embodiment of the present application;

[0041] Figure 3 Schematic diagram of the pin configuration of the low-speed bus interface provided in an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the pin configuration of the high-speed bus interface provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to facilitate a clearer understanding of the various embodiments of the present application, some relevant background knowledge is first introduced as follows.

[0044] If a high-speed bus can be used for communication between the main card and the sub-card, the control modules on the main card and the sub-card need to support the high-speed bus communication standard. In addition, since the high-speed bus resources of the control module on the main card are limited (generally, the control module on the main card is configured with 1 or 2 high-speed buses, and the number of high-speed buses configured by the control module is less than the number of sub-cards, which cannot meet the communication needs of the main card and multiple sub-cards), a bus expansion module needs to be set on the backplane. The bus expansion module is used to expand the high-speed bus of the main card, expanding one high-speed bus into multiple high-speed buses so that the number of expanded high-speed buses matches the number of sub-cards.

[0045] If a low-speed bus can be used for communication between the main card and the sub-card, the control modules on the main card and the sub-card need to support the low-speed bus communication standard. Moreover, since the low-speed bus resources of the control module on the main card are relatively abundant (generally, the control module on the main card is configured with multiple low-speed buses to meet the communication needs of the main card and multiple sub-cards), a bus expansion module does not need to be set on the backplane.

[0046] The same board (including the main card and backplane, etc.) only supports one bus communication scenario, low-speed bus communication scenario or high-speed bus communication scenario, and has poor compatibility.

[0047] In order to overcome the above-mentioned defects, the present application provides a circuit board card and a signal generator, which can support communication between the main card and the sub-card using a low-speed bus and / or a high-speed bus, thereby achieving compatibility with multiple bus communication scenarios.

[0048] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0049] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0050] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0051] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0052] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0053] An embodiment of the present application provides a circuit board card, including: a main card and a backplane.

[0054] Figure 1 This is a schematic diagram of the structure of the backplane provided in the embodiment of the present application. Figure 1 As shown, the backplane is configured with a low-speed bus interface for docking the main card, a high-speed bus interface for docking the main card, a bus expansion interface for docking the bus expansion board, and multiple daughter card interfaces (one daughter card interface is connected to one daughter card). The communication rate of the high-speed bus is higher than the communication rate of the low-speed bus.

[0055] Figure 2 This is a schematic diagram of the structure of the main card provided in the embodiment of the present application. Figure 2 As shown, the main card is configured with a main control chip slot (for carrying the main control chip), a low-speed bus interface for docking the backplane, and a high-speed bus interface for docking the backplane. The main control chip slot is connected to the low-speed bus interface, and the main control chip slot is connected to the high-speed bus interface.

[0056] Alternatively, as Figure 2 As shown, the main card is also configured with an external interface. Exemplarily, the main card can communicate with the host computer through the external interface.

[0057] The low-speed bus interface is configured with multiple groups of low-speed bus pins, one group of low-speed bus pins is used to transmit multiple low-speed bus signals, and one group of low-speed bus pins in the low-speed bus interface is connected to a group of low-speed bus pins in a daughter card interface; the high-speed bus interface is configured with at least one group of high-speed bus pins, one group of high-speed bus pins is used to transmit one high-speed bus signal.

[0058] For example, Figure 3 FIG. 1 is a schematic diagram of the pin configuration of the low-speed bus interface provided in an embodiment of the present application. Figure 3 As shown, the low-speed bus interface may be configured with m groups of low-speed bus pins, where m may represent the number of daughter card interfaces. Figure 4 : is a schematic diagram of the pin configuration of the high-speed bus interface provided in the embodiment of the present application, such as Figure 4 As shown, the high-speed bus interface can be configured with n groups of high-speed bus pins, where n represents the total number of high-speed lines supported by the main control chip.

[0059] When the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface. The bus expansion board is configured with at least one high-speed bus switching chip. The same group of high-speed bus pins in the high-speed bus interface are connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins. Each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion is connected to a corresponding group of high-speed bus pins in a daughter card interface.

[0060] The working principle of the circuit board card provided in the embodiment of the present application is introduced below.

[0061] During the process of assembling the board, the low-speed bus interface and the high-speed bus interface on the main card can be aligned with the low-speed bus interface and the high-speed bus interface on the backplane. When aligned, the main card is plugged into the backplane. After the plugging is completed, the low-speed bus interface on the main card and the low-speed bus interface on the backplane are electrically connected to each other, and the high-speed bus interface on the main card and the high-speed bus interface on the backplane are electrically connected to each other.

[0062] The low-speed bus interface on the backplane is a male or female socket, and correspondingly, the low-speed bus interface on the main card is a female or male socket. This ensures that the low-speed bus interface on the backplane can be adapted to the low-speed bus interface on the main card, thereby achieving reliable electrical connection between the low-speed bus on the backplane and the low-speed bus on the main card.

[0063] The high-speed bus interface on the backplane is a male or female socket, and correspondingly, the high-speed bus interface on the main card is a female or male socket. This ensures that the high-speed bus interface on the backplane and the high-speed bus interface on the main card can be adapted to each other, thereby achieving reliable electrical connection between the high-speed bus on the backplane and the high-speed bus on the main card.

[0064] For example, the high-speed bus is a PCIe bus, and the low-speed bus is an SPI bus or an I2C bus. For the Inter-Integrated Circuit (I2C) bus, I2C is a multi-host serial communication protocol commonly used to connect low-speed peripheral device chips. For the Serial Peripheral Interface (SPI), SPI is a full-duplex, synchronous communication protocol primarily used for short-distance communication.

[0065] A group of low-speed bus pins is connected to a daughter card interface. Accordingly, the daughter card interface is also configured with a group of low-speed bus pins.

[0066] Each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion is connected to a daughter card interface. Correspondingly, the daughter card interface is also configured with a group of high-speed bus pins.

[0067] The bus expansion board may be configured with one or more high-speed bus switch chips. The number of high-speed bus switch chips may be determined according to the processing capability of the high-speed bus switch chip and the number of daughter card interfaces.

[0068] If the main control chip is configured with multiple high-speed buses and a high-speed bus switch chip is configured on the bus expansion board, then the multiple high-speed buses on the main control chip are connected to the same high-speed bus switch chip on the bus expansion board via the high-speed bus interface. If the main control chip is configured with multiple high-speed buses and multiple high-speed bus switch chips are configured on the bus expansion board, then for any two high-speed buses on the main control chip, the two high-speed buses can be connected to the same high-speed bus switch chip on the bus expansion board via the high-speed bus interface, or the two high-speed buses can be connected to different high-speed bus switch chips on the bus expansion board via the high-speed bus interface.

[0069] For example, the total number of high-speed lines supported by the main control chip is 2, and the number of sub-card interfaces is 8. In this case, the 2-way high-speed bus needs to be expanded to an 8-way high-speed bus. If the processing capacity of a high-speed bus switching chip can meet the needs of expanding the 2-way high-speed bus to an 8-way high-speed bus, then a high-speed bus switching chip can be configured on the bus expansion board, and the 2-way high-speed buses on the main control chip are connected to the same high-speed bus switching chip on the bus expansion board via the high-speed bus interface.

[0070] For another example, the total number of high-speed lines supported by the main control chip is 2, and the number of sub-card interfaces is 10. In this case, the 2-way high-speed bus needs to be expanded to a 10-way high-speed bus. If the processing capacity of a high-speed bus switching chip cannot meet the needs of expanding the 2-way high-speed bus to a 10-way high-speed bus, the bus expansion board can be configured with 2 high-speed bus switching chips. The 2-way high-speed buses on the main control chip are connected to different high-speed bus switching chips on the bus expansion board via the high-speed bus interface. Each high-speed bus switching chip expands 1 high-speed bus to 5 high-speed buses.

[0071] The bus expansion interface is configured with at least n+m groups of high-speed bus pins, where n represents the total number of high-speed lines supported by the main control chip. Accordingly, the high-speed bus interface is configured with n groups of high-speed bus pins, and m represents the number of daughter card interfaces, that is, the number of high-speed bus pins obtained after expansion via the high-speed bus switching chip on the bus expansion board. <m。

[0072] For example, Figure 1As shown, the bus expansion interface includes a high-speed snap connector male socket 1 (i.e., the first high-speed snap connector of the bus expansion interface) and a high-speed snap connector male socket 2 (i.e., the second high-speed snap connector of the bus expansion interface). The high-speed snap connector male socket 1 is configured with n groups of high-speed bus pins, and the high-speed snap connector male socket 2 is configured with m groups of high-speed bus pins. Accordingly, as Figure 1 As shown, the bus expansion board includes a high-speed snap-on connector socket 1 (i.e., the first high-speed snap-on connector of the bus expansion board) and a high-speed snap-on connector socket 2 (i.e., the second high-speed snap-on connector of the bus expansion board). The high-speed snap-on connector socket 1 is configured with n groups of high-speed bus pins, and the high-speed snap-on connector socket 2 is configured with m groups of high-speed bus pins.

[0073] The high-speed bus interface is connected to the high-speed bus switching chip on the bus expansion board through n groups of high-speed bus pins (which can be used to transmit n high-speed bus signals) in the bus expansion interface, such as Figure 1 As shown, the first high-speed bus is connected to the high-speed bus switch chip 1, and the n-th high-speed bus is connected to the high-speed bus switch chip 2. The bus between the first high-speed bus and the n-th high-speed bus can be connected to the high-speed bus switch chip 1 and the high-speed bus switch chip 2 in an evenly distributed manner, so that each group of high-speed bus pins in the high-speed bus interface is connected to a high-speed bus switch chip. The n-way high-speed bus is expanded into m-way high-speed buses through the high-speed bus switch chip on the bus expansion board. The m-way high-speed buses are connected to the high-speed bus switch chip 2 through the m groups of high-speed bus pins in the bus expansion interface (such as Figure 1 As shown, the m groups of high-speed bus pins in the high-speed snap-on connector socket 2 are connected to the daughter card interface on the backplane. The number of high-speed buses obtained after expansion is equal to the number of daughter card interfaces, so that each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion is connected to a daughter card interface.

[0074] A high-speed bus switch chip is a chip with switch functionality used in a bus architecture, capable of routing and managing data between multiple devices. A high-speed bus signal on the main card is transmitted to the high-speed bus switch chip via a set of high-speed bus pins in the high-speed bus interface. The high-speed bus switch chip can then route the high-speed bus signal from the main card to multiple high-speed buses, expanding a single set of high-speed bus pins (corresponding to a single high-speed bus on the main card) into multiple sets of high-speed bus pins (corresponding to the multiple high-speed buses being routed).

[0075] For example, if the high-speed bus is a PCIe bus, the high-speed bus switch chip can be a PCIe switch chip. A PCIe switch chip is a "PCIe switch chip." "PCIe" here stands for "Peripheral Component Interconnect Express," and "switch" refers to the function of a switch. A "PCIe switch chip" is a chip that functions as a switch in the PCI Express bus architecture, routing and managing data between multiple devices.

[0076] Optionally, a main control chip is placed in the main control chip slot, the main control chip is configured with a low-speed bus, and the low-speed bus of the main control chip is connected to the low-speed bus interface.

[0077] Optionally, a main control chip is placed on the main control chip slot, and the main control chip is configured with a high-speed bus, and the high-speed bus of the main control chip is connected to the high-speed bus interface. Figure 2 As shown, the main control chip is configured with n high-speed buses, where n can be equal to 1 or 2.

[0078] Optionally, the main control chip may be configured with a high-speed bus and a low-speed bus at the same time. In this case, the low-speed bus of the main control chip is connected to the low-speed bus interface, and the high-speed bus of the main control chip is connected to the high-speed bus interface.

[0079] Exemplarily, the main control chip is FPGA or MCU.

[0080] It can be understood that when a low-speed bus is used for communication between the main card and the sub-card, a main control chip that can support the low-speed bus can be placed in the main control chip slot. The low-speed bus of the main control chip is connected to the sub-card interface through a low-speed bus interface. The main control chip can be equipped with multiple low-speed buses. Assuming that the number of sub-card interfaces is m, the main control chip is configured with k×m low-speed buses (k is an integer greater than or equal to 2), and k low-speed buses form a group. A group of low-speed buses is connected to the corresponding sub-card interface through a group of low-speed bus pins in the low-speed bus interface (used to transmit k low-speed bus signals), so that each group of low-speed buses on the main control chip can be connected to the corresponding sub-card interface.

[0081] It should be noted that the communication rate of a low-speed bus is limited. By connecting a set of low-speed buses on the main control chip to the corresponding daughter card interface, the communication rate between the main control chip and the daughter card can be increased, thereby effectively improving communication efficiency when using a low-speed bus for communication.

[0082] When a high-speed bus is used for communication between the main card and the sub-card, a main control chip that supports the high-speed bus can be placed in the main control chip slot, and a bus expansion board can be plugged into the bus expansion interface of the backplane. The main control chip can be equipped with one or more high-speed buses. Assuming that the main control chip is configured with n high-speed buses and the number of sub-card interfaces is m, the n high-speed buses of the main control chip are extended through the high-speed bus interface and the high-speed bus switching chip of the bus expansion board to obtain m high-speed buses after expansion. The m high-speed buses are connected to the m sub-card interfaces through m groups of high-speed bus pins. In this way, when the number n of high-speed buses of the main control chip is less than the number m of sub-cards, a communication connection supporting the high-speed bus standard can be established between the main chip and the m sub-cards.

[0083] When a low-speed bus is used for communication between the main card and a part of the daughter cards (assuming the number of these daughter cards is m1), and a high-speed bus is used for communication between the main card and another part of the daughter cards (assuming the number of these daughter cards is m2), a main control chip that supports both low-speed and high-speed buses can be placed in the main control chip slot. The main control chip is configured with k×m1 low-speed buses, with k low-speed buses forming a group. A group of low-speed buses is connected to the corresponding daughter card interface through a group of low-speed bus pins in the low-speed bus interface (for transmitting k low-speed bus signals). This daughter card interface is connected to one of the above-mentioned m1 daughter cards; the main control chip is also configured with n high-speed buses. The n high-speed buses of the main control chip are extended through the high-speed bus interface and the high-speed bus switching chip of the bus expansion board to obtain m2 high-speed buses after expansion. The m2 high-speed buses are connected to the m2 daughter card interfaces (this daughter card interface is connected to one of the above-mentioned m2 daughter cards) through m2 groups of high-speed bus pins.

[0084] Therefore, the board provided in the embodiment of the present application can support communication between the main card and the daughter card using a low-speed bus and / or a high-speed bus, achieving compatibility with various bus communication scenarios. The board can adapt to different types of daughter cards and has strong scalability.

[0085] In one possible implementation, the main card includes a main control chip carrier board and a low-speed bus interface board;

[0086] like Figure 2 As shown, the main control chip carrier board is configured with a main control chip slot, a high-speed bus interface for connecting to the backplane, and a low-speed bus slot for carrying a low-speed bus interface board in a stacked manner (a slot that supports the transmission of low-speed bus signals);

[0087] like Figure 2 As shown, the low-speed bus interface board is configured with a low-speed bus interface for docking with the backplane, and the low-speed bus interface board is also configured with a low-speed snap connector, which can be snapped with the low-speed bus slot;

[0088] like Figure 2 As shown, the main control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the main control chip slot is connected to the high-speed bus interface.

[0089] It is understandable that, in the prior art, since the main card of PG is only applicable to high-speed bus communication scenarios or low-speed bus communication scenarios, the main card is generally only equipped with an interface for a high-speed bus or an interface for a low-speed bus. In the embodiment of the present application, the main card is not only configured with a low-speed bus interface but also configured with a high-speed bus interface. Configuring two types of bus interfaces simultaneously on a main card will cause the board size to increase. In order to effectively control the board size, by configuring the main card as a main control chip carrier board and a low-speed bus interface board, the low-speed bus interface board is plugged into the main control chip carrier board through a low-speed bus slot, and the main control chip carrier board and the low-speed bus interface board can be assembled in a stacked manner to avoid placing the low-speed bus interface and the high-speed bus interface on the same plane, which can effectively reduce the size (area) of the main card.

[0090] It should be noted that compared with the high-speed bus, the low-speed bus has lower requirements for impedance continuity. Therefore, leading the low-speed bus to the backplane through the low-speed bus interface board has less impact on the signal quality on the low-speed bus.

[0091] In one possible implementation, the low-speed bus interface is configured with a plurality of pins for transmitting slot status signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting slot status signals;

[0092] On the backplane, a pin for transmitting a slot status signal is connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card (the signal is used to indicate that a daughter card is plugged into the daughter card interface);

[0093] On the main card, each pin for transmitting slot status signals is connected to the main control chip slot.

[0094] like Figure 1 As shown, a pin for transmitting a slot status signal is connected to a daughter card interface. Accordingly, the daughter card interface is also configured with a pin for transmitting a slot signal, that is, Figure 1 Slot status signal pin in .

[0095] It can be understood that when a sub-card is plugged into the sub-card interface, the sub-card will send a slot status signal through the corresponding pin on the sub-card interface (the pin for transmitting the slot status signal), and then the slot status signal is transmitted to the main control chip via the low-speed bus interface or the high-speed bus interface. Then the main control chip can know whether a sub-card is plugged into each sub-card interface, and can perform corresponding operations when monitoring the slot status signal, such as reporting an insertion event message (indicating an event of inserting a sub-card into the sub-card interface) to the host computer, so as to realize efficient monitoring of the slot status of the sub-card interface.

[0096] In one possible implementation, the low-speed bus interface is configured with a plurality of pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting synchronization signals;

[0097] On the backplane, a pin for transmitting a synchronization signal is connected to a synchronization signal pin of a daughter card interface;

[0098] On the main card, each pin for transmitting synchronization signals is connected to the main control chip slot.

[0099] like Figure 1 As shown, a pin for transmitting a synchronization signal is connected to a daughter card interface. Accordingly, the daughter card interface is also configured with a pin for transmitting a synchronization signal, that is, Figure 1 The synchronization signal pin in.

[0100] It is understandable that during the communication between the main card and multiple sub-cards, it may be necessary to maintain the synchronization of communication between the main card and multiple sub-cards. In order to meet the requirements of this business scenario, the main card transmits the synchronization signal to each sub-card through the corresponding pins (pins for transmitting synchronization signals) configured on the low-speed bus interface or the high-speed bus interface, thereby maintaining communication synchronization between the main card and multiple sub-cards.

[0101] Alternatively, as Figure 1 As shown, the daughter card interface is configured with a power pin for supplying power to the daughter card.

[0102] In one possible implementation, on the backplane, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector (a connector adapted to transmit high-speed bus signals, such as a PCIe slot, an ADF connector, or an HM connector).

[0103] On the main card, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector;

[0104] The high-speed bus connector on the backplane is a male or female connector, and correspondingly, the high-speed bus connector on the main card is a female or male connector.

[0105] It is worth noting that in the prior art, low-speed bus interfaces and high-speed bus interfaces are generally configured with different types of connectors. For example, when the low-speed bus is an SPI bus and the high-speed bus is a PCIe bus, the SPI bus interface is configured as a plug-in connector (e.g., a header connector), and the PCIe bus interface is configured as a PCIe slot.

[0106] In the board provided in the embodiment of the present application, a low-speed bus interface and a high-speed bus interface are configured on the main card, and a low-speed bus interface and a high-speed bus interface are also configured on the backplane. If the low-speed bus interface and the high-speed bus interface use different types of connectors, then in the process of plugging the main card into the backplane or in the process of unplugging the main card from the backplane, the force applied to the low-speed bus interface and the force applied to the high-speed bus interface are different, and the force between different interfaces is uneven, resulting in a shortened service life of the interface.

[0107] To overcome the drawback of uneven force between interfaces, the low-speed bus interface and the high-speed bus interface can be configured with the same high-speed bus connector. For example, if the high-speed bus is a PCIe bus, the high-speed bus connector can include an ADF connector and a HM connector. The ADF connector is used to transmit bus signals, and the HM connector is used to transmit other signals (such as synchronization signals or slot status signals).

[0108] HM connectors, also known as Hard Metric connectors, are commonly used in industrial applications, particularly those related to the PCI bus standard for computers. HM connectors typically have a centerline spacing of 2mm and are used for circuit board-to-circuit board connections.

[0109] ADF (Advanced Differential Fabric) connector is a high-speed differential connector that supports high-speed data transmission and has a high-density signal line layout.

[0110] Since the high-speed bus connector is adaptable to transmitting high-speed bus signals, it is also compatible with transmitting low-speed bus signals. Therefore, during the process of inserting or removing the main card into or from the backplane, since the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector, the number, size, and arrangement of pins on the low-speed bus interface remain the same as those on the high-speed bus interface. This results in the same force applied to the low-speed bus interface as to the high-speed bus interface, ensuring uniform force across different interfaces. This effectively prevents uneven force across different interfaces from shortening their service life.

[0111] In addition, the low-speed bus interface and the high-speed bus interface are configured with the same high-speed bus connector, which can unify the interface type between the main card and the backplane and improve production and maintenance efficiency.

[0112] The present application also provides a signal generator comprising: a daughter card and any of the above-mentioned circuit boards. The signal generator may include one or more daughter cards, which are plugged into a daughter card interface of the circuit board. The signal generator may specifically be a pattern generator (PG) or semiconductor testing equipment.

[0113] It should be understood that expressions such as "include" and "may include" used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "include" and / or "have" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0114] In addition, in the embodiments of the present application, the mathematical concepts mentioned include symmetry, equality, parallelism, and perpendicularity. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense. A small amount of deviation is allowed, and it is possible to be approximately symmetric, approximately equal, approximately parallel, or approximately perpendicular. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0115] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A circuit board card, characterized in that: include: Main card and back panel; The backplane is equipped with a low-speed bus interface for connecting to the main card, a high-speed bus interface for connecting to the main card, a bus expansion interface for connecting to the bus expansion board, and multiple daughter card interfaces. The communication rate of the high-speed bus is higher than that of the low-speed bus. The main card is configured with a main control chip slot, a low-speed bus interface for docking the backplane, and a high-speed bus interface for docking the backplane, the main control chip slot is connected to the low-speed bus interface, and the main control chip slot is connected to the high-speed bus interface; The low-speed bus interface is configured with multiple groups of low-speed bus pins, one group of low-speed bus pins is used to transmit multiple low-speed bus signals, and one group of low-speed bus pins in the low-speed bus interface is correspondingly connected to a group of low-speed bus pins in a daughter card interface; The high-speed bus interface is configured with at least one set of high-speed bus pins, and the set of high-speed bus pins is used to transmit one high-speed bus signal; In the case where the main card and the daughter card communicate using a high-speed bus, a bus expansion board is plugged into the bus expansion interface, and the bus expansion board is configured with at least one high-speed bus switching chip. The same group of high-speed bus pins in the high-speed bus interface are connected to the same high-speed bus switching chip. The high-speed bus switching chip is used to expand each group of high-speed bus pins in the high-speed bus interface into multiple groups of high-speed bus pins. Each group of high-speed bus pins in the multiple groups of high-speed bus pins obtained after expansion is connected to a corresponding group of high-speed bus pins in a daughter card interface.

2. The circuit board card according to claim 1, wherein: The main control chip slot is provided with a main control chip, the main control chip is provided with a low-speed bus, and the low-speed bus of the main control chip is connected to the low-speed bus interface.

3. The circuit board card according to claim 1, wherein: The main control chip slot is provided with a main control chip, the main control chip is provided with a high-speed bus, and the high-speed bus of the main control chip is connected to the high-speed bus interface.

4. The circuit board card according to claim 2 or 3, characterized in that: The main control chip is FPGA or MCU.

5. The circuit board card according to claim 1, wherein: On the backplane, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector; On the main card, the low-speed bus interface and the high-speed bus interface use the same high-speed bus connector; The high-speed bus connector on the backplane is a male socket or a female socket, and correspondingly, the high-speed bus connector on the main card is a female socket or a male socket.

6. The circuit board card according to claim 1, wherein: The main card includes: a main control chip carrier board and a low-speed bus interface board; The main control chip carrier is configured with a main control chip slot, a high-speed bus interface for docking with a backplane, and a low-speed bus slot for carrying the low-speed bus interface board in a stacked manner; The low-speed bus interface board is provided with a low-speed bus interface for docking with the backplane; The main control chip slot is connected to the low-speed bus interface through the low-speed bus slot, and the main control chip slot is connected to the high-speed bus interface.

7. The circuit board card according to claim 1, wherein: The low-speed bus interface is configured with a plurality of pins for transmitting slot status signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting slot status signals; On the backplane, a pin for transmitting a slot status signal is correspondingly connected to a slot status signal pin of a daughter card interface to receive the slot status signal sent by the daughter card; On the main card, each pin for transmitting a slot status signal is connected to the main control chip slot.

8. The circuit board card according to claim 1, wherein: The low-speed bus interface is configured with a plurality of pins for transmitting synchronization signals, and / or the high-speed bus interface is configured with a plurality of pins for transmitting synchronization signals; On the backplane, a pin for transmitting a synchronization signal is correspondingly connected to a synchronization signal pin of a daughter card interface; On the main card, each pin for transmitting a synchronization signal is connected to a main control chip slot.

9. The circuit board card according to any one of claims 1-3 or any one of claims 5-8, characterized in that: The bus expansion interface and the bus expansion board are provided with a first high-speed buckle connector, and each group of high-speed bus pins in the high-speed bus interface of the backplane is connected to the high-speed bus switching chip through the first high-speed buckle connector; The bus expansion interface and the bus expansion board are provided with a second high-speed snap connector, and the high-speed bus pins in each daughter card interface are connected to the high-speed bus switching chip through the second high-speed snap connector.

10. A signal generator, characterized in that: include: A daughter card and a circuit board card as claimed in any one of claims 1 to 9.

Images