Semiconductor chip testing method and system

Abstract

The present invention relates to the technical field of integrated circuit design and packaging, and discloses a semiconductor chip testing method and system. The chip testing method is applied to testing equipment, and specifically includes the following steps: S101: receiving a test request sent by a preceding manufacturing end, the test request carrying the chip feature data to be tested and the file format of the feature data; S102: identifying the file format of the chip feature data to be tested, and inputting the chip feature data into a preset content recognition model for identification, while performing test processing on the chip to be tested. The present invention compares the preset feature data with the current feature data value tested, thereby determining the deficiencies and defects of the tested semiconductor chip. Automated testing solves the problem of insufficient efficiency and excessive manpower consumption in the semi-automatic manual chip testing process, making the test more accurate and stable, and the tested data more efficient and accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and packaging, and in particular to a semiconductor chip testing method and system. Background Art

[0002] With the development of microelectronics technology, the application scope of semiconductor chips is becoming more and more extensive. From daily life to professional fields, semiconductor chip-related products have penetrated into all aspects of people's lives.

[0003] During semiconductor chip manufacturing, after packaging, the chips must be tested to determine if they are qualified. Traditionally, chips are manually placed in a test fixture and, after testing, removed and placed on trays corresponding to the test level. This process inevitably causes damage or contamination to the products during handling, and there's also the possibility of the products being placed on the wrong trays after testing. Consequently, chip testing carries risks to chip quality, is inefficient, and requires excessive manpower. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor chip testing method and system. The automated testing solves the problem of insufficient efficiency and excessive manpower consumption in the semi-automatic manual chip testing process, and aims to solve the problem of defective products being outflowed due to errors in the existing technology causing chips to be placed in the wrong grade tray.

[0005] The present invention is implemented as follows: a semiconductor chip testing method is applied to a testing device and specifically comprises the following steps:

[0006] S101: Receive a test request sent by a previous manufacturing end, wherein the test request carries characteristic data of a chip to be tested and a file format of the characteristic data;

[0007] S102: Identify the file format of the chip feature data to be tested, input the chip feature data into a preset content recognition model for recognition, and perform test processing on the chip to be tested;

[0008] S103: Obtaining a content recognition result output by the content recognition model based on the chip feature data, and obtaining, from the content recognition result, a preset feature data value of the chip feature data and a current feature data value obtained after the chip to be tested is tested;

[0009] S104: generating a preset correlation index generation model curve according to the preset characteristic data value, wherein the preset correlation index generation model curve includes a physical property correlation value and a communication property correlation value of the semiconductor chip;

[0010] S105: Obtain the current feature data value, and insert the current feature data value into the preset correlation index generation model curve, determine the deviation feature of the tested current feature data value and the preset correlation index generation model curve, if the deviation feature is within the set threshold range, establish a verification mark on the semiconductor chip according to the pre-established corresponding identification relationship between the semiconductor chip and the test equipment.

[0011] Furthermore, in S101, receiving a test request sent by a previous manufacturing end includes:

[0012] receiving a connection request sent by a previous manufacturing end through a preset network, wherein the connection request is used to request to establish a connection with the test device;

[0013] Detecting the current process identifier of the preceding manufacturing end and determining the content of the test required for the current process identifier;

[0014] Identify the chips to be tested that are already in place, and perform tests based on the content of the tests required by the current process identification. After the test is completed, the obtained test data is transmitted to the previous manufacturing end where the connection is established.

[0015] Furthermore, the preset network includes one or a combination of 3G network, 4G network, 5G network, and WIFI network.

[0016] Furthermore, in S102, identifying the file format of the chip feature data to be tested includes:

[0017] Acquire the characteristic data of the chip to be tested, and perform a first feature recognition reading on the characteristic data of the chip to be tested to determine the current character format;

[0018] Obtaining a translation model in the current character format, inputting the chip feature data to be tested into the translation model in the current character format to translate the data content, thereby obtaining current translation feature data;

[0019] The current translation feature data is obtained, and feature recognition reading is performed a second time on the current translation feature data to determine the content of the feature data of the chip to be tested.

[0020] Furthermore, in S102, the chip feature data is input into a preset content recognition model for recognition, including:

[0021] Acquire multiple content recognition models, and sort the multiple content recognition models in descending order of recognition values;

[0022] The content text of the chip feature data is obtained, and the chip feature data is input into the content recognition model ranked first.

[0023] Furthermore, in S103, the preset characteristic data value of the chip characteristic data is the ideal characteristic data of the semiconductor chip to be processed. After obtaining the ideal characteristic data of the semiconductor chip, the testing equipment tests the semiconductor chip to obtain the current characteristic data value, completes the comparison between the ideal characteristic data and the current characteristic data value, and obtains the deviation characteristic.

[0024] Furthermore, in S105, the current characteristic data value is obtained and inserted into a preset correlation index generation model curve, including:

[0025] Obtaining a preset correlation index generated by a preset characteristic data value to generate a model curve;

[0026] The current characteristic data value is obtained, and according to the corresponding relationship between the physical attribute correlation value and the communication attribute correlation value of the current characteristic data value, a plurality of discrete points of the current characteristic data value are obtained in the correlation index generation model curve;

[0027] The current feature data value discrete points are linked to ensure that the slope of the linked current feature data value discrete points is close to the correlation index generation model curve.

[0028] Compared with the prior art, the semiconductor chip testing method and system provided by the present invention have the following beneficial effects:

[0029] 1. Semi-finished product testing can be performed on each process of semiconductor chips. First, the testing equipment establishes a connection with the upstream manufacturing end to obtain the preset characteristic data of the chip to be tested. Then, the chip to be tested is tested and processed. The preset characteristic data is compared with the current characteristic data value tested to determine the deficiencies and defects of the tested semiconductor chip. Automated testing solves the problems of insufficient efficiency and excessive manpower consumption in the semi-automatic manual chip testing process, and the possibility of defective products being discharged due to errors such as chips being placed in the wrong grade tray. This makes the test more accurate and stable, and the test data more efficient and accurate.

[0030] 2. By performing functional and stability tests on packaged chips, qualified finished products are selected, and they are graded, recorded, and counted according to device performance. Under the premise of ensuring the cleanliness and stability of product handling, the chips are more efficiently moved to the test station and the corresponding test grade target tray to ensure that the functional and performance indicators of the chips leaving the factory meet the design specifications, thereby realizing the control and management of circuit production.

[0031] A semiconductor chip testing system is used to perform the above-mentioned testing method, and the testing system includes:

[0032] A startup module is used to start the test equipment, and after receiving the signal, the test equipment enters the stage of waiting for the previous manufacturing end to send a connection and receive;

[0033] A connection module, used for establishing a connection between the test equipment and the preceding manufacturing end and transmitting chip feature data;

[0034] Model recognition module, used to input chip feature data into a preset content recognition model for recognition;

[0035] A generation module, configured to determine a correlation value between a physical property and a communication property of the semiconductor chip, and generate a preset correlation index generation model curve based on preset characteristic data values;

[0036] The comparison output module is used to insert the current characteristic data value into the preset correlation index generation model curve to determine the deviation characteristics between the tested current characteristic data value and the preset correlation index generation model curve.

[0037] Specifically, the model recognition module includes:

[0038] An acquisition unit, used for acquiring characteristic data of the chip to be tested;

[0039] A first recognition unit is used to perform a first feature recognition reading on the feature data of the chip to be tested to determine the current character format;

[0040] The translation model unit is used to input the chip feature data to be tested into the translation model of the current character format to translate the data content to obtain the current translation feature data;

[0041] The second recognition unit is used to perform a second feature recognition reading on the current translated feature data to determine the content of the feature data of the chip to be tested.

[0042] Specifically, the comparison output module includes:

[0043] A curve model generating unit, configured to generate a preset correlation index generating model curve for a preset characteristic data value;

[0044] A discrete point marking unit is used to obtain a plurality of discrete points of the current characteristic data value in the correlation index generation model curve according to the corresponding relationship between the physical attribute correlation value and the communication attribute correlation value of the current characteristic data value;

[0045] The discrete point association unit is used to link the current feature data value discrete points and ensure that the slope of the linked current feature data value discrete points is close to the correlation index generation model curve. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1This is a schematic flow chart of the semiconductor chip testing method proposed by the present invention;

[0047] Figure 2 This is a schematic block diagram of the process of receiving a test request sent by a previous manufacturing end in the semiconductor chip testing method proposed by the present invention;

[0048] Figure 3 This is a schematic structural diagram of the semiconductor chip testing system proposed by the present invention;

[0049] Figure 4 This is a structural diagram of the model recognition module in the semiconductor chip testing system proposed by the present invention;

[0050] Figure 5 This is a structural diagram of the comparison output module in the semiconductor chip testing system proposed by the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0052] The implementation of the present invention is described in detail below with reference to specific embodiments.

[0053] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "up", "down", "left", "right", etc. indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0054] Reference Figure 1-2 As shown, the semiconductor chip testing method is applied to the testing equipment and specifically includes the following steps:

[0055] S101: Receive a test request sent by a previous manufacturing end, the test request carrying feature data of a chip to be tested and a file format of the feature data;

[0056] Receive the test request sent by the previous manufacturing end, including:

[0057] Receive a connection request sent by a previous manufacturing end through a preset network, the connection request being used to request establishment of a connection with a test device;

[0058] Detect the current process identification of the previous manufacturing end and determine the content that needs to be tested for the current process identification;

[0059] Identify the chips to be tested that are already in place, perform tests based on the content of the tests required by the current process identification, and after the tests are completed, transmit the acquired test data to the previous manufacturing end with which the connection is established;

[0060] S102: Identify the file format of the chip feature data to be tested, input the chip feature data into a preset content recognition model for recognition, and perform test processing on the chip to be tested;

[0061] Identify the file format of the chip feature data to be tested, including:

[0062] Acquire the characteristic data of the chip to be tested, and perform a first feature recognition reading on the characteristic data of the chip to be tested to determine the current character format;

[0063] Obtaining a translation model in the current character format, inputting the chip feature data to be tested into the translation model in the current character format to translate the data content, thereby obtaining current translation feature data;

[0064] Acquire current translation feature data, and perform a second feature recognition read on the current translation feature data to determine the content of the feature data of the chip to be tested;

[0065] S103: Obtaining a content recognition result output by the content recognition model based on the chip feature data, and obtaining, in the content recognition result, a preset feature data value of the chip feature data and a current feature data value obtained after the chip to be tested is tested;

[0066] S104: generating a preset correlation index generation model curve according to the preset characteristic data value, wherein the preset correlation index generation model curve includes a physical property correlation value and a communication property correlation value of the semiconductor chip;

[0067] S105: Obtain the current feature data value, and insert the current feature data value into the preset correlation index generation model curve, determine the deviation feature of the tested current feature data value and the preset correlation index generation model curve, if the deviation feature is within the set threshold range, establish a verification mark on the semiconductor chip according to the pre-established corresponding identification relationship between the semiconductor chip and the test equipment, and perform semi-finished product testing on each process of the semiconductor chip. First, the test equipment establishes a connection with the previous manufacturing end to obtain the preset feature data of the chip to be tested, and then the chip to be tested is tested and processed, and the preset feature data is compared with the tested current feature data value to determine the deficiencies and defects of the tested semiconductor chip. Automated testing solves the problems of insufficient efficiency and excessive manpower consumption in the semi-automatic manual chip testing process, and there may be problems such as chips being placed in the wrong grade tray due to errors, resulting in the outflow of defective products.

[0068] In S101 of this embodiment, the preset network includes one of a 3G network, a 4G network, a 5G network, and a WIFI network, or a combination thereof.

[0069] In S102 of this embodiment, the chip feature data is input into a preset content recognition model for recognition, including:

[0070] Obtain multiple content recognition models, and sort the multiple content recognition models in descending order of recognition values;

[0071] The content text of the chip feature data is obtained, and the chip feature data is input into the first-ranked content recognition model.

[0072] In S103 of this embodiment, the preset characteristic data value of the chip characteristic data is the ideal characteristic data of the semiconductor chip to be processed. After obtaining the ideal characteristic data of the semiconductor chip, the testing equipment tests the semiconductor chip to obtain the current characteristic data value, completes the comparison between the ideal characteristic data and the current characteristic data value, and obtains the deviation feature.

[0073] In S105 of this embodiment, the current feature data value is obtained and inserted into the preset correlation index generation model curve, including:

[0074] Obtaining a preset correlation index generated by a preset characteristic data value to generate a model curve;

[0075] The current characteristic data value is obtained, and according to the corresponding relationship between the physical attribute correlation value and the communication attribute correlation value of the current characteristic data value, a plurality of discrete points of the current characteristic data value are obtained in the correlation index generation model curve;

[0076] Link the current characteristic data value discrete points to ensure that the slope of the linked current characteristic data value discrete points is close to the correlation index generation model curve. By performing functional and stability tests on the packaged chips, qualified finished products are selected, and they are graded, recorded and counted according to the device performance. Under the premise of ensuring the cleanliness and stability of product transportation, the chips are more efficiently moved to the test station and the corresponding test grade target tray to ensure that the functional and performance indicators of the factory chips meet the design specifications, thereby realizing the control and management of circuit production.

[0077] Reference Figure 3-5 As shown, a semiconductor chip testing system is used to perform the above-mentioned testing method. The testing system includes: a startup module for starting the test equipment, and the test equipment enters the stage of sending and connecting to the previous manufacturing end after receiving the signal; a connection module for establishing a connection between the test equipment and the previous manufacturing end and transmitting chip feature data; a model recognition module for inputting the chip feature data into a preset content recognition model for recognition; a generation module for determining the physical property correlation value and the communication property correlation value of the semiconductor chip, and generating a preset correlation index generation model curve based on the preset feature data value; a comparison output module for inserting the current feature data value into the preset correlation index generation model curve, and determining the deviation characteristics between the current feature data value under test and the preset correlation index generation model curve. By performing functional and stability tests on the packaged chips, qualified finished products are selected, and they are graded according to the device performance and recorded and counted. Under the premise of ensuring the cleanliness and stability of the product handling, the chips are more efficiently transferred to the test station and the corresponding test grade target tray, ensuring that the function and performance indicators of the shipped chips meet the design specifications, thereby realizing the control and management of circuit production.

[0078] The specific working principle of the equipment is: the chip test target disc is transported to the lifting platform through the assembly line, the QR code on the disc is obtained and recorded by an industrial camera, and the disc to be tested is carried to one of the multiple loading positions through the lifting platform. The remaining loading positions and the empty discs that have been tested are repeated until there are discs at each loading position and unloading position. When there is a disc to be tested ready at any loading position, the material picking nozzle moves to the top of the chip, picks up the product through vacuum and places it on the shuttle. The shuttle moves to the vicinity of an idle test station, and the test nozzle takes the product from the shuttle and places it inside the test station. The test station starts testing, and the shuttle and the test nozzle The nozzle moves to the vicinity of the test station where the test is completed, takes out the tested product and places it on the shuttle. The shuttle moves back to the vicinity of the test tray, places the tested products in different unloading trays according to their grades, and then takes the chip to be tested and repeats the above actions. By performing functional and stability tests on the packaged chips, qualified finished products are selected, and they are graded according to the device performance and recorded and counted. Under the premise of ensuring the cleanliness and stability of product transportation, the chips are more efficiently transferred to the test station and the corresponding test grade target tray to ensure that the functional and performance indicators of the chips leaving the factory meet the design specifications, thereby realizing the control and management of circuit production.

[0079] In this embodiment, the model recognition module includes: an acquisition unit for acquiring the characteristic data of the chip to be tested; a first recognition unit for performing a first feature recognition reading on the characteristic data of the chip to be tested to determine the current character format; a translation model unit for inputting the characteristic data of the chip to be tested into the translation model of the current character format for data content translation to obtain the current translation characteristic data; a second recognition unit for performing a second feature recognition reading on the current translation characteristic data to determine the content of the characteristic data of the chip to be tested. Semi-finished product testing can be performed on each process of the semiconductor chip. First, the testing equipment establishes a connection with the previous manufacturing end to obtain the preset characteristic data of the chip to be tested, and then the chip to be tested is tested and processed. The preset characteristic data is compared with the current characteristic data value tested to determine the deficiencies and defects of the tested semiconductor chip.

[0080] In this embodiment, the comparison output module includes: a curve model generation unit, which is used to generate a preset correlation index generation model curve for the preset characteristic data value; a discrete point marking unit, which is used to obtain multiple current characteristic data value discrete points in the correlation index generation model curve based on the correspondence between the physical property correlation value and the communication property correlation value of the current characteristic data value; a discrete point association unit, which is used to link the current characteristic data value discrete points and ensure that the slope of the linked current characteristic data value discrete points is similar to the correlation index generation model curve. Automated testing solves the problems of insufficient efficiency and excessive manpower consumption in the semi-automatic manual chip testing process, and the possible outflow of defective products due to chips being placed in the wrong grade tray due to errors, making the test more accurate and stable, and the tested data more efficient and accurate.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor chip testing method, characterized in that: Applied to test equipment, specifically including the following steps: S101: Receive a test request sent by a previous manufacturing end, wherein the test request carries characteristic data of a chip to be tested and a file format of the characteristic data; Receiving a test request sent by a preceding manufacturing end includes: receiving a connection request sent by a previous manufacturing end through a preset network, wherein the connection request is used to request to establish a connection with the test device; Detecting the current process identifier of the preceding manufacturing end and determining the content of the test required for the current process identifier; Identify the chips to be tested that are already in place, perform tests based on the content of the tests required by the current process identification, and after the tests are completed, transmit the acquired test data to the previous manufacturing end with which the connection is established; S102: Identify the file format of the chip feature data to be tested, input the chip feature data into a preset content recognition model for recognition, and perform test processing on the chip to be tested; The step of identifying the file format of the chip feature data to be tested includes: Acquire the characteristic data of the chip to be tested, and perform a first feature recognition reading on the characteristic data of the chip to be tested to determine the current character format; Obtaining a translation model in the current character format, inputting the chip feature data to be tested into the translation model in the current character format to translate the data content, thereby obtaining current translation feature data; Acquire current translation feature data, and perform a second feature recognition read on the current translation feature data to determine the content of the feature data of the chip to be tested; S103: Obtaining a content recognition result output by the content recognition model based on the chip feature data, and obtaining, from the content recognition result, a preset feature data value of the chip feature data and a current feature data value obtained after the chip to be tested is tested; The preset characteristic data value of the chip characteristic data is the ideal characteristic data of the semiconductor chip to be processed. After obtaining the ideal characteristic data of the semiconductor chip, the testing device tests the semiconductor chip to obtain the current characteristic data value, compares the ideal characteristic data with the current characteristic data value, and obtains the deviation feature. S104: generating a preset correlation index generation model curve according to the preset characteristic data value, wherein the preset correlation index generation model curve includes a physical property correlation value and a communication property correlation value of the semiconductor chip; S105: Obtaining a current feature data value, inserting the current feature data value into a preset correlation index generation model curve, determining a deviation feature between the tested current feature data value and the preset correlation index generation model curve, and if the deviation feature is within a set threshold range, establishing a verification mark on the semiconductor chip according to a pre-established corresponding mark relationship between the semiconductor chip and the test equipment; The current characteristic data value is obtained and inserted into a preset correlation index generation model curve, including: Obtaining a preset correlation index generated by a preset characteristic data value to generate a model curve; The current characteristic data value is obtained, and according to the corresponding relationship between the physical attribute correlation value and the communication attribute correlation value of the current characteristic data value, a plurality of discrete points of the current characteristic data value are obtained in the correlation index generation model curve; The current feature data value discrete points are linked to ensure that the slope of the linked current feature data value discrete points is close to the correlation index generation model curve.

2. The semiconductor chip testing method according to claim 1, wherein: The preset network includes one of 3G network, 4G network, 5G network, WIFI network or a combination thereof.

3. The semiconductor chip testing method according to claim 2, wherein: In S102, the chip feature data is input into a preset content recognition model for recognition, including: Acquire multiple content recognition models, and sort the multiple content recognition models in descending order of recognition values; The content text of the chip feature data is obtained, and the chip feature data is input into the content recognition model ranked first.

4. A semiconductor chip testing system, characterized in that: For performing the test method according to any one of claims 1 to 3, the test system comprises: A startup module is used to start the test equipment, and after receiving the signal, the test equipment enters the stage of waiting for the previous manufacturing end to send a connection and receive; A connection module, used for establishing a connection between the test equipment and the preceding manufacturing end and transmitting chip feature data; Model recognition module, used to input chip feature data into a preset content recognition model for recognition; A generation module, configured to determine a correlation value between a physical property and a communication property of the semiconductor chip, and generate a preset correlation index generation model curve based on preset characteristic data values; The comparison output module is used to insert the current characteristic data value into the preset correlation index generation model curve to determine the deviation characteristics between the tested current characteristic data value and the preset correlation index generation model curve.

5. The semiconductor chip testing system according to claim 4, wherein: The model recognition module includes: An acquisition unit, used for acquiring characteristic data of the chip to be tested; A first recognition unit is used to perform a first feature recognition reading on the feature data of the chip to be tested to determine the current character format; The translation model unit is used to input the chip feature data to be tested into the translation model of the current character format to translate the data content to obtain the current translation feature data; The second recognition unit is used to perform a second feature recognition reading on the current translated feature data to determine the content of the feature data of the chip to be tested.

6. The semiconductor chip testing system according to claim 5, wherein: The comparison output module includes: A curve model generating unit, configured to generate a preset correlation index generating model curve for a preset characteristic data value; A discrete point marking unit is used to obtain a plurality of discrete points of the current characteristic data value in the correlation index generation model curve according to the corresponding relationship between the physical attribute correlation value and the communication attribute correlation value of the current characteristic data value; The discrete point association unit is used to link the current feature data value discrete points and ensure that the slope of the linked current feature data value discrete points is close to the correlation index generation model curve.

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