A low-complexity serial port read-write register processing method and device

Abstract

The present invention discloses a low-complexity serial port read-write register processing method and device in the field of data communication, which is applied to a pure PL platform without PS. The method includes: an FPGA chip performs serial-to-parallel conversion on serial data to obtain parallel data; caches the parallel data according to the character type; determines whether it is a write / read data state according to the operation character; if it is a write data state, the address character and the data character are decoded from ASCII code to hexadecimal code; according to the decoded address character, the decoded data character is assigned to the register corresponding to the corresponding address; if it is a read data state, the address character is decoded from ASCII code to hexadecimal code; according to the decoded address character, the register corresponding to the address is assigned to the data character to be sent; the data character to be sent is decoded from hexadecimal code to ASCII code, and then the parallel-to-serial conversion is obtained to obtain the serial data to be sent, and the data character to be sent is sent. The present invention can realize the function of serial port reading and writing PL registers.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a low-complexity serial port read-write register processing method and device. Background Art

[0002] In some specific development requirements, there are almost no functions that require PS participation. If you continue to select chips with PS, it will be a waste of resources and will not meet the economic principle in terms of cost. At the same time, the register function of FPGA plays a pivotal role in both early debugging and later problem location. Therefore, on a pure PL platform without PS, it is particularly important to develop a register system that is both simple and can meet the needs of technicians in debugging and problem location. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a low-complexity serial port reading and writing register processing method and device for realizing the function of serial port reading and writing PL registers on a PL platform without PS by connecting the serial port to a host computer and carrying an FPGA.

[0004] To achieve the above object, the present invention is implemented by adopting the following technical solutions:

[0005] In a first aspect, the present invention provides a low-complexity serial port read and write register processing method, which is applied to a pure PL platform without a PS, wherein the pure PL platform comprises a host computer, a UART chip and an FPGA chip connected in sequence, wherein the read and write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip; the processing method comprises:

[0006] In response to receiving the serial data corresponding to the read / write instruction, the FPGA chip performs serial-to-parallel conversion on the serial data to obtain parallel data;

[0007] caching the parallel data according to character types, wherein the character types include operation characters, address characters, and data characters;

[0008] Determine whether it is a write data state or a read data state according to the operation character;

[0009] If the operation character is in the data writing state, the address character and the data character are decoded from ASCII code to hexadecimal code;

[0010] Set the write data enable to a high level, and assign the decoded data character to the register corresponding to the corresponding address according to the decoded address character;

[0011] If the operation character is in the data reading state, the address character is decoded from ASCII code to hexadecimal code;

[0012] Set the read data enable to a high level, and assign the register corresponding to the address to the data character to be sent according to the decoded address character;

[0013] The data characters to be sent are decoded from hexadecimal codes to ASCII codes, and the decoded data characters to be sent are converted from parallel to serial to obtain serial data to be sent, and then sent.

[0014] Optionally, the serial data corresponding to the read and write instructions includes:

[0015] Write operation: wrreg xxxx yyyyyyyy, among which, represents a space character, wrreg represents an operation character, xxxx represents an address character, which is defined as 16 bits, and yyyyyyyy represents a data character, which is defined as 32 bits;

[0016] Read operation: rdreg xxxx, where rdreg represents the operation character.

[0017] Optionally, the serial-to-parallel conversion includes:

[0018] Setting a first counter and a second counter;

[0019] The first counter starts counting when the start bit of the serial port of the UART chip is captured and set to a low level, and performs a clearing operation when the coefficient value is subtracted by 1, and then counts in a loop;

[0020] Whenever the first counter counts to the coefficient value minus 1, the second counter increases by 1, and when the second counter counts to 9, a clearing operation is performed and counting is cyclic;

[0021] When the count values ​​of the second counter are 1 to 8 respectively, the serial data is sequentially placed into the 8-bit buffer data according to the principle of putting the advanced data into the lower LSB, thereby completing the conversion of the serial data into parallel data;

[0022] The acquisition of the coefficient value includes:

[0023] Use 1s / baud rate to calculate the time required to transmit 1 bit of data at the current baud rate;

[0024] The required number of unit clocks for transmitting 1 bit of data is obtained by dividing the required time by the unit clock period, and the number of unit clocks is used as the coefficient value.

[0025] Optionally, caching the parallel data according to character type includes:

[0026] Setting a third counter;

[0027] Whenever the second counter counts to 9, the third counter increases by 1, and when the third counter counts to N, a clearing operation is performed and counting is cyclic;

[0028] When the parallel data is in the write data state, N=18:

[0029] When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into 48-bit operation characters in order from high to low;

[0030] When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into 32-bit address characters in order from high to low;

[0031] When the count value of the third counter is 10 to 18 respectively, the parallel data is sequentially cached into 72-bit data characters in order from high to low;

[0032] When the parallel data is in the read data state, N=9:

[0033] When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into 48-bit operation characters in order from high to low;

[0034] When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into the 32-bit address characters in order from high to low.

[0035] Optionally, when the parallel data is in a write data state or a read data state, if any character of the operation character is not the ASCII code value it represents, the third counter is reset.

[0036] In a second aspect, the present invention provides a low-complexity serial port read-write register processing device, which is applied to a pure PL platform without a PS, wherein the pure PL platform comprises a host computer, a UART chip and an FPGA chip connected in sequence, wherein the read-write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip; the processing device comprises:

[0037] The instruction processing module is configured to, in response to receiving serial data corresponding to the read / write instruction, convert the serial data into parallel data by the FPGA chip;

[0038] A classification cache module is configured to cache the parallel data according to character types, wherein the character types include operation characters, address characters, and data characters;

[0039] A read / write determination module, configured to determine whether it is a write data state or a read data state according to the operation character;

[0040] The write operation module is configured to decode the address character and the data character from ASCII code to hexadecimal code if the operation character is in the write data state; set the write data enable to a high level, and assign the decoded data character to a register corresponding to the corresponding address according to the decoded address character;

[0041] The read operation module is configured to decode the address character from ASCII code to hexadecimal code if the operation character is in the read data state; set the read data enable to a high level, and assign the register corresponding to the address to the data character to be sent according to the decoded address character; decode the data character to be sent from hexadecimal code to ASCII code, convert the decoded data character to be sent from parallel to serial to obtain the serial data to be sent, and send it.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] The present invention provides a low-complexity processing method and device for serial port reading and writing registers. 1) It is applied on a PL platform without PS, and realizes the function of serial port reading and writing PL registers by connecting the serial port to the host computer and carrying FPGA, thereby replacing the method of PS reading and writing registers through the bus, reducing development costs. 2) When using the serial port to read and write PL registers, the present invention takes into account the adaptation of the baud rates of different serial ports to make the system more universal and compatible. 3) When using the serial port to read and write PL registers, the present invention reduces the system hang caused by misoperation and enhances the robustness of the system. 4) The present invention clearly displays the operation process by defining the operation characters, address characters and data characters of the read and write instructions, thereby reducing the complexity of the serial port read and write register system. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a system block diagram of a pure PL platform without PS provided by an embodiment of the present invention;

[0045] Figure 2 The present invention is a flowchart of a method for reading and writing a serial port register with low complexity provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0047] Embodiment 1:

[0048] like Figure 1 As shown, the present invention provides a low-complexity method for processing serial port read and write registers, which is applied to a pure PL platform without PS. The pure PL platform includes a host computer, a UART chip and an FPGA chip connected in sequence. The read and write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip.

[0049] like Figure 2 As shown, the processing method includes the following steps:

[0050] Step S1, in response to receiving serial data corresponding to a read / write instruction, the FPGA chip performs serial-to-parallel conversion on the serial data to obtain parallel data.

[0051] Specifically in this embodiment, the serial data corresponding to the read and write instructions includes:

[0052] Write operation: wrreg xxxx yyyyyyyy, among which, represents a space character, wrreg represents an operation character, xxxx represents an address character, which is defined as 16 bits, and yyyyyyyy represents a data character, which is defined as 32 bits;

[0053] Read operation: rdreg xxxx, where rdreg represents the operation character.

[0054] When performing a write operation, the operation character, address character, and data character need to be first transmitted to the UART chip through the USB interface of the host computer, and then transmitted to the FPGA chip through the serial port of the UART chip; when performing a read operation, only the operation character and address character need to be first transmitted to the UART chip through the USB interface of the host computer, and then transmitted to the FPGA chip through the serial port of the UART chip, and then the data signal returned by the FPGA chip is transmitted to the UART chip through the serial port, and then the UART chip transmits it back to the host computer through the serial port to USB. For the receiving end of the FPGA chip, there are data characters during the write operation, but no data characters during the read operation.

[0055] The serial data received from the serial port is converted into parallel data and cached. According to the relationship between the clock and the baud rate, the coefficient is set. This coefficient is adapted to the baud rate of different serial ports. Specifically, 1s / baud rate is used to calculate the time required to transmit 1 bit of data at the current baud rate; the required time is divided by the unit clock cycle to obtain the number of unit clocks required to transmit 1 bit of data, and the number of unit clocks is used as the coefficient value.

[0056] Serial-to-parallel conversion includes:

[0057] (1) Setting a first counter and a second counter;

[0058] (2) The first counter starts counting when the start bit of the serial port of the UART chip is captured and set to a low level. When the coefficient value is minus 1, the counter is cleared and the counting is repeated. The first counter is used to count the time required for the serial port to transmit 1 bit of data.

[0059] (3) Whenever the first counter counts to the coefficient value minus 1, the second counter increases by 1. When the second counter counts to 9, it performs a clearing operation and loops the count. The second counter is used to count the time required for the serial port to transmit a full frame of 10-bit data including the start bit, data bit and end bit.

[0060] (4) When the count value of the second counter is 1 to 8, the serial data is sequentially placed in the 8-bit buffer data according to the principle of placing the advanced data in the lower LSB, thus completing the conversion of the serial data into parallel data;

[0061] Step S2: caching the parallel data according to character types, where the character types include operation characters, address characters, and data characters.

[0062] Specifically in this embodiment, caching the parallel data according to the character type includes:

[0063] (1) Setting a third counter;

[0064] (2) Whenever the second counter counts to 9, the third counter increases by 1. When the third counter counts to N, it performs a clearing operation and loops the counting. When the parallel data is in the write data state or the read data state, if any character of the operation character (wrreg / rdreg) is not the ASCII code value it represents, the third counter is reset.

[0065] (3) When the parallel data is in the write data state, N=18:

[0066] When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into the 48-bit operation character in order from high to low;

[0067] When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into the 32-bit address characters in order from high to low;

[0068] When the count value of the third counter is 10 to 18 respectively, the parallel data is sequentially cached into 72-bit data characters in order from high to low;

[0069] (4) When the parallel data is in the read data state, N=9:

[0070] When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into the 48-bit operation character in order from high to low;

[0071] When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into the 32-bit address characters in order from high to low.

[0072] Step S3: Determine whether it is in the write data state or the read data state according to the operation character.

[0073] The instructions input by the host computer reach the FPGA chip through the USB and serial port. They are ASCII code streams. The operation characters for write operations are "wrreg" and "rdreg". The ASCII value represented by the w character is decimal 119, which is converted to hexadecimal 77; the ASCII value represented by the r character is decimal 114, which is converted to hexadecimal 72; the ASCII value represented by the e character is decimal 101, which is converted to hexadecimal 65; the ASCII value represented by the g character is decimal 103, which is converted to hexadecimal 67; the ASCII value represented by the d character is decimal 100, which is converted to hexadecimal 64; the ASCII value represented by the space character is decimal 32, which is converted to hexadecimal 20.

[0074] Whether the cached write operation character is 48'h777272656720, if yes, it is in the write data state; whether it is 48'h726472656720, if yes, it is in the read data state. 48'h represents a 48-bit hexadecimal number.

[0075] Step S4: If the operation character is in the data writing state, the address character and the data character are decoded from ASCII code to hexadecimal code.

[0076] The received ASCII code and the hexadecimal code inside the FPGA chip are not the same code element. Even if you know the specific character name corresponding to the ASCII code, you cannot perform logical operations inside the FPGA chip based on it, so you need to decode the ASCII code into hexadecimal code. Determine the hexadecimal code corresponding to each complete character in turn. When the ASCII code is determined to be hexadecimal 30, translate it into hexadecimal code 0; when the ASCII code is determined to be hexadecimal 31, translate it into hexadecimal code 1; when the ASCII code is determined to be hexadecimal 32, translate it into hexadecimal code 2; when the ASCII code is determined to be hexadecimal 33, translate it into hexadecimal code 3; when the ASCII code is determined to be hexadecimal 34, translate it into hexadecimal code 4; when the ASCII code is determined to be hexadecimal 35, translate it into hexadecimal code 5; when the ASCII code is determined to be hexadecimal 36, translate it into hexadecimal code 6; when the ASCII code is determined to be hexadecimal 37, translate it into hexadecimal code 7 ; When it is determined that the ASCII code is hexadecimal 38, translate it into hexadecimal code 8; when it is determined that the ASCII code is hexadecimal 39, translate it into hexadecimal code 9; when it is determined that the ASCII code is hexadecimal 61, translate it into hexadecimal code a; when it is determined that the ASCII code is hexadecimal 62, translate it into hexadecimal code b; when it is determined that the ASCII code is hexadecimal 63, translate it into hexadecimal code c; when it is determined that the ASCII code is hexadecimal 64, translate it into hexadecimal code d; when it is determined that the ASCII code is hexadecimal 65, translate it into hexadecimal code e; when it is determined that the ASCII code is hexadecimal 66, translate it into hexadecimal code f, and the decoding of the ASCII code to the hexadecimal code is completed.

[0077] Step S5, set the write data enable to a high level, and assign the decoded data character to the register corresponding to the corresponding address according to the decoded address character.

[0078] When the complete 19 characters in the write direction are transmitted, the write data enable signal is set to a high level, which means that the data can be assigned to the register of the corresponding address. According to the specific value of the address, the decoded data characters are assigned to the register of the corresponding address, and the write data operation is completed.

[0079] Step S6: If the operation character is in the data reading state, the address character is decoded from ASCII code to hexadecimal code.

[0080] Step S7, set the data read enable to a high level, and assign a register corresponding to the address to the data character to be sent according to the decoded address character.

[0081] When the complete 10 characters in the read direction are transmitted, the read data enable signal is set to a high level, which means that the specific 32-bit register value corresponding to the address can be assigned to different 8 data characters at the corresponding address, from low to high every 4 bits, and numbered from 1 to 8. At this time, the read data operation is completed.

[0082] Step S8, decode the data characters to be sent from hexadecimal code to ASCII code, convert the decoded data characters to be sent into parallel-serial code to obtain serial data to be sent, and send it.

[0083] The decoding of hexadecimal code to ASCII code includes:

[0084] When the hexadecimal code is judged to be 0, it is translated into ASCII code 30; when the hexadecimal code is judged to be 1, it is translated into ASCII code 31; when the hexadecimal code is judged to be 2, it is translated into ASCII code 32; when the hexadecimal code is judged to be 3, it is translated into ASCII code 33; when the hexadecimal code is judged to be 4, it is translated into ASCII code 34; when the hexadecimal code is judged to be 5, it is translated into ASCII code 35; when the hexadecimal code is judged to be 6, it is translated into ASCII code 36; when the hexadecimal code is judged to be 7, it is translated into ASCII code 37; When the hexadecimal code is judged to be 8, it is translated into ASCII code 38; when the hexadecimal code is judged to be 9, it is translated into ASCII code 39; when the hexadecimal code is judged to be a, it is translated into ASCII code 61; when the hexadecimal code is judged to be b, it is translated into ASCII code 62; when the hexadecimal code is judged to be c, it is translated into ASCII code 63; when the hexadecimal code is judged to be d, it is translated into ASCII code 64; when the hexadecimal code is judged to be e, it is translated into ASCII code 65; when the hexadecimal code is judged to be f, it is translated into ASCII code 66.

[0085] Parallel-to-serial conversion includes:

[0086] Set counter 1'. When the read data enable signal is captured and set to a high level, it starts counting. When the accumulated count reaches the coefficient value of step 2 minus 1, it performs a clearing operation and loops the count. This counter 1' is used to count the time required for the transmitter serial port to transmit 1 bit of data. Set counter 2'. Whenever counter 1' counts to the coefficient value minus 1, counter 2' adds 1. When counter 1' counts to the coefficient value minus 1 and the value of counter 2' is 9, it performs a clearing operation. This counter 2' is used to count the time required for the serial port to transmit a full frame of 10 bits of data including the start bit, data bit and end bit. Whenever counter 1' counts to the coefficient value minus 1, it processes data symbol 8 to data symbol 1 in order first. When the value of counter 2' is 0, a low level is output, which is the start bit. When the value of counter 2' is 1 to 8, bits 0 to 7 of the parallel data symbol are output serially in sequence according to the LSB principle. This is the data bit. When the value of counter 2' is 9, a high level is output, which is the end bit.

[0087] Finally, determine whether the read data value displayed by the host computer meets expectations. When the FPGA chip sends serial data to the UART chip through the serial port, the UART chip parses the data and the data reaches the host computer through the serial port to USB protocol. At this time, compare the received data from the FPGA displayed by the host computer and whether the register value is correct.

[0088] Embodiment 2:

[0089] Based on the processing method provided in the first embodiment, this embodiment provides a low-complexity serial port read and write register processing device, which is applied to a pure PL platform without PS. The pure PL platform includes a host computer, a UART chip and an FPGA chip connected in sequence. The read and write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip. The processing device includes:

[0090] The instruction processing module is configured to respond to receiving serial data corresponding to the read and write instructions, and the FPGA chip performs serial-to-parallel conversion on the serial data to obtain parallel data;

[0091] A classification cache module is configured to cache the parallel data according to character types, where the character types include operation characters, address characters, and data characters;

[0092] A read / write determination module is configured to determine whether the operation character is in a write data state or a read data state according to the operation character;

[0093] The write operation module is configured to decode the address character and the data character from ASCII code to hexadecimal code if the operation character is in the write data state; set the write data enable to a high level, and assign the decoded data character to the register corresponding to the corresponding address according to the decoded address character;

[0094] The read operation module is configured to decode the address character from ASCII code to hexadecimal code if the operation character is in the read data state; set the read data enable to a high level, and assign the register corresponding to the address to the data character to be sent according to the decoded address character; decode the data character to be sent from hexadecimal code to ASCII code, convert the decoded data character to be sent from parallel to serial to obtain the serial data to be sent, and send it.

[0095] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0096] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-complexity serial port read and write register processing method, applied to a pure PL platform without PS, characterized in that: The pure PL platform includes a host computer, a UART chip and an FPGA chip connected in sequence, the read and write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip; the processing method includes: In response to receiving the serial data corresponding to the read / write instruction, the FPGA chip performs serial-to-parallel conversion on the serial data to obtain parallel data; caching the parallel data according to character types, wherein the character types include operation characters, address characters, and data characters; Determine whether it is a write data state or a read data state according to the operation character; If the operation character is in the data writing state, the address character and the data character are decoded from ASCII code to hexadecimal code; Set the write data enable to a high level, and assign the decoded data character to the register corresponding to the corresponding address according to the decoded address character; If the operation character is in the data reading state, the address character is decoded from ASCII code to hexadecimal code; Set the read data enable to a high level, and assign the register corresponding to the address to the data character to be sent according to the decoded address character; The data characters to be sent are decoded from hexadecimal codes to ASCII codes, and the decoded data characters to be sent are converted from parallel to serial to obtain serial data to be sent, and then sent.

2. The low-complexity serial port read-write register processing method according to claim 1, characterized in that: The serial data corresponding to the read and write instructions include: Write operation: wrreg xxxx yyyyyyyy, among which, represents a space character, wrreg represents an operation character, xxxx represents an address character, which is defined as 16 bits, and yyyyyyyy represents a data character, which is defined as 32 bits; Read operation: rdreg xxxx, where rdreg represents the operation character.

3. The low-complexity serial port read-write register processing method according to claim 2, characterized in that: The serial-to-parallel conversion includes: Setting a first counter and a second counter; The first counter starts counting when the start bit of the serial port of the UART chip is captured and set to a low level, and performs a clearing operation when the coefficient value is subtracted by 1, and then counts in a loop; Whenever the first counter counts to the coefficient value minus 1, the second counter increases by 1, and when the second counter counts to 9, a clearing operation is performed and counting is cyclic; When the count values ​​of the second counter are 1 to 8 respectively, the serial data is sequentially placed into the 8-bit buffer data according to the principle of putting the advanced data into the lower LSB, thereby completing the conversion of the serial data into parallel data; The acquisition of the coefficient value includes: Use 1s / baud rate to calculate the time required to transmit 1 bit of data at the current baud rate; The required number of unit clocks for transmitting 1 bit of data is obtained by dividing the required time by the unit clock period, and the number of unit clocks is used as the coefficient value.

4. The low-complexity serial port read-write register processing method according to claim 3, characterized in that: The caching of the parallel data according to character type comprises: Setting a third counter; Whenever the second counter counts to 9, the third counter increases by 1, and when the third counter counts to N, a clearing operation is performed and counting is cyclic; When the parallel data is in the write data state, N=18: When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into 48-bit operation characters in order from high to low; When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into 32-bit address characters in order from high to low; When the count value of the third counter is 10 to 18 respectively, the parallel data is sequentially cached into 72-bit data characters in order from high to low; When the parallel data is in the read data state, N=9: When the count value of the third counter is 0 to 5 respectively, the parallel data is sequentially cached into 48-bit operation characters in order from high to low; When the count value of the third counter is 6 to 9 respectively, the parallel data is sequentially cached into 32-bit address characters in order from high to low.

5. The low-complexity serial port read-write register processing method according to claim 4, characterized in that: When the parallel data is in the write data state or the read data state, and any character of the operation character is not the ASCII code value it represents, the third counter is reset.

6. A low-complexity serial port read-write register processing device, applied to a pure PL platform without PS, characterized in that: The pure PL platform includes a host computer, a UART chip and an FPGA chip connected in sequence, the read and write instructions of the host computer are transmitted to the FPGA chip through the serial port of the UART chip, and the data read by the host computer is received from the FPGA chip through the serial port of the UART chip; the processing device includes: The instruction processing module is configured to, in response to receiving serial data corresponding to the read / write instruction, convert the serial data into parallel data by the FPGA chip; A classification cache module is configured to cache the parallel data according to character types, wherein the character types include operation characters, address characters, and data characters; A read / write determination module, configured to determine whether it is a write data state or a read data state according to the operation character; The write operation module is configured to decode the address character and the data character from ASCII code to hexadecimal code if the operation character is in the write data state; set the write data enable to a high level, and assign the decoded data character to a register corresponding to the corresponding address according to the decoded address character; The read operation module is configured to decode the address character from ASCII code to hexadecimal code if the operation character is in the read data state; set the read data enable to a high level, and assign the register corresponding to the address to the data character to be sent according to the decoded address character; decode the data character to be sent from hexadecimal code to ASCII code, convert the decoded data character to be sent from parallel to serial to obtain the serial data to be sent, and send it.

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