A single-line communication system

Abstract

The present application provides a single-line communication system, which relates to the field of communication technology. The system comprises a host, a slave and a first resistor, wherein the host and the slave are connected via a bus, one end of the first resistor is connected to the bus, and the other end is connected to a power supply; when the host pulls the bus down for a time period greater than a preset first time period, the slave enters a reset state; when the slave is in a reset state, and the host pulls the bus down for a time period equal to a preset second time period, the signal receiving end enters an activated state; wherein the second time period is less than the first time period; when the signal receiving end is in an activated state, and the signal sending end pulls the bus down for a time period equal to a preset third time period, the signal receiving end enters a transmission state, and the third time period is associated with the second time period; when the signal receiving end is in a transmission state, the signal sending end sends a data signal or a command signal to the signal receiving end. The present application has the advantage of improving system stability.

Description

Technical Field

[0001] The present application relates to the technical field of chip testing and debugging, and in particular to a single-line communication system. Background Art

[0002] Currently, after the chip is produced, the voltage of the linear regulator inside the chip, the frequency of the clock oscillator and other modules will have large deviations before calibration, and this deviation will affect the normal communication of the external communication interface.

[0003] At this time, if two-wire communication is used, one signal line is used as the clock line and the other signal line is used as the data line, this communication method generally does not cause any failure. However, this communication method occupies two IO ports. In the case of extremely tight pin resources of some chips, there may be insufficient pins. Therefore, in actual communication, a single-wire communication method is used.

[0004] However, the single-wire communication method is sensitive to frequency. The voltage, temperature, and process deviation inside the chip will affect the frequency of the clock. These influences have a great impact on the stability of communication before the chip is calibrated.

[0005] Therefore, there is a problem in the prior art that the communication stability of the single-line communication system is poor. Summary of the invention

[0006] The purpose of the present application is to provide a single-line communication system to solve the problem of poor communication stability of the single-line communication system in the prior art.

[0007] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0008] The embodiment of the present application provides a single-line communication system, which includes a host, a slave, and a resistor. The host and the slave are connected via a bus, one end of the resistor is connected to the bus, and the other end is connected to a power supply; one of the host and the slave is used as a signal sending end, and the other is used as a signal receiving end; wherein,

[0009] The slave includes a reset state, an activation state and a transmission state, and the host includes an activation state and a transmission state;

[0010] When the host pulls the bus down for a time period greater than a preset first time period, the slave enters a reset state;

[0011] When the slave is in a reset state, and the host pulls the bus down for a time period equal to a preset second time period, the signal receiving end enters an activated state; wherein the second time period is less than the first time period;

[0012] When the signal receiving end is in an activated state, and the duration for which the signal transmitting end pulls the bus down is equal to a preset third duration, the signal receiving end enters a transmission state, wherein the third duration is associated with the second duration;

[0013] When the signal receiving end is in a transmission state, the signal sending end sends a data signal or a command signal to the signal receiving end.

[0014] Optionally, when the third duration is equal to half of the second duration, and the bit period is equal to the second duration, the signal transmitted by the bus is logic 0;

[0015] When the third time length is equal to three-half of the second time length, and the bit period is equal to twice the second time length, the signal transmitted by the bus is logic 1.

[0016] Optionally, when the signal receiving end is in the transmission state and the signal sending end sends 8 signal bits to the signal receiving end through the bus, the signal receiving end returns to the activation state.

[0017] Optionally, when the duration for which the signal sending end pulls the bus low is equal to a preset third duration, the signal sending end sends 1 status bit through the bus;

[0018] When the number of bits of logic 1 in the state bit and the signal bit is greater than or equal to 5, the signal sending end sends a command signal to the signal receiving end through the bus;

[0019] When the number of bits of logic 1 in the state bit and the signal bit is less than or equal to 4, the signal transmitting end sends a data signal to the signal receiving end through the bus.

[0020] Optionally, when the number of logic 1s in the setting command signal sent by the signal sending end is less than or equal to 4, in the generated corresponding command signal, the state bit is logic 1, and the signal bit is opposite to the signal bit in the setting command signal;

[0021] When the number of logic 1s in the setting command signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding command signal is generated to be logic 0, and the signal bit is the same as the signal bit in the setting command signal;

[0022] When the number of logic 1s in the setting data signal sent by the signal transmitting end is less than or equal to 4, the state bit in the corresponding data signal is generated to be logic 0, and the signal bit is the same as the signal bit in the setting data signal;

[0023] When the number of logic 1s in the setting data signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding data signal is generated to be logic 1, and the signal bit is opposite to the signal bit in the setting data signal.

[0024] Optionally, when the clock period of the signal receiving end is T, the pulse width of the signal sent by the signal sending end is greater than or equal to 3T.

[0025] Optionally, the second duration is greater than or equal to 2T.

[0026] Optionally, the second duration is less than two-thirds of the first duration.

[0027] Optionally, when the host determines that the slave device has timed out in response, the host pulls the bus low for a time period greater than a preset first time period, so that the slave device enters a reset state.

[0028] Optionally, when the host sends multiple reset command signals to the slave in succession, the slave is reset.

[0029] Compared with the prior art, this application has the following beneficial effects:

[0030] The embodiment of the present application provides a single-line communication system, including a host, a slave and a first resistor, the host and the slave are connected by a bus, one end of the first resistor is connected to the bus, and the other end is connected to the power supply; in the host and the slave, one of them is used as a signal sending end and the other is used as a signal receiving end; wherein, the slave includes a reset state, an activation state and a transmission state, and the host includes an activation state and a transmission state; when the host pulls the bus down for a time longer than a preset first time, the slave enters a reset state; when the slave is in a reset state, and the signal sending end pulls the bus down for a time equal to a preset second time, the signal receiving end enters an activation state; wherein, the second time is less than the first time; when the signal receiving end is in an activation state, and the signal sending end pulls the bus down for a time equal to a preset third time, the signal receiving end enters a transmission state, wherein the third time is associated with the second time; when the signal receiving end is in a transmission state, the signal sending end sends a data signal or a command signal to the signal receiving end. Since the single-line communication system provided by the present application has three states set for the slave and two states set for the host, the signal can only be transmitted in a specific state. Furthermore, the host can define the communication time slice, thus eliminating the impact of unstable slave frequency and improving system stability.

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A circuit diagram of a single-line communication system provided in an embodiment of the present application.

[0034] Figure 2 Another circuit diagram of a single-line communication system provided in an embodiment of the present application.

[0035] Figure 3 A state transition diagram of a slave device provided in an embodiment of the present application.

[0036] Figure 4 A first timing diagram of the state transition of a slave provided in an embodiment of the present application.

[0037] Figure 5 A second timing diagram of the state transition of the slave provided in an embodiment of the present application.

[0038] Figure 6 A third timing diagram of the state transition of the slave provided in an embodiment of the present application.

[0039] Figure 7 A fourth timing diagram of the state transition of the slave provided in an embodiment of the present application.

[0040] Figure 8 A schematic diagram of signal bits provided in an embodiment of the present application.

[0041] Fig. 9 Another schematic diagram of signal bits provided in an embodiment of the present application.

[0042] Fig.10 A schematic diagram of high-order first transmission provided in an embodiment of the present application.

[0043] Fig.11 A schematic diagram of the division of data signals and command signals provided in an embodiment of the present application.

[0044] Fig.12 A first schematic diagram of signal compilation provided in an embodiment of the present application.

[0045] Fig.13 A second schematic diagram of signal compilation provided in an embodiment of the present application.

[0046] Fig.14A third schematic diagram of signal compilation provided in an embodiment of the present application.

[0047] Fig.15 A schematic diagram of timing sampling provided in an embodiment of the present application.

[0048] Fig.16 Another schematic diagram of timing sampling provided in an embodiment of the present application.

[0049] Fig.17 A schematic diagram of the bus driving of the host and slave provided in an embodiment of the present application.

[0050] Fig.18 A schematic diagram of a host initiating a reset operation on a slave provided in an embodiment of the present application.

[0051] Fig.19 A coding diagram used for commands provided in an embodiment of the present application.

[0052] Fig. 20 A schematic diagram of a data transmission command provided in an embodiment of the present application.

[0053] Fig.21 A schematic diagram of an address transfer command provided in an embodiment of the present application.

[0054] Fig. 22 A schematic diagram of a read data command provided in an embodiment of the present application.

[0055] Fig.23 A schematic diagram of a read status command provided in an embodiment of the present application.

[0056] Fig.24 A schematic diagram of a read fixed identification command provided in an embodiment of the present application.

[0057] Fig.25 A schematic diagram of reading a chip ID provided in an embodiment of the present application.

[0058] Fig.26 A schematic diagram of a reset command provided in an embodiment of the present application.

[0059] Fig. 27 A schematic diagram of a query command provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0062] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0063] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0064] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0065] When the chip is manufactured, it needs to be tested and debugged. Testing refers to the testing that chip design manufacturers need to perform after the chip is produced, screening out faulty chips, correcting deviations in internal circuits, and burning relevant data into the non-volatile memory inside the chip. Debugging means that on the user side, users can use this interface as a communication interface to read and write internal registers of the chip for troubleshooting, or program burning in the CPU (Central Processing Unit) chip, as well as single-step running and breakpoint debugging.

[0066] When testing and debugging the chip, as described in the background technology, in order to save IO ports, a single-line communication method can be used. However, the single-line communication method is sensitive to frequency. The voltage, temperature, and process deviation inside the chip will affect the frequency of the clock. These influences have a great impact on the stability of communication before the chip is calibrated.

[0067] In view of this, the present application provides a single-line communication system, which achieves the effect of improving the stability of single-line communication by setting multiple slave states and host states and defining communication time slices by the host.

[0068] The following is an exemplary description of the single-line communication system provided by the present application:

[0069] As an alternative implementation, see Figure 1 The single-line communication system includes a host, a slave and a resistor R0. The host and the slave are connected via a bus. One end of the resistor R0 is connected to the bus and the other end is connected to a power supply. One of the host and the slave serves as a signal sending end and the other serves as a signal receiving end.

[0070] That is, in this application, the host can send signals to the slave, and the slave can also send signals to the host, thereby realizing single-line two-way communication. When the host transmits data to the slave, the host acts as the signal sending end and the slave acts as the signal receiving end; when the host reads the slave data, the slave sends data to the host, at which time the slave acts as the signal sending end and the host acts as the signal receiving end. Of course, the control of the bus is mainly achieved by the host. Specifically, after power-on, the bus is driven by the host to a high level, and the slave does not drive the bus.

[0071] Therefore, in this application, the slave has three states, namely, reset state, activation state and transmission state; and the host has two states, namely, activation state and transmission state. The reset signal can only be initiated by the host, and the slave cannot initiate a reset. The slave drives the bus only after receiving the read command from the host and the host releases the bus. After the slave sends the data, it should actively cancel the drive of the bus. During the handover between the host and the slave, they are jointly driven to a high-impedance state, and the bus level is pulled up to high by resistor R0.

[0072] Therefore, in practical applications, the chip that needs to be tested or debugged can be used as a slave, and the device for testing or debugging can be used as a host, and the two can achieve single-line bidirectional communication through the bus. When there is no signal transmission between the two, the bus is pulled high through resistor R0; when signal transmission is required between the two, the bus is pulled low. In addition, by controlling the length of time the bus is pulled low, the slave or host can enter different states and transmit different signals. It can be understood that the length of time the bus is pulled low can be determined by the host, so the host can define the time slice of communication, thereby eliminating the impact of the unstable frequency of the slave and improving the stability of the entire single-line communication system.

[0073] It should be noted that the "pull up" and "pull down" described in this application are relative concepts. Generally speaking, when the bus voltage is greater than the set value, the bus level is high; and when the bus voltage is less than the set value, the bus level is low. Figure 1In the example, since resistor R0 is connected to the power supply, when there is no signal transmission between the host and the slave, the bus voltage will be pulled to VCC by resistor R0. The voltage value of VCC is greater than the set value, such as the voltage value of VCC is 3.3V, the bus voltage is pulled up to 3.3V. When the host and the slave are transmitting signals, the port of the host or the slave can be grounded, thereby pulling the bus voltage down to 0V. Therefore, the "pulling up" described in this application refers to pulling the bus voltage to the power supply voltage, at which time the bus voltage is a high level; the "pulling down" described in this application refers to pulling the bus voltage down to the ground, at which time the bus voltage is a low level.

[0074] Of course, in order to ensure that there is no failure between the master and slave due to direct connection, as a way to achieve this, please refer to Figure 2 The single-line communication system may also include a host, a slave, a first resistor R1 and a second resistor R2, one end of the second resistor R2 is connected to the host, and the other end is respectively connected to the first resistor R1 and the slave, and the first resistor R1 is also connected to a power supply.

[0075] Similarly, after power-on, the bus is pulled up to a high level. In addition, the host and slave provided in this application both adopt push-pull output to further improve the stability of communication.

[0076] See also Figure 3 The slave includes reset state, activation state and transmission state. The jump relationship between the three states is: the reset state can jump to the activation state, the activation state can jump to the reset state or the transmission state, and the transmission state can jump to the reset state or the activation state.

[0077] Specifically, when the duration of the bus being pulled down by the host is greater than the preset first duration, the slave enters a reset state; when the slave is in a reset state, and the duration of the bus being pulled down by the host is equal to the preset second duration, the signal receiving end enters an activated state; wherein the second duration is less than the first duration. When the signal receiving end is in an activated state, and the duration of the bus being pulled down by the signal transmitting end is equal to the preset third duration, the signal receiving end enters a transmission state, wherein the third duration is associated with the second duration. For example, the third duration is in a multiple relationship with the second duration. When the signal receiving end is in a transmission state, the signal transmitting end may send a data signal or a command signal to the signal receiving end. Wherein, when in an activated state and a transmission state, if the host transmits a signal to the slave, the slave acts as a signal receiving end, and the slave enters an activated state and a transmission state. If the slave transmits a signal to the host, the host acts as a signal receiving end, and the host enters an activated state and a transmission state. It can be understood that only when the signal receiving end is in a transmission state can signals be sent and received between the host and the slave. The signal receiving end needs to be in the transmission state and needs to go through the reset state and the activation state.

[0078] Therefore, please refer to Figure 4 In any state, the host can make the slave enter the reset state by pulling down the bus for a time greater than T1 (the preset first duration). For example, when the host and the slave are not transmitting signals, the bus voltage is pulled up. At this time, if signal transmission is required, the host can output a low level, such as the port connecting the host and the bus is grounded, and the bus level is pulled down. Once the bus level is pulled down for a preset first duration T1, the slave will enter the reset state after receiving the bus level change.

[0079] It should be noted that in order to ensure that the slave enters the reset state, when the host pulls down the bus level, the time for pulling down the bus level can be greater than T1, so that the slave can be guaranteed to enter the reset state. In addition, in order to prevent noise interference, the duration of T1 is generally set to be relatively long, such as tens or hundreds of ms. In this way, when power interference occurs and the bus is suddenly pulled down, the slave will not enter the reset state in this case because the interference pulls down the bus for a short time, thus ensuring the stability of the slave entering the reset state.

[0080] Also, see Figure 5 In the reset state, by pulling down the bus for a period of time T2 (a preset second duration), the signal receiving end can enter the activated state.

[0081] Among them, the duration of T2 is shorter than the duration of T1, so that there is a large difference between the time to enter the reset state and the time to enter the active state, avoiding state confusion. For example, after the slave enters the reset state, if the host pulls the bus low for a time of T2, the slave enters the active state. If the host continues to pull the bus low, and the time of pulling it low reaches T1, the slave enters the reset state again. It should be noted that when jumping from the reset state to the active state, the pulse width can calibrate the communication frequency, thereby realizing self-calibration of the communication frequency.

[0082] See also Figure 6 In the activated state, when the duration of pulling the bus down is equal to T3 (the preset third duration), the signal receiving end can enter the transmission state. The third duration is associated with the second duration. After entering the transmission state, the host and the slave can transmit signals. When the slave receives a signal, the slave enters the transmission state; when the host receives a signal, the host enters the transmission state.

[0083] The third duration described in the present application is associated with the second duration, which means that the third duration and the second duration are in a multiple relationship. Moreover, for the preset third duration, different durations can represent different logics of the digital signal. Among them, the bit period representing the logic 0 is less than the bit period representing 1.

[0084] Specifically, if Figure 6 As shown in FIG. 1 , when the third duration is equal to half of the second duration, and the bit period T0 is equal to the second duration, the signal transmitted by the bus is logic 0. Figure 7 As shown, when the third time length is equal to two thirds of the second time length, and the bit period T0 is equal to twice the second time length, the signal transmitted by the bus is logic 1.

[0085] It can be understood that after the signal receiving end enters the activation state, no matter whether logic 1 or logic 0 is transmitted in the bus, it will trigger the signal receiving end to enter the transmission state.

[0086] In this application, the bits transmitted between the master and the slave are divided into status bits and signal bits. The status bit refers to the bit transmitted when jumping from the activation state to the transmission state. Figure 6 and Figure 7 In the example, after the signal receiving end enters the activation state, when the state bit is received, the signal receiving end enters the transmission state regardless of whether the state bit is logic 0 or logic 1. After entering the transmission state, the bit transmitted at this time is the signal bit.

[0087] Furthermore, when the signal receiving end is in the transmission state and the signal sending end sends 8 signal bits to the signal receiving end through the bus, the signal receiving end returns to the activated state. That is, in the present application, the signal is transmitted in a cycle-by-cycle manner, and for each cycle, it includes 1 bit representing the transition from the activated state to the transmission state, and 8 bits representing the specific signal. That is, each transmission cycle includes 9 bits. After the 9 bits are transmitted, the signal receiving end returns to the activated state, and if the signal of the next cycle needs to be transmitted, it continues to transmit 9 bits.

[0088] For example, see Figure 8 After entering the activation state, 8 signal bits are transmitted between the master and the slave, and the signal bits can be logic 0 or logic 1. For example, the signal bits are 00000000, 00100000, etc. After transmitting 8 signal bits, the signal receiving end jumps to the activation state. If the signal needs to be transmitted again, the signal sending end needs to send the status bit again. After the signal receiving end enters the transmission state again, it continues to transmit 8 signal bits.

[0089] Therefore, in a transmission cycle defined in this application, the first bit is the status bit, and the other 8 bits are signal bits. Of course, when transmitting signal bits, it is allowed to insert a continuous high level in the middle of the signal bits. Fig. 9 As shown, a high level is inserted between the third signal bit and the fourth signal bit.

[0090] See also Fig.10In this application, the 8 signal bits are transmitted with logic high bits first. In the figure, LIE represents the status bit, B0~B7 represents the signal bits, and after the status bit is transmitted, the signal receiving end enters the transmission state and transmits the signal bits in the high-bit priority order of B7, B6, B5...B0.

[0091] Furthermore, in this application, the signals transmitted between the host and the slave include data signals and command signals. The data signal refers to the specific data transmitted, such as temperature data, current data, etc., and the command signal refers to some commands transmitted, such as reset, enable, etc.

[0092] When distinguishing command signals from data signals, refer to Fig.11 , when the number of logical 1 bits in the status bit and the signal bit is greater than or equal to 5, the signal transmitter sends a command signal to the signal receiver through the bus; when the number of logical 1 bits in the status bit and the signal bit is less than or equal to 4, the signal transmitter sends a data signal to the signal receiver through the bus. That is, in each transmission cycle, 9 bits are included; if the number of logical 1 bits in the 9 bits is greater than or equal to 5, then this transmission cycle represents a command signal; if the number of logical 1 bits is less than 5, then this transmission cycle represents a data signal. For example, if the signal transmitted in a certain transmission cycle is 1111111111, it means that the transmission cycle transmits a command signal; if a certain transmission cycle is 111100000, it means that the transmission cycle transmits a data signal.

[0093] It should be noted that, through the setting of the transmission period, the accurate division of the command signal and the data signal is ensured. In addition, since the bit period of logic 0 is the second time length T2, the bit period of logic 1 is twice the second time length T2. In addition, the number of logic 0s in the transmitted data signal is the majority, so for the data signal, more signals can be transmitted per unit time, so the rate of transmitting the data signal can be faster.

[0094] In the signal transmission between the host and the slave, the command signal accounts for a small proportion, and most of them are data transmission signals. Therefore, the transmission rate of the entire system can be faster and the transmission efficiency can be higher. In addition, since the bit period of logic 0 and logic 1 is different, the communication rate can be adaptive when the host and the slave communicate. For example, 111100000 and 000000000 are both data signals, but the transmission rates between the two can be different. Therefore, the above setting method realizes the adaptive communication rate.

[0095] On the basis of the above implementation, when performing specific signal compilation, when the state bit is 1, the signal bit is inverted to determine the specific data signal or command signal. When the state bit is 0, the signal bit remains unchanged.

[0096] In one implementation, see Fig.12 , when signal compilation is performed, the original signal and the status bit need to be processed by XOR before they are output. For example, when the host performs signal compilation, when the original signal to be transmitted to the slave is 01010101, and the status bit is 1, due to the working principle of the XOR gate, if the input level is the same, the output is 0; if the input level is different, the output is 1. Therefore, the output signal bit is 10101010. That is, when compiling, the signal bit is opposite to the original signal. When the status bit is 0, the signal bit is the same as the original bit.

[0097] On this basis, when the number of logical 1s contained in the setting command signal sent by the signal sending end is less than or equal to 4, the state bit in the corresponding command signal is logical 1, and the signal bit is opposite to the signal bit in the setting command signal; when the number of logical 1s contained in the setting command signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding command signal is logical 0, and the signal bit is the same as the signal bit in the setting command signal; when the number of logical 1s contained in the setting data signal sent by the signal sending end is less than or equal to 4, the state bit in the corresponding data signal is logical 0, and the signal bit is the same as the signal bit in the setting data signal; when the number of logical 1s contained in the setting data signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding data signal is logical 1, and the signal bit is opposite to the signal bit in the setting data signal.

[0098] For example, see Fig.13 , when the transmitted signal is a command signal, if the original command signal to be transmitted is C7~C0, the state bit is determined according to the number of logical 1s contained in the original signal. If the number of logical 1s contained is less than or equal to 4, the state bit is 1, and the original command signal is inverted and compiled into the signal to be transmitted, which is 0, ~C7, ~C6...~C0. If the number of logical 1s contained is greater than or equal to 5, the state bit is 0, and the original command signal is kept unchanged and compiled into the signal to be transmitted, which is 0, C7, C6...C0.

[0099] See also Fig.14 , when the transmitted signal is a data signal, if the original data signal to be transmitted is D7~D0, the state bit is determined according to the number of logical 1s contained in the original data signal. If the number of logical 1s contained is greater than or equal to 5, the state bit is 1, and the original data signal is inverted and compiled into the signal to be transmitted, which is 0, ~D7, ~D6...~D0. If the number of logical 1s contained is less than or equal to 4, the state bit is 0, and the original data signal is kept unchanged and compiled into the signal to be transmitted, which is 0, D7, D6...D0.

[0100] In addition, in order to ensure that the signal receiving end can stably sample the bus signal at least twice, as an implementation method, when the clock period of the signal receiving end is T, the pulse width of the signal sent by the signal sending end is greater than or equal to 3T.

[0101] For example, see Fig.15 , when the slave is used as the signal receiving end, if the clock cycle of the slave is T, then in the signal sent by the host, the pulse width Tpluse_min is greater than or equal to 3T. Taking the pulse width Tpluse_min equal to 3T as an example, in extreme cases, even if the slave end samples the rising edge or falling edge (x in the figure), it can still sample at least 2 bus signals at each pulse width, improving the stability of system sampling.

[0102] In addition, the low level T2 sent in the active state should be greater than or equal to 2 times Tpluse_min, that is, Tactive>= 2 *Tpluse_min. Therefore, the second duration is greater than or equal to 6T. After receiving the activation pulse, the signal receiving end should record the number of sampling times of the low level of the activation pulse. If the number of counts of the subsequent low levels is less than the number of low levels of the activation pulse, it is recorded as logic 0. If the number of counts is greater than the number of low levels of the activation pulse, it is recorded as logic 1.

[0103] See also Fig.16 In extreme cases, when T2 = 2 * Tpluse_min, when sending logic 0, the number of low-level samples sampled by the signal receiving end may be 2, 3, or 4, and when sending logic 1, the number of low-level samples sampled by the signal receiving end may be 8, 9, or 10, while the number of activated low-level samples may be 5, 6, or 7, avoiding misjudgment when judging logic 0 and logic 1.

[0104] Furthermore, as an implementation method, the second duration is less than two-thirds of the first duration, thereby preventing the existence of interference from misjudging logic 1 as reset. That is, the low level T2 sent during activation should be less than 2 / 3 * T1, that is, T2<2 / 3 * T1. This setting ensures that a certain distance is maintained between T2 and 2 / 3 * T1, effectively preventing logic 1 from being misjudged as reset.

[0105] As an implementation method, the time of T1 is 256 clock cycles of the slave, that is, T1 = 256 * T.

[0106] In this application, the priority of the host is higher than that of the slave. That is, after power-on, the bus is driven high by the host, and the slave does not drive the bus. The slave drives the bus only after receiving the read command from the host and the host releases the bus. After the slave sends the data, it should actively cancel the drive of the bus. During the handover between the host and the slave, they are driven to a high impedance state together, and the bus level is pulled up to high by the pull-up resistor R1.

[0107] See also Fig.17 After the host sends a read command (B2, B1, B0), the host releases the bus, and after a period of high impedance Z1, the slave starts to drive the bus. Among them, LIE after Z1 represents the status bit sent by the slave, and then in the transmission state, the slave returns the signal bit to the host. When the slave sends the data, it automatically cancels the drive of the bus. At this time, after a period of high impedance Z2, the bus is driven by the host again. That is, LIE after Z2 and B7~B0 are the host driving the bus.

[0108] When the slave sends data to the host, it should not send reset and activation operations, but only return status or data, and the timing should also follow the timing of the host to the slave. The definition of the status is consistent with the command sent by the host to the slave. After the slave obtains control of the bus, if an error has occurred inside the slave, before returning data, it should actively report the error to the host and then return the data.

[0109] In addition, the host can drive the slave to re-enter the reset state when the slave fails. For example, after the host sends a read command to the slave, it waits for the slave to respond and return status or data. If the slave does not respond within a certain period of time (such as 25ms), it is judged as a timeout, and the host should take over the bus drive and re-initiate the reset operation.

[0110] See also Fig.18 After the host sends a read command (B2, B1, B0) to the slave, if the slave does not respond within 25ms, that is, the bus is in a high-impedance state Z for 25ms, the host re-initiates a reset operation to put the slave into the reset state again.

[0111] Alternatively, when the master and slave drive the bus level, they should detect whether the drive level and the bus level are consistent. If the master detects that the drive level and the bus level are inconsistent when driving the bus, the master will also initiate a reset operation. If the slave detects that the drive level and the bus level are inconsistent when driving the bus, the slave will give up driving the bus and switch to passive listening to receive the reset operation of the master.

[0112] And, after the host and slave receive the first logic bit, the subsequent 8 logic bits should be continuous. Fig. 9As shown in the figure, after entering the transmission state, a high level is allowed to be inserted between the logic bits, but if the time between the logic bits exceeds the T1 time, the transmission state should be exited, and the logic bits received afterwards should be regarded as a new start. If it is the slave that is receiving, the slave should record this error and report it to the host after the next read request.

[0113] During the transmission process between the host and the slave, the following command protocols need to be followed:

[0114] When data is transmitted, 256 data from 0x00 to 0xff are used together with commands. When data is transmitted, after 8B->9B encoding, the number of 1s will not exceed 4. And when data is transmitted, there should be a CRC (Cyclic Redundancy Check) check.

[0115] Among them, see Fig.19 , the command uses the 44 codes shown in the figure. After the command in the figure is encoded by 8B->9B, the number of 1s is 6, and there are no more than 3 consecutive identical codes. Other commands are considered illegal commands.

[0116] See also Fig. 20 There are 11 data transmission commands, 0x23 is a 1-byte data transmission command, 0x25 is a 2-byte data transmission command, 0x26 is a 4-byte data transmission command, 0x29 is an 8-byte data transmission command, 0x2a is a 16-byte data transmission command, 0x2c is a 32-byte data transmission command, 0x45 is a 64-byte data transmission command, 0x46 is a 128-byte data transmission command, 0x49 is a 256-byte data transmission command, 0x4a is a 512-byte data transmission command, and 0x4c is a 1024-byte data transmission command.

[0117] Of course, the slave can selectively support the above commands. These commands are used when the master transmits data to the slave and when the slave transmits data to the master.

[0118] See also Fig.21 There are 4 address transmission commands, 0x31 is 1-byte address transmission, 0x32 is 2-byte address transmission, 0x34 is 4-byte address transmission, and 0x38 is 8-byte address transmission. The slave should selectively support the bit width of the address according to the scenario.

[0119] See also Fig. 22 In the read data command, 0xb7 is the read data command. After sending the command packet, the host should release the bus driver, and then the slave drives the bus and returns the data. Among them, DT is Fig. 20 Data transfer commands in.

[0120] See also Fig.23 In the read status command, 0xbb is the master's read status command to the slave. After sending the command packet, the master should release the bus driver, and then the slave drives the bus and uses the command 0xee to return the status information. After returning the status information, the slave should clear the previous error status. In addition, when the slave receives any read command, if there is an error inside the slave, it should actively transmit the status report first, and then transmit the data.

[0121] The definition of the status register is shown in Table 1:

[0122] Table 1

[0123]

[0124] See also Fig.24 , read fixed identification, 0xc4 is the host to the slave read fixed identification command, after sending the command packet, the host should release the bus drive, then the slave drive the bus, return the fixed identification information, and the returned data is the ASCII code of "SWID".

[0125] See also Fig.25 , read chip ID, 0xc8 is the master to slave read chip ID command, after the master sends the command packet, it should release the bus drive, then the slave drives the bus and returns the slave chip ID information. This command is used to distinguish different chips.

[0126] When the master determines that the slave has timed out, the master pulls the bus low for a time greater than the preset first time to put the slave into a reset state. Fig.26 , provides a reset command, 0x77 is the reset command of the host to the slave. The host can reset the slave by sending this command three times in succession.

[0127] See also Fig. 27 , 0xd7 is the query command initiated by the host to the slave. After sending the command packet, the host should release the bus drive, and then the slave drives the bus and returns the query information. The query information is the length of data that the slave needs to return. 0 means that no data needs to be returned. This command is used by the slave to actively initiate data transmission to the host. After receiving the query information, the host initiates a read request based on the data length to read the data inside the slave.

[0128] It should be noted that the CRC8 calculation method provided in this application uses the polynomial 0x131, that is:

[0129] CRC8=X 8 +X 5 +X 4 +1

[0130] In summary, an embodiment of the present application provides a single-line communication system, including a host, a slave and a first resistor, the host and the slave are connected via a bus, one end of the first resistor is connected to the bus, and the other end is connected to a power supply; among the host and the slave, one serves as a signal sending end and the other serves as a signal receiving end; wherein, the slave includes a reset state, an activation state and a transmission state, and the host includes an activation state and a transmission state; when the host pulls the bus low for a duration greater than a preset first duration, the slave enters a reset state; when the slave is in a reset state and the signal sending end pulls the bus low for a duration equal to a preset second duration, the signal receiving end enters an activation state; wherein the second duration is less than the first duration; when the signal receiving end is in an activation state and the signal sending end pulls the bus low for a duration equal to a preset third duration, the signal receiving end enters a transmission state, wherein the third duration is associated with the second duration; when the signal receiving end is in a transmission state, the signal sending end sends a data signal or a command signal to the signal receiving end. Since the single-line communication system provided by the present application has three states set for the slave and two states set for the host, signal transmission can only be performed in a specific state. In addition, the host can define the communication time slice, thereby eliminating the impact of unstable slave frequency and improving system stability.

[0131] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0132] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A single-line communication system, characterized in that: The single-line communication system includes a host, a slave and a resistor, wherein the host and the slave are connected via a bus, one end of the resistor is connected to the bus, and the other end is connected to a power supply; one of the host and the slave is used as a signal sending end, and the other is used as a signal receiving end; wherein, The slave includes a reset state, an activation state and a transmission state, and the host includes an activation state and a transmission state; When the host pulls the bus down for a time period greater than a preset first time period, the slave enters a reset state; When the slave is in a reset state, and the host pulls the bus down for a time period equal to a preset second time period, the signal receiving end enters an activated state; wherein the second time period is less than the first time period; When the signal receiving end is in an activated state, and the duration for which the signal transmitting end pulls the bus down is equal to a preset third duration, the signal receiving end enters a transmission state, wherein the third duration is associated with the second duration; When the signal receiving end is in a transmission state, the signal sending end sends a data signal or a command signal to the signal receiving end.

2. The single-line communication system according to claim 1, characterized in that: When the third duration is equal to half of the second duration, and the bit period is equal to the second duration, the signal transmitted by the bus is logic 0; When the third time length is equal to two thirds of the second time length, and the bit period is equal to twice the second time length, the signal transmitted by the bus is logic 1.

3. The single-line communication system according to claim 2, characterized in that: When the signal receiving end is in the transmission state and the signal sending end sends 8 signal bits to the signal receiving end through the bus, the signal receiving end returns to the activation state.

4. The single-line communication system according to claim 3, characterized in that: When the duration for which the signal transmitting end pulls the bus down is equal to a preset third duration, the signal transmitting end transmits one status bit through the bus; When the number of bits of logic 1 in the state bit and the signal bit is greater than or equal to 5, the signal sending end sends a command signal to the signal receiving end through the bus; When the number of bits of logic 1 in the state bit and the signal bit is less than or equal to 4, the signal transmitting end sends a data signal to the signal receiving end through the bus.

5. The single-line communication system according to claim 4, characterized in that: When the number of logic 1s in the setting command signal sent by the signal sending end is less than or equal to 4, the state bit in the corresponding command signal is generated to be logic 1, and the signal bit is opposite to the signal bit in the setting command signal; When the number of logic 1s in the setting command signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding command signal is generated to be logic 0, and the signal bit is the same as the signal bit in the setting command signal; When the number of logic 1s in the setting data signal sent by the signal transmitting end is less than or equal to 4, the state bit in the corresponding data signal is generated to be logic 0, and the signal bit is the same as the signal bit in the setting data signal; When the number of logic 1s in the setting data signal sent by the signal sending end is greater than or equal to 5, the state bit in the corresponding data signal is generated to be logic 1, and the signal bit is opposite to the signal bit in the setting data signal.

6. The single-line communication system according to claim 1, characterized in that: When the clock period of the signal receiving end is T, the pulse width of the signal sent by the signal sending end is greater than or equal to 3T.

7. The single-line communication system according to claim 6, characterized in that: The second duration is greater than or equal to 6T.

8. The single-line communication system according to claim 1, characterized in that: The second duration is less than two-thirds of the first duration.

9. The single-line communication system according to claim 1, characterized in that: When the host determines that the slave has timed out in response, the host pulls the bus down for a time period greater than a preset first time period, so that the slave enters a reset state.

10. The single-line communication system according to claim 1, characterized in that: When the host sends multiple reset command signals to the slave in succession, the slave is reset.

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