Digital simulation verification method and system for quadruple-redundant flight tube computer

Abstract

The present invention provides a digital simulation verification method and system for a quadruple-redundant flight tube computer, comprising: step S1: simulating and modeling a digital chip PowerPC750; step S2: simulating and modeling a quadruple-redundant flight tube computer; step S3: completing time synchronization of the quadruple-redundant flight tube computer by synchronizing clock beats; step S4: completing data synchronization by distributed data bus or memory sharing; step S5: performing scenario verification tests including synchronous operation, time-sharing startup, and fault simulation. The present invention completes data synchronization by distributed data bus or memory sharing technology, verifies the functions of multiple quadruple-redundant flight tube computers on one host, and improves verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of digital simulation technology, and in particular to a digital simulation verification method and system for a quadruple-redundant flight tube computer. Background Art

[0002] Redundancy control is a control system used by aircraft. The flight control of existing aircraft uses flight control computers to control and manage the aircraft's control system. However, during the flight of the aircraft, system failures may occur, causing the flight control system to crash, thereby causing serious flight accidents. In order to prevent the above accidents from happening, existing aircraft will use a redundancy management system (redundancy refers to a design method that requires two or more failures, rather than a single failure, to cause a predetermined undesirable working state) to set up multiple functional links. When a functional link crashes, another backup link can be quickly enabled to ensure that the flight control system can continue to control the aircraft.

[0003] As the key control hardware system of the model aircraft, the quadruple-redundant flight control computer participates in the flight control of the aircraft throughout the whole process. It is equivalent to the "brain" of the aircraft and is an important guarantee for the aircraft to achieve automated and intelligent flight. At present, the quadruple-redundant flight control computer is a proprietary device with high hardware cost and long delivery cycle. For software development supporting units other than the host institute, they do not have the conditions for batch purchase. They can only use the semi-physical single-board combination method to complete the basic function verification test, which cannot effectively verify the precise synchronous control and specific fault scenarios. As a result, the design defects and development quality problems are not identified until the joint test, resulting in multiple rework and task delays. At present, the shortage of physical test resources affects the development progress; the inefficiency of semi-physical testing and the lack of testing methods affect the quality of the model. It is necessary to use digital twin technology to adopt a full digital simulation method to speed up the development process. Summary of the invention

[0004] In view of the defects in the prior art, the purpose of the present invention is to provide a digital simulation verification method and system for a quadruple-redundant flight tube computer.

[0005] A digital simulation verification method for a quadruple-redundant flight tube computer provided by the present invention comprises:

[0006] Step S1: Simulate and model the digital chip PowerPC750;

[0007] Step S2: Simulating and modeling the quadruple-redundant flight tube computer;

[0008] Step S3: completing the time synchronization of the quadruple-redundant flight tube computer by synchronizing the clock beat;

[0009] Step S4: completing data synchronization through a distributed data bus or memory sharing;

[0010] Step S5: Perform scenario verification tests including synchronous operation, time-sharing startup, and fault simulation.

[0011] Preferably, the step S1 comprises:

[0012] Step S1.1: Obtain the instruction set of the digital chip PowerPC75O, model the instruction decoder and execution unit, verify the correctness of instruction parsing, and ensure that the execution results are consistent with those generated by the real hardware;

[0013] Step S1.2: Based on the digital chip PowerPC75O target board, complete the modeling of on-chip peripherals including RAM, ROM, timer and interrupt controller;

[0014] Step S1.3: Modeling the external communication interface, obtaining external excitation and collecting CPU operation feedback data;

[0015] Step S1.4: Model the synchronous clock beat interface to complete the time calibration and time window control between the local time and the external system time.

[0016] Preferably, step S2 comprises:

[0017] Step S2.1: Based on the digital chip PowerPC750 model and according to the hardware structure of the quadruple-redundant flight tube computer, a digital quadruple-redundant flight tube computer simulation modeling is completed by using a graphical construction method;

[0018] Step S2.2: Complete the parameter setting and active / standby switching setting of each CPU according to the hardware setting in the real environment;

[0019] Step S2.3: loading the binary software code burned into the quadruple-redundant flight tube computer into the digital simulation environment according to the specified address;

[0020] Step S2.4: Use the host clock as the time standard to complete the clock control of the other three CPUs.

[0021] Preferably, the step S3 includes: using the beat control mechanism of the distributed data bus to complete the time synchronization and time window control between the internal simulation time of the digital chip PowerPC750 and the external system time.

[0022] Preferably, step S4 includes: using a shared memory read / write mechanism and / or a distributed data bus to complete data synchronization among four digital chips PowerPC750.

[0023] Preferably, step S5 comprises:

[0024] Step S5.1: Use the set synchronous control protocol command to complete the start, run and stop control of the digital quadruple-redundant flight tube computer;

[0025] Step S5.2: completing the scenario simulation of time-sharing startup and delayed startup due to a CPU failure by initializing the startup time difference setting;

[0026] Step S5.3: Simulate irreversible damage business scenarios by injecting CPU register, memory and communication link faults;

[0027] Step S5.4: Complete the test scenario construction, test data generation, test script editing, test script running, test data and running status monitoring, and test report generation through the network call interface, and support automated test integration.

[0028] A digital simulation verification system for a quadruple-redundant flight tube computer provided by the present invention comprises:

[0029] Module M1: Simulation modeling of digital chip PowerPC750;

[0030] Module M2: Simulation modeling of quadruple-redundant flight tube computer;

[0031] Module M3: complete the time synchronization of the quadruple redundant flight tube computer by synchronizing the clock beat;

[0032] Module M4: completes data synchronization through distributed data bus or memory sharing;

[0033] Module M5: Scenario verification testing including synchronous operation, time-sharing startup and fault simulation.

[0034] Preferably, the module M1 comprises:

[0035] Module M1.1: Obtain the instruction set of the digital chip PowerPC75O, model the instruction decoder and execution unit, verify the correctness of instruction parsing, and ensure that the execution results are consistent with those generated by the real hardware;

[0036] Module M1.2: Based on the digital chip PowerPC75O target board, complete the modeling of on-chip peripherals including RAM, ROM, timer and interrupt controller;

[0037] Module M1.3: Model the external communication interface, obtain external stimulus and collect CPU operation feedback data;

[0038] Module M1.4: Model the synchronous clock beat interface to complete the time calibration and time window control between the local time and the external system time.

[0039] Preferably, the module M2 comprises:

[0040] Module M2.1: Based on the digital chip PowerPC750 model and the hardware structure of the quadruple-redundant flight tube computer, a graphical construction method is used to complete the digital quadruple-redundant flight tube computer simulation modeling;

[0041] Module M2.2: Complete the parameter settings and active / standby switching settings of each CPU according to the hardware settings in the real environment;

[0042] Module M2.3: Load the binary software code written in the quadruple-redundant flight tube computer into the digital simulation environment according to the specified address;

[0043] Module M2.4: Use the host clock as the time standard to complete the clock control of the other three CPUs.

[0044] Preferably, the module M3 includes: using the beat control mechanism of the distributed data bus to complete the time calibration and time window control of the internal simulation time of the digital chip PowerPC750 and the external system time;

[0045] The module M4 includes: using a shared memory read-write mechanism and / or a distributed data bus to complete data synchronization between four digital chips PowerPC750;

[0046] The module M5 comprises:

[0047] Module M5.1: Use the set synchronous control protocol commands to complete the start, run and stop control of the digital quadruple-redundant flight tube computer;

[0048] Module M5.2: Complete the scenario simulation of time-sharing startup and delayed startup due to a CPU failure by setting the initial startup time difference;

[0049] Module M5.3: Simulate irreversible damage business scenarios through CPU register, memory and communication link fault injection;

[0050] Module M5.4: Completes test scenario construction, test data generation, test script editing, test script execution, test data and operation status monitoring, and test report generation through network call interfaces, and supports automated test integration.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] 1. The present invention solves the problem that four physical target boards cannot be quickly and accurately synchronized and controlled by digital simulation technology, completes the computer simulation of quadruple-redundant flight tubes, can be independent of hardware dependence, develop in parallel with hardware, carry out software function testing in advance, identify software defects as early as possible at the design front end, and shorten the R&D test cycle;

[0053] 2. The present invention completes data synchronization through a distributed data bus or memory sharing technology, verifies the functions of multiple quadruple-redundant flight tube computers on one host, and improves verification efficiency;

[0054] 3. The present invention can complete the integration of complex systems and system function verification through subsystem combination, so that the overall test verification is shifted left, the system interaction design problems are identified early, and the problem that the unit test passes but the integration test needs to be reworked to modify the interaction interface is solved, thereby reducing the rework time cost caused by design problems;

[0055] 4. The present invention can complete irreversible fault scenarios that cannot be reproduced by real hardware through fault injection, verify the hardware's safety fault-tolerant mechanism, quickly locate problems, and expand the scenario coverage of security testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0057] Figure 1 This is a schematic diagram of the digital simulation verification system of the quadruple-redundant flight tube computer.

[0058] Figure 2 This is a flow chart of the digital simulation verification method for the quadruple-redundant flight tube computer.

[0059] Figure 3 This is a schematic diagram of data synchronization. DETAILED DESCRIPTION

[0060] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0061] Example 1

[0062] According to a digital simulation verification method and system for a quadruple-redundant flight tube computer provided by the present invention, a full digital simulation technology is used to complete the hardware environment simulation of the quadruple-redundant flight tube computer, and the time synchronization of the quadruple-redundant flight tube computer is completed by synchronizing the clock beat; data synchronization is completed by distributed data bus or memory sharing technology; synchronous operation of the simulation system is set by software, fault verification is started in time-sharing, and the main-standby switching function verification verifies the flight tube software function in the early design stage without hardware.

[0063] The digital simulation verification method of the quadruple-redundant flight tube computer is as follows: Figures 1 to 3As shown, including:

[0064] Step 1: Complete the simulation modeling of the digital chip PowerPC750 according to the chip manual;

[0065] Step 2: Complete the construction of the digital simulation flight control target machine by referring to the quadruple-redundant flight control computer hardware design manual;

[0066] Step 3: Use the synchronization beat of the distributed data bus to complete the startup and operation control of the four PowerPC750s, and use the shared memory read and write mechanism to complete the data synchronization between the four PowerPC750s;

[0067] Step 4: Verify business scenarios such as synchronous operation, time-sharing startup, and fault simulation that are difficult to simulate with real hardware.

[0068] Specifically, the step 1 includes the following steps:

[0069] Step 1.1: The digital chip PowerPC75O instruction parsing and execution results are consistent with the real hardware;

[0070] Step 1.2: Complete the modeling of on-chip peripherals such as RAM, ROM, watchdog, timer, interrupt controller, etc. by referring to the real PowerPC75O target board;

[0071] Step 1.3: The reserved visual property setting interface can be used to set CPU operating parameters and active / standby modes;

[0072] Step 1.4: According to the actual hardware situation, the digital external communication interface is encapsulated as distributed data bus data through a unified protocol format, and the external stimulus injection and digital simulation CPU operation feedback data collection are completed in a fully digital manner without the real physical hardware;

[0073] Step 1.5: Use the synchronous clock beat interface provided by the distributed data bus to complete the synchronization and time window control between the internal simulation time of the digital chip PowerPC750 and the external system time.

[0074] Specifically, the step 2 includes the following steps:

[0075] Step 2.1: Corresponding to the PowerPC75O in step 1, a digital quadruple-redundant flight tube computer is built using a graphical construction method according to the actual quadruple-redundant flight tube computer hardware configuration;

[0076] Step 2.2: Complete the parameter settings and active / standby switching settings of each CPU according to the hardware settings in the real environment;

[0077] Step 2.3: Load the binary software code burned into the quadruple-redundant flight tube computer into the digital simulation environment according to the specified address;

[0078] Step 2.4: Use the host clock as the time standard to complete the clock control of the other three CPUs.

[0079] Specifically, step 3 includes the following steps:

[0080] Step 3.1: corresponds to the clock synchronization control and data synchronization part in step 2;

[0081] Step 3.2: For clock synchronization control, the timing synchronization between each CPU is ensured through the synchronization beat command and response mechanism;

[0082] Step 3.3: If Figure 3 The shared memory read-write space is preset, and semaphores are used to control the read-write control of the shared memory to achieve synchronization and mutual exclusion of data communication among the four CPUs.

[0083] Specifically, step 4 includes the following steps:

[0084] Step 4.1: Use the set synchronous control protocol command to complete the start, run and stop control of the digital quadruple-redundant flight tube computer;

[0085] Step 4.2: Complete the scenario simulation of time-sharing startup and delayed startup due to a CPU failure by initializing the startup time difference setting;

[0086] Step 4.3: Simulate irreversible damage scenarios that are difficult to reproduce on real hardware by injecting CPU register, memory and communication link faults;

[0087] Step 4.4: Complete common test functions such as test scenario construction, test data generation, test script editing, test script running, test data and running status monitoring, and test report generation through the network call interface, support automated test integration, and complete complex system integration and system function verification.

[0088] The present invention also provides a digital simulation verification system for a quadruple-redundant flight tube computer. The digital simulation verification system for the quadruple-redundant flight tube computer can be implemented by executing the process steps of the digital simulation verification method for the quadruple-redundant flight tube computer, that is, those skilled in the art can understand the digital simulation verification method for the quadruple-redundant flight tube computer as a preferred implementation of the digital simulation verification system for the quadruple-redundant flight tube computer.

[0089] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0090] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A digital simulation verification method for a quadruple-redundant flight tube computer, characterized in that: include: Step S1: Simulate and model the digital chip; Step S2: performing simulation modeling on the quadruple-redundant flight tube computer according to the digital chip; Step S3: completing the time synchronization of the quadruple-redundant flight tube computer by synchronizing the clock beat; Step S4: completing the quadruple-redundant flight tube computer data synchronization through a distributed data bus or memory sharing; Step S5: Perform scenario verification tests including synchronous operation, time-sharing startup, and fault simulation; The step S3 includes: using the beat control mechanism of the distributed data bus to complete the time calibration and time window control of the internal simulation time of the digital chip and the external system time; The step S4 includes: using a shared memory read-write mechanism and / or a distributed data bus to complete data synchronization between the four digital chips; The step S5 comprises: Step S5.1: Use the set synchronous control protocol command to complete the start, run and stop control of the digital quadruple-redundant flight tube computer; Step S5.2: completing the scenario simulation of time-sharing startup and delayed startup due to a CPU failure by initializing the startup time difference setting; Step S5.3: Simulate irreversible damage business scenarios by injecting CPU register, memory and communication link faults; Step S5.4: Complete the test scenario construction, test data generation, test script editing, test script running, test data and running status monitoring, and test report generation through the network call interface, and support automated test integration.

2. The digital simulation verification method of the quadruple-redundant flight tube computer according to claim 1, characterized in that: The step S1 comprises: Step S1.1: Obtain the instruction set of the digital chip, model the instruction decoder and execution unit, verify the correctness of instruction parsing, and ensure that the execution results are consistent with those generated by the real hardware; Step S1.2: Based on the digital chip target board, complete the modeling of on-chip peripherals including RAM, ROM, timer and interrupt controller; Step S1.3: Modeling the external communication interface, obtaining external excitation and collecting CPU operation feedback data; Step S1.4: Model the synchronous clock beat interface to complete the time calibration and time window control between the local time and the external system time.

3. The digital simulation verification method of the quadruple-redundant flight tube computer according to claim 1 is characterized in that: The step S2 comprises: Step S2.1: Based on the digital chip model and the hardware structure of the quadruple-redundant flight tube computer, a digital quadruple-redundant flight tube computer simulation modeling is completed by using a graphical construction method; Step S2.2: Complete the parameter setting and active / standby switching setting of each CPU according to the hardware setting in the real environment; Step S2.3: loading the binary software code burned into the quadruple-redundant flight tube computer into the digital simulation environment according to the specified address; Step S2.4: Use the host clock as the time standard to complete the clock control of the other three CPUs.

4. A digital simulation verification system for a quadruple-redundant flight tube computer, characterized in that: include: Module M1: Simulation modeling of digital chips; Module M2: Simulating and modeling the quadruple-redundant flight tube computer according to the digital chip; Module M3: complete the time synchronization of the quadruple redundant flight tube computer by synchronizing the clock beat; Module M4: Complete quadruple-redundant flight tube computer data synchronization through distributed data bus or memory sharing; Module M5: Scenario verification test including synchronous operation, time-sharing start-up and fault simulation; The module M3 includes: using the beat control mechanism of the distributed data bus to complete the time calibration and time window control of the internal simulation time of the digital chip and the external system time; The module M4 includes: using a shared memory read-write mechanism and / or a distributed data bus to complete data synchronization between four digital chips; The module M5 comprises: Module M5.1: Use the set synchronous control protocol commands to complete the start, run and stop control of the digital quadruple-redundant flight tube computer; Module M5.2: Complete the scenario simulation of time-sharing startup and delayed startup due to a CPU failure by setting the initial startup time difference; Module M5.3: Simulate irreversible damage business scenarios through CPU register, memory and communication link fault injection; Module M5.4: Completes test scenario construction, test data generation, test script editing, test script execution, test data and operation status monitoring, and test report generation through network call interfaces, and supports automated test integration.

5. The digital simulation verification system of the quadruple-redundant flight tube computer according to claim 4 is characterized in that: The module M1 comprises: Module M1.1: Obtain the instruction set of the digital chip, model the instruction decoder and execution unit, verify the correctness of instruction parsing, and ensure the execution results are consistent with those generated by the real hardware; Module M1.2: Based on the digital chip target board, complete the modeling of on-chip peripherals including RAM, ROM, timer and interrupt controller; Module M1.3: Model the external communication interface, obtain external stimulus and collect CPU operation feedback data; Module M1.4: Model the synchronous clock beat interface to complete the time calibration and time window control between the local time and the external system time.

6. The digital simulation verification system of the quadruple-redundant flight tube computer according to claim 4 is characterized in that: The module M2 comprises: Module M2.1: Based on the digital chip model and the hardware structure of the quadruple-redundant flight tube computer, a graphical construction method is used to complete the digital quadruple-redundant flight tube computer simulation modeling; Module M2.2: Complete the parameter settings and active / standby switching settings of each CPU according to the hardware settings in the real environment; Module M2.3: Load the binary software code written in the quadruple-redundant flight tube computer into the digital simulation environment according to the specified address; Module M2.4: Use the host clock as the time standard to complete the clock control of the other three CPUs.

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