MOS device and method for manufacturing the same

Abstract

The present application discloses a MOS device and a preparation method thereof, comprising a substrate and a drift layer on one side of the substrate, the drift layer having a first surface facing away from the substrate, a source region structure arranged in the drift layer and extending from the first surface to the substrate, the source region structure comprising a first injection region, a second injection region and a plurality of third injection regions, the first injection region being arranged at intervals in the drift layer and extending from the first surface to the substrate, the first injection region having a first side surface and a second side surface, the second injection region being in contact with the bottom surface and the first side surface of the first injection region respectively, the third injection region being arranged at intervals in the drift layer and extending from the first surface to the substrate, the third injection region being in contact with the second side surface, the bottom surface of at least one third injection region being in contact with the drift layer, the first injection region having a first doping type, and the second injection region and the third injection region having a second doping type. The invention solves the problem of low reliability of MOS devices caused by external FRD in the related art.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOS device and a method for preparing the same. Background Art

[0002] Silicon-based IGBTs dominate high-voltage and high-current scenarios, but they cannot withstand high-frequency conditions and have high power consumption. SiC's high-voltage and high-temperature resistance allows it to cover the voltage resistance level of silicon-based IGBTs with only simpler MOSFET devices, while avoiding its high energy consumption disadvantages. Under the same environment, silicon carbide-based MOSFETs reduce energy losses by 66% compared to silicon-based IGBTs of the same specifications, mainly due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used to drive and control inverters, on-board chargers, and fast charging piles for motors. In photovoltaic power generation, leading photovoltaic inverter companies have currently adopted SiC power devices to replace silicon devices.

[0003] In the prior art, in most high-power converter applications, MOS switch devices require a freewheeling diode to handle reverse current, but the parasitic diode in the traditional silicon MOSFET is not suitable for this purpose. Due to the minority carrier storage effect, the reverse recovery characteristics are poor, causing large switching power consumption. In practical applications, a fast recovery diode (FRD) is usually connected in reverse parallel to the source and drain of the MOSFET to suppress the conduction of the parasitic body diode and provide a new freewheeling path. However, the external FRD will increase the circuit module area and introduce additional parasitic parameters. Under large surge currents, existing devices are easily damaged at the source bonding wire connection due to high temperature, and the metal at the gate bus is also easily melted, resulting in low reliability of the device. Summary of the invention

[0004] The present application provides a MOS device and a method for manufacturing the same, so as to solve the problem of low reliability of the MOS device caused by an external FRD in the related art.

[0005] According to one aspect of the present application, a MOS device is provided, comprising a substrate and a drift layer on one side of the substrate, the drift layer having a first surface facing away from the substrate, the MOS device further comprising a plurality of cells, the cells being located on the side of the drift layer facing away from the substrate, the cells comprising: a source region structure, the source region structure being arranged in the drift layer and extending in a direction from the first surface to the substrate, the source region structure comprising a first injection region, a second injection region and a plurality of third injection regions, the first injection regions being arranged at intervals in the drift layer and extending in a direction from the first surface to the substrate, the first injection region having a first side surface and a second side surface, the second injection region being in contact with a bottom surface of the first injection region and the first side surface, respectively, the plurality of third injection regions being arranged at intervals in the drift layer and extending in a direction from the first surface to the substrate, the third injection region being in contact with the second side surface, the bottom surface of at least one of the third injection regions being in contact with the drift layer, the first injection region having a first doping type, and the second injection region and the third injection region having a second doping type.

[0006] Optionally, a depth of the third injection region in a first direction is greater than a depth of the second injection region, and the first direction is perpendicular to the first surface.

[0007] Optionally, the third injection region has different widths in a second direction, and the second direction is parallel to the first surface.

[0008] Optionally, the MOS device further includes: a fourth injection region, the fourth injection region is located in the drift layer and contacts a bottom surface of the second injection region, and the fourth injection region has a second doping type.

[0009] Optionally, the doping concentration of the third injection region and / or the fourth injection region is greater than the doping concentration of the second injection region.

[0010] Optionally, the MOS device also includes: a first conductive layer, which is located on the surface of the substrate and contacts the third injection region and a portion of the first injection region facing away from the substrate; and a second conductive layer, which is located on the surface of the substrate, covers the first conductive layer, and contacts the drift layer region between adjacent third injection regions and a portion of the first injection region facing away from the substrate.

[0011] Optionally, the MOS device further includes: a junction field effect transistor, the junction field effect transistor is located in the drift layer and extends from the first surface to the substrate, the source region structure is symmetrically arranged on both sides of the junction field effect transistor, and the junction field effect transistor is respectively in contact with the second injection region; or a gate trench structure, the gate trench structure is located in the drift layer and extends from the first surface to the substrate, the source region structure is symmetrically arranged on both sides of the gate trench structure, the gate trench structure is respectively in contact with the second injection region, the gate trench structure includes a gate and a gate oxide layer, and the gate oxide layer is respectively located between the gate and the drift layer and between the gate and the source region structure.

[0012] According to one aspect of the present application, a method for preparing a MOS device is provided, the steps of the preparation method comprising: providing a substrate; forming a drift layer on the substrate, the drift layer having a first surface facing away from the substrate; forming a source region structure, the source region structure being arranged in the drift layer and extending in a direction from the first surface to the substrate, the source region structure comprising a first injection region, a second injection region and a plurality of third injection regions, the first injection regions being arranged at intervals in the drift layer and extending in a direction from the first surface to the substrate, the first injection regions having a first side surface and a second side surface, the second injection regions respectively contacting a bottom surface of the first injection region and the first side surface, the third injection regions being arranged at intervals in the drift layer and extending in a direction from the first surface to the substrate, the third injection regions contacting the second side surface, the bottom surface of at least one of the third injection regions contacting the drift layer, the first injection region having a first doping type, and the second injection region and the third injection region having a second doping type.

[0013] Optionally, the step of forming the source region structure includes: using an ion implantation process to form a plurality of third implant regions in the drift layer, the third implant regions being alternately located in the drift layer and extending from the first surface in a direction pointing toward the substrate; using an ion implantation process to form a second implant region on a side of the starting third implant region away from the remaining third implant regions, the second implant region being in contact with a side wall of the starting third implant region, wherein the starting third implant region is a third implant region located at the edge of the plurality of third implant regions; and using an ion implantation process to form the first implant region in the second implant region, the first implant region being in contact with the third implant region.

[0014] Optionally, before forming the source region structure, it also includes: using an ion implantation process to form a fourth implantation region in the drift layer, the fourth implantation region has the first doping type, and after forming the source region structure, the fourth implantation region is located at the bottom surface of the second implantation region and contacts the second implantation region.

[0015] By applying the technical solution of the present application, a MOS device is provided, in which a plurality of third injection regions and a drift layer have different doping concentrations. After the MOS device is turned on, a PN junction structure is formed at the bottom of the third injection region, that is, a hybrid PiN / Schottky diode (Merge pin Schottky, MPS for short) is integrated inside the MOS device. When a large reverse current flows through the device, the on-state voltage drop of the transistor can be reduced, the junction temperature can be reduced, and current concentration can be suppressed to a certain extent, thereby improving the ability to resist surge current impact and the reliability of the MOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a schematic cross-sectional structure diagram of a MOS device according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a circuit structure of a MOS device according to an embodiment of the present application;

[0019] Figure 3 is a schematic cross-sectional structure diagram of another MOS device according to an embodiment of the present application;

[0020] Figure 4 is a schematic cross-sectional structure diagram of another MOS device according to an embodiment of the present application;

[0021] Figure 5 is a schematic cross-sectional structure diagram of another MOS device according to an embodiment of the present application;

[0022] Figure 6 A flow chart of a method for preparing a MOS device provided according to an embodiment of the present application is shown;

[0023] Figure 7 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in a method for preparing a MOS device provided in an embodiment of the present application is shown;

[0024] Figure 8 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in another method for preparing a MOS device provided in an embodiment of the present application is shown;

[0025] Fig. 9 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in another method for preparing a MOS device provided in an embodiment of the present application is shown;

[0026] Fig.10 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in a method for preparing a MOS device provided in an embodiment of the present application is shown.

[0027] The above drawings include the following reference numerals:

[0028] 10. Substrate; 20. Drift layer; 201. Drift layer region; 202. Preparatory drift layer; 30. Source region structure; 301. First injection region; 3011. First side; 3012. Second side; 302. Second injection region; 303. Third injection region; 3031. Starting third injection region; 3032. Remaining third injection regions; 304. Fourth injection region; 41. First conductive layer; 42. Second conductive layer; 43. Third conductive layer; 44. Fourth conductive layer; 51. Planar gate oxide layer; 52. Planar gate; 53. Trench gate oxide layer; 531. First trench; 532. Second trench; 54. Trench gate; 60. Dielectric layer; 70. Junction field effect transistor. DETAILED DESCRIPTION

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] As described in the background technology, in the MOS device in the prior art, the parasitic body diode is suppressed from conducting by connecting a fast recovery diode (FRD) in reverse parallel at both ends of the source and drain of the MOS device, and a new freewheeling path is provided. However, the external FRD increases the circuit module area and introduces additional parasitic parameters. Moreover, under large surge currents, the existing device is easily damaged at the source bonding wire connection due to high temperature, and the metal at the gate bus is also easily melted, resulting in low reliability of the device. In order to solve the above problems, the present application provides a MOS device and a preparation method thereof.

[0033] According to one aspect of the present application, a MOS device is provided, such as Figure 1 As shown, the MOS device includes a substrate 10 and a drift layer 20 on one side of the substrate 10, wherein the drift layer 20 has a first surface facing away from the substrate, and the MOS device further includes a plurality of cells, wherein the cells are located on the side of the drift layer 20 facing away from the substrate 10, and the cells include a source region structure 30, wherein the source region structure 30 is arranged in the drift layer 20 and extends from the first surface to the substrate 10, and the source region structure 30 includes a first injection region 301, a second injection region 302, and a plurality of third injection regions 303, wherein the first injection region 301 is arranged in the drift layer 20 and extends from the first surface to the substrate 10. The first injection region 301 has a first side surface 3011 and a second side surface 3012, the second injection region 302 is in contact with the bottom surface of the first injection region 301 and the first side surface 3011 respectively, the third injection region 303 is arranged in the drift layer 20 at intervals and extends from the first surface to the substrate 10, and the third injection region 303 is in contact with the second side surface 3012, the bottom surface of at least one third injection region 303 is in contact with the drift layer 20, the first injection region 301 has a first doping type, and the second injection region 302 and the third injection region 303 have a second doping type. The source region structure 30 in the device includes a plurality of third injection regions 303, and the third injection region 303 has a different doping concentration from the drift layer 20. After the MOS device is turned on, a PN junction structure is formed at the bottom of the third injection region 303, such as Figure 2 As shown, a hybrid PiN / Schottky diode (Merge pin Schottky, MPS for short) is integrated inside the MOS device. The MPS is connected to both ends of the source S and the drain D of the MOS device. The gate G can control the on-current of the device. When the device has a large reverse current, the gate G can be controlled while reducing the on-voltage drop of the transistor, reducing the junction temperature, and suppressing current concentration to a certain extent, thereby improving the ability to resist surge current impact and enhancing the reliability of the MOS device.

[0034] Specifically, the second injection region and the drift layer have different doping types to form a PN junction structure. When the MOS device is turned on, a depletion layer is formed at the junction of the second injection region and the drift layer, which prevents the free movement of external charges into the PN junction, thereby preventing the flow of current, shielding the electric field on the gate oxide surface, reducing the surface electric field strength, and improving the gate oxide reliability.

[0035] In some optional embodiments, such as Figure 1 As shown, the depth of the third implantation region 303 in the first direction A is greater than the depth of the second implantation region 302 , and the first direction A is perpendicular to the first surface.

[0036] Specifically, there are multiple third injection regions in the MOS device, that is, the MPS (Mergepin Schottky) structure integrated inside the MOS device, which has a rectifying effect. In the MPS structure, the second injection region has a deeper depth, and the depletion layer formed by the second injection region and the drift layer extends into the device. When the reverse bias increases, the maximum electric field position moves directly to the bottom of the second injection region, reducing the electric field on the gate oxide surface. In addition, multiple deep depletion layers disperse the electric field inside the MOS device, further reducing the electric field on the gate oxide surface.

[0037] In some optional embodiments, such as Figure 1 As shown, the third implantation region 303 has different widths in the second direction B, and the second direction B is parallel to the first surface.

[0038] Specifically, multiple third injection regions and drift layers form multiple PN junction structures. When the MOS device is turned on, multiple depletion layers are formed. Because the third injection regions have different widths in the second direction, the PN junctions have different contact areas. When the diode structure is forward biased and the current is large, multiple PN junction structures form multiple depletion layers. The multiple depletion layers have different areas, so that the multiple PN junction structures can transport different minority carriers. PN junctions with large contact areas can transport more minority carriers, and PN junctions with small contact areas can transport fewer minority carriers. Due to the conductivity modulation effect, PN junctions with large contact areas can more significantly reduce the resistance of the diode structure, thereby improving the surge resistance of the diode structure. However, PN junctions with large contact areas will increase the size of the device. Those skilled in the art can select them according to product performance, and this application does not make specific limitations.

[0039] In some optional embodiments, such as Figure 3 As shown, the MOS device further includes: a fourth implantation region 304 , which is located in the drift layer 20 and contacts the bottom surface of the second implantation region 302 , and has the second doping type. Figure 2 The positional relationship of other structures shown in Figure 1 The positional relationship of the structure is the same and will not be repeated here.

[0040] Specifically, the fourth injection region and the drift layer have different doping types, so the fourth injection region and the drift layer can form a PN junction structure. Under the action of the external electric field, the fourth injection region can form an electric field barrier, that is, when an electric field is formed in the fourth injection region, the charge will move along the conductive path of the material, which will have a counteracting effect on the energy of the electric field, and weaken the electric field in the internal area. The fourth injection region is formed at the bottom of the source region structure, which can reduce the electric field strength at the bottom of the source region structure and enhance the anti-breakdown property of the MOS device.

[0041] In some optional embodiments, the doping concentration of the third implantation region and / or the fourth implantation region is greater than the doping concentration of the second implantation region.

[0042] Specifically, the third injection region contacts the source electrode of the MOS device. On the basis that the third injection region has a high doping concentration, a metal-semiconductor structure can be formed with the source electrode. Depending on the doping concentration, a Schottky contact or an ohmic contact can be formed. In the Schottky contact, when the metal material and the semiconductor material are in contact, the energy band of the semiconductor material at the contact interface bends to form a Schottky barrier, so that a large number of carriers exist at the interface. Therefore, the Schottky contact can reduce the forward voltage drop of the diode structure and increase the breakdown voltage. The ohmic contact is based on the metal-semiconductor structure, and the semiconductor material has a high doping concentration. The carriers can pass through the barrier with the help of the tunnel effect. Therefore, the ohmic contact has a lower resistance and improves the surge resistance of the diode structure.

[0043] Specifically, the fourth injection region has a higher doping concentration, has better conductivity, higher stability and faster response speed inside the drift layer, and the fourth injection region and the drift layer form a depletion layer under the device conduction condition, which can shield the electric field on the surface of the gate oxide layer, reduce the surface electric field strength, and improve the gate oxide reliability;

[0044] In some optional embodiments, Figure 1 and Figure 3 As shown, the MOS device also includes: a first conductive layer 41, the first conductive layer 41 is located on the side of the third injection region 303 and a portion of the first injection region 301 away from the substrate 10; a second conductive layer 42, the second conductive layer 42 is located on the side of the drift layer region 201 and the first conductive layer 41 away from the substrate, and the drift layer region 201 is a portion of the drift layer 20 located between adjacent third injection regions 303.

[0045] In the above optional implementation, if Figure 1 and Figure 3As shown, the MOS device further includes: a planar gate oxide layer 51, the planar gate oxide layer 51 is located on the side of the preliminary drift layer 202 and the adjacent partial source region structure 30 away from the substrate, and the preliminary drift layer 202 is a partial region of the drift layer 20 located between the adjacent source region structures 30; a planar gate 52, the planar gate 52 is located on the side of the planar gate oxide layer 51 away from the substrate 10; a dielectric layer 60, the dielectric layer 60 is located on the side of the planar gate 52 and the adjacent partial source region structure 30 away from the substrate, and the dielectric layer 60 is in contact with the planar gate oxide layer 51, the planar gate 52, the first conductive layer 41 and the partial source region structure 30; and a third conductive layer 43, the third conductive layer 43 is located on the side of the substrate 10 away from the drift layer 20.

[0046] In some optional embodiments, such as Figures 1 to 4 As shown, the source region structure 30 is applied to a planar gate MOS device. Figure 4 As shown, the MOS device further includes: a junction field effect transistor 70, the junction field effect transistor 70 is located in the drift layer 20 and extends from the first surface to the substrate 10, the source region structure 30 is symmetrically arranged on both sides of the junction field effect transistor 70, and the junction field effect transistor 70 is respectively in contact with the second injection region 302, and in addition, Figure 4 The other structural position relationships shown in Figure 2 The positional relationship of the structures in is the same and will not be repeated here.

[0047] Specifically, the junction field effect transistor (JFET) is located between adjacent source region structures. The JFET uses the voltage applied to the gate terminal to control the current flowing between the drain and the source, so the output current is proportional to the gate input voltage. When a certain reverse bias voltage is applied to the gate, the channel of the JFET will be turned off. The input and output terminals of the JFET are highly isolated, making the MOS device more stable. JFET includes N-channel JFET and P-channel JFET. For the N-channel JFET, the carriers between its drain and source are electrons, and the corresponding turn-off voltage is a negative value, which has a lower resistance than the P-channel JFET. For the P-channel JFET, the carriers of its channel are holes, and the corresponding turn-off voltage is a positive value. It has a higher resistance value than its N-channel counterparts. Among them, the type of JFET is the same as the doping type of the drift layer, and the doping concentration of the JFET is 5×10 17 cm -3 ~1.5×10 18 cm -3 .

[0048] In other optional embodiments, such as Figure 5As shown, the above-mentioned source region structure 30 can be applied to a trench gate MOS device, and the MOS device further includes: a gate trench structure, the gate trench structure is located in the drift layer 20 and extends from the first surface toward the substrate 10, the source region structure 30 is symmetrically arranged on both sides of the gate trench structure, the gate trench structure is in contact with the second injection region 302 and the first injection region 301 respectively, the gate trench structure includes a trench gate 54 and a trench gate oxide layer 53, and the trench gate oxide layer 53 is respectively located between the trench gate 54 and the drift layer 20 and between the trench gate 54 and the source region structure 30.

[0049] Specifically, in the trench gate MOS device, since the MPS is integrated inside, the maximum electric field position is moved to the bottom surface of the third implantation region, so that the device has a higher reverse withstand voltage, thereby increasing the reliability of the trench gate MOS device.

[0050] In the above embodiment, if Figure 5 As shown, the trench gate MOS device further includes a fourth conductive layer 44, which is located on the side of the trench gate 54 away from the substrate 10; a dielectric layer 60, which is located on the side of the gate trench structure and the partial source region structure 30 located on both sides of the fourth conductive layer 44 away from the substrate. In addition, Figure 5 The positional relationship of other structures shown in Figure 2 The positional relationship of the structure is the same and will not be repeated here.

[0051] Specifically, the materials of the planar gate and the trench gate include but are not limited to doped polysilicon materials, wherein polysilicon is a polycrystalline material composed of small crystals, the arrangement of silicon atoms in polysilicon is non-directional, and there are multiple randomly arranged small grains. This special structure makes polysilicon have the properties of both metal and semiconductor, that is, it has good conductivity, and can also achieve specific electrical functions through doping. In MOS devices, the doped polysilicon and the drift layer have different doping types, and because polysilicon has metallic properties, the doped polysilicon and the drift layer form a heterojunction Schottky diode structure, which realizes the integration of SBD in MOS devices, reduces the resistance of the rectification structure, reduces the forward turn-on voltage drop of the diode structure without increasing the width of the SiC MOSFET cell, and shortens the reverse recovery time of the diode structure.

[0052] In some optional embodiments, such as Figure 1 and Figures 3 to 5 As shown, the first conductive layer 41, the second conductive layer 42, the third conductive layer 43, and the fourth conductive layer 44 include conductive materials, and the conductive materials include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0053] Among them, the first conductive layer contacts the third injection area to form a metal-semiconductor structure. Personnel in this field can match the metal material with the semiconductor material of the injection area to form an ohmic contact according to the functional requirements of the product to achieve the functional requirements of the product; the second conductive layer serves as the source electrode, the third conductive layer serves as the drain electrode, and the fourth conductive layer serves as the gate electrode, and they need to have good conductive properties to improve the current transmission efficiency of the MOS device.

[0054] Exemplarily, ohmic metals are commonly Ni, Ti or other materials. If Ni metal is used, NiSi is generally formed at 600℃~800℃ with a thickness of about 200nm~400nm, and then the unreacted Ni is stripped off with Ni etching solution, and high-temperature annealing is performed at 900℃~1000℃. The source and gate electrodes generally use Ti / AlCu materials, where the thickness of Ti is 50nm~2000nm and the thickness of AlCu is 2nm~6um.

[0055] Specifically, the first conductive layer and the second conductive layer have different work functions. The work function refers to the minimum energy required to move an electron from the inside to the surface, reflecting the ease with which the metal material loses ionization. The work function of the metal material determines the height of the electron barrier between the metal and the semiconductor material, and can affect the transmission properties of electrons in the contact area. In addition, there are multiple PN junction structures in the diode structure, and metal materials with low work functions can be flexibly selected as the metal structure in the Schottky contact.

[0056] In a specific embodiment, the first conductive layer is metal nickel, which has a work function of 4.6eV and a relatively high work function, and can easily form an ohmic contact with the semiconductor material to reduce the on-resistance and forward voltage drop of the diode structure; the third conductive part is metal aluminum 4.1eV, which has good conductivity and improves the current transmission efficiency of the MOS device.

[0057] According to another aspect of the present application, a method for preparing a MOS device is provided, such as Figure 6 As shown, the method comprises the following steps:

[0058] S101: providing a substrate;

[0059] S102: forming a drift layer on a substrate, wherein the drift layer has a first surface facing away from the substrate;

[0060] S103: forming a source region structure, wherein the source region structure is arranged in the drift layer and extends from the first surface to the substrate, the source region structure comprises a first injection region, a second injection region and a plurality of third injection regions, the first injection regions are arranged at intervals in the drift layer and extend from the first surface to the substrate, the first injection region has a first side surface and a second side surface, the second injection region contacts the bottom surface and the first side surface of the first injection region respectively, the third injection regions are arranged at intervals in the drift layer and extend from the first surface to the substrate, the third injection region contacts the second side surface, the bottom surface of at least one third injection region contacts the drift layer, the first injection region has a first doping type, and the second injection region and the third injection region have a second doping type.

[0061] The above-mentioned preparation method of the embodiment of the present application is adopted, and a multi-channel ion implantation process is adopted to form a source region structure, wherein the source region structure includes multiple third implantation regions, wherein the third implantation region and the drift layer have different doping concentrations. After the MOS device is turned on, a PN junction structure is formed at the bottom of the third implantation region, that is, a hybrid PiN / Schottky diode (Merge pin Schottky, referred to as MPS) is integrated inside the MOS device. When the device reverses a large current, the on-state voltage drop of the transistor can be reduced, the junction temperature can be reduced, and the current concentration can be suppressed to a certain extent, thereby improving the ability to resist surge current impact and improving the reliability of the MOS device.

[0062] The following will describe in more detail the exemplary embodiments of the method for preparing the trench MOSFET device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0063] First, proceed to step S101: Figure 7 (a) to Fig.10 As shown in (a), a substrate 10 is provided;

[0064] Specifically, the material of the substrate 10 may include silicon carbide material, or may include silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, aluminum nitride and other materials. Personnel in this field may make reasonable selections according to actual needs, and no specific limitation is made without application.

[0065] Exemplarily, the substrate includes a doped SiC substrate having a resistivity of 0.016 Ωcm-0.024 Ωcm, so as to form a Schottky contact at the source, reduce the forward voltage drop of the MOS device, and increase the breakdown voltage.

[0066] After the step of providing the substrate 10, step S102 is performed: Figure 7 (a) to Fig.10 As shown in (a), a drift layer 20 is formed on a substrate 10;

[0067] Specifically, the drift layer 20 may include an epitaxial layer having the same doping type as the substrate 10, and the doping concentration of the drift layer 20 is 10 15 cm -3 ~10 16 cm -3 , and the doping concentration of the drift layer 20 is lower than the doping concentration of the substrate, and bears the main breakdown voltage in the MOS device. In addition, those skilled in the art can adjust the thickness of the drift layer 20 to meet the breakdown voltage of the product. For example, when the thickness of the drift layer is 9μm~11μm, the breakdown voltage of the MOS device is 1200V, and when the thickness of the drift layer is 5μm~7μm, the breakdown voltage of the MOS device is 650V.

[0068] In some optional embodiments, the process of forming a drift layer includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0069] After the drift layer is formed, step S103 is performed to form a source region structure.

[0070] Specifically, the steps of forming the source region structure include: first, Figure 7 (b) Figure 8 (c) Fig. 9 (c) Fig.10 As shown in (c), a plurality of third implantation regions 303 are formed in the drift layer 20 by an ion implantation process. The third implantation regions 303 are alternately located in the drift layer 20 and extend from the first surface toward the substrate 10. Then, as shown in Figure 7 (c) Figure 8 (d) Fig. 9 (d) and Fig.10 As shown in (d), an ion implantation process is used to form a second implantation region 302 on a side of the starting third implantation region 3031 away from the remaining third implantation regions, and the second implantation region 302 is in contact with the third implantation region 303, wherein the starting third implantation region 3031 is a third implantation region 303 located at the edge of the plurality of third implantation regions 303, and the starting third implantation region 3031 and the remaining third implantation regions 3032 constitute a plurality of third implantation regions 303; then, as Figure 7 (d) Figure 8 (e) Fig. 9 (e) Fig.10 As shown in (e), the first implantation region 301 is formed in the second implantation region 302 by using an ion implantation process, and the first implantation region 301 is in contact with the third implantation region 303 .

[0071] Exemplarily, the doping concentration of the third injection region is greater than the doping concentration of the second injection region. Exemplarily, the doping concentration of the first injection region is 5×10 18 cm -3 ~1.5×10 19 cm -3 , the implantation depth is 0.9μm~1.8μm; the doping concentration of the second implantation region is 5×10 16 cm -3 ~1.5×10 17 cm -3 , the implantation depth is 0.7μm~0.8μm; the doping concentration of the third implantation region is 5×10 18 cm -3 ~1.5×10 19 cm -3 The injection depth is 0.9μm~1.8μm. Those skilled in the art can make a reasonable selection based on actual needs, and no specific limitation is made without application.

[0072] In some optional implementations, before forming the source region structure, the method further includes: Figure 8 (b) Fig. 9 (b) Fig.10As shown in (b), a fourth implantation region 304 is formed in the drift layer 20 by an ion implantation process. The fourth implantation region 304 has a first doping concentration. After the source region structure 30 is formed, the fourth implantation region 304 is located at the bottom surface of the second implantation region 302 and contacts the second implantation region 302 .

[0073] Specifically, the process of forming the first implantation area, the second implantation area, the third implantation area and the fourth implantation area includes but is not limited to the ion implantation process and the diffusion process, wherein the ion implantation process is to inject a high-energy ion beam into the semiconductor material, and is a process in which ions and semiconductor atoms collide and embed ions into the semiconductor crystal. The ion implantation process can accurately control the concentration and depth, and ion doping can be achieved at a lower temperature. The ion implantation equipment is expensive and the cost is high. The diffusion process is a process in which impurity atoms are allowed to diffuse freely along the thermal gradient of the crystal while maintaining thermal equilibrium in the semiconductor through high temperature or chemical reaction to achieve doping. The diffusion process does not require expensive equipment, requires higher control temperature and time conditions, and cannot accurately control the distribution and concentration of impurity atoms. Those skilled in the art can make reasonable selections according to actual needs, and no specific restrictions are made without application.

[0074] In the above embodiment, if Fig. 9 As shown in (f), an ion implantation process is used to form a junction field effect transistor 70 in the drift layer 20 located between adjacent source region structures 30, wherein the junction field effect transistor 70 controls the current flowing between the drain and the source by applying a voltage to the gate terminal, so the output current is proportional to the gate input voltage. When a certain reverse bias voltage is applied to the gate, the channel of the JFET will be turned off. The input and output terminals of the JFET are highly isolated, making the MOS device more stable. JFET includes N-channel JFET and P-channel JFET. For N-channel JFET, the carriers between its drain and source are electrons, and the corresponding turn-off voltage is a negative value, which has a lower resistance than the P-channel JFET. For P-channel JFET, the carriers in its channel are holes, and the corresponding turn-off voltage is a positive value. It has a higher resistance value than similar N-channel products. Among them, the type of JFET is the same as the doping type of the drift layer, and the doping concentration of JFET is 5×10 17 cm -3 ~1.5×10 18 cm -3 .

[0075] In the above embodiment, if Figure 7 (e) to Figure 7 (f) Figure 8 (f) to Figure 8 (g) Fig. 9 (g) to Fig. 9As shown in (h), the steps of forming the planar gate oxide layer 51 and the planar gate 52 include: first, Figure 7 (e) and Figure 8 As shown in (f), a planar gate oxide layer 51 is formed on the preliminary drift layer 202 and a portion of the source region structure 30 located on both sides of the preliminary drift layer 202. Fig. 9 As shown in (g), a planar gate oxide layer 51 is formed on the junction field effect transistor 70 and a portion of the source region structure 30 located on both sides of the junction field effect transistor 70 by a deposition process; then, as shown in Figure 7 (f) Figure 8 (g) and Fig. 9 As shown in (h), a planar gate 52 is formed on the side of the planar gate oxide layer 51 facing away from the substrate 10.

[0076] In another embodiment, Fig.10 (f) to Fig.10 As shown in (h), the steps of forming the trench gate oxide layer 53 and the trench gate 54 include: first, Fig.10 As shown in (f), an etching process is used to form a first trench 531 penetrating the source region structure 30 and extending to the drift layer 20; then, as shown in Fig.10 As shown in (g), an oxidation process is used to oxidize the sidewall of the first trench 531 to form a trench gate oxide layer 53, and the remaining area in the first trench 531 is the second trench 532; then, as shown in Fig.10 As shown in (h), a trench gate 54 is formed in the second trench 532 by a deposition process.

[0077] Specifically, the materials of the planar gate and the trench gate include but are not limited to doped polysilicon materials, wherein polysilicon is a polycrystalline material composed of small crystals, the arrangement of silicon atoms in polysilicon is non-directional, and there are multiple randomly arranged small grains. This special structure makes polysilicon have the properties of both metal and semiconductor, that is, it has good conductivity, and can also achieve specific electrical functions through doping. In MOS devices, the doped polysilicon and the drift layer have different doping types, and because polysilicon has metallic properties, the doped polysilicon and the drift layer form a heterojunction Schottky diode structure, which realizes the integration of SBD in MOS devices, reduces the resistance of the rectification structure, reduces the forward turn-on voltage drop of the diode structure without increasing the width of the SiC MOSFET cell, and shortens the reverse recovery time of the diode structure.

[0078] The above implementation also includes: Figure 7 (g) to Figure 7 (h) Figure 8 (h) to Figure 8 (i) Fig. 9 (i) to Fig. 9 (j) and Fig.10 (i) to Fig.10 As shown in (j), a first conductive layer 41, a second conductive layer 42, a third conductive layer 43, a fourth conductive layer 44 and a dielectric layer 60 are formed. Figure 7 (g) Figure 8 (h) Fig. 9 (i) and Fig.10 As shown in (i), a first conductive layer 41 is formed on a side of the source region structure 30 facing away from the substrate; then Figure 7 (h) Figure 8 (i) Fig. 9 As shown in (j), a second conductive layer 42 is formed on the side of the first conductive layer 41 and the drift layer 20 away from the substrate 10 by a deposition process, and the second conductive layer 42 is in contact with the dielectric layer 60, the drift layer 20 and the first conductive layer 41. A third conductive layer 43 is formed on the side of the substrate 10 away from the drift layer 20 by a deposition process. In addition, Fig.10 As shown in (i), a fourth conductive layer 44 is formed on the side of the trench gate 54 away from the substrate by a deposition process, and a silicon oxide material is deposited on the substrate by a deposition process to form a dielectric layer 60, and the dielectric layer 60 is respectively in contact with the trench gate 54, a part of the source region structure 30, the first conductive layer 41 and the second conductive layer 42; then, as shown in Fig.10 As shown in (j), a second conductive layer 42 is formed on the side of the first conductive layer 41 and the dielectric layer 60 away from the substrate 10 by a deposition process, and the second conductive layer 42 is in contact with the first conductive layer 41 and the dielectric layer 60 respectively. A third conductive layer 43 is formed on the side of the substrate 10 away from the drift layer 20 by a deposition process.

[0079] Specifically, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may include conductive materials, and the conductive materials include but are not limited to alloy materials composed of one or more of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals. Those skilled in the art can make reasonable selections based on actual needs, and this application does not make specific limitations.

[0080] Specifically, the first conductive layer contacts the first heavily doped region and part of the second heavily doped region, forming an ohmic contact to reduce the on-current of the MOS device. The second conductive layer and the third conductive layer serve as the source electrode and drain electrode of the MOS device, respectively, and play the role of current input and output of the MOS device. In the trench MOS device, the fourth conductive layer constitutes the gate electrode of the MOS device, and plays the role of controlling the charge density in the source channel, thereby controlling the current size of the MOS device.

[0081] Exemplarily, ohmic metals are commonly Ni, Ti or other materials. If Ni metal is used, NiSi is generally formed at 600℃~800℃ with a thickness of about 200nm~400nm, and then the unreacted Ni is stripped off with Ni etching solution, and high-temperature annealing is performed at 900℃~1000℃. The source and gate electrodes generally use Ti / AlCu materials, where the thickness of Ti is 50nm~2000nm and the thickness of AlCu is 2nm~6um.

[0082] In addition, the gate material may include a doped polysilicon material, the doping type of the gate is different from the doping type of the drift layer, and the doping concentration of the gate material is 10 19 cm -3 ~10 20 cm -3 Doped polysilicon material has high electrical conductivity and can withstand large current and voltage. In addition, polysilicon material has good stability and compatibility. Using doped polysilicon material as gate material can improve the conductivity and stability of MOS devices.

[0083] The MOS device formed by the MOS device preparation method of the present application will be described below in conjunction with an embodiment.

[0084] Example 1

[0085] The method for preparing the planar gate MOS device provided in this embodiment comprises the following steps: Figure 7 As shown:

[0086] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Figure 7 (a) as shown;

[0087] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 cm -3 ,like Figure 7 (a) as shown;

[0088] A plurality of P-type third implantation regions 303 are formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, such as Figure 7 (b) as shown;

[0089] An ion implantation process is used to form a P-type second implantation region 302 on the side of the starting third implantation region 3031 away from the remaining third implantation regions 3032, with a doping concentration of 10 17 cm -3 , with a depth of 0.7 μm, such as Figure 7 (c) as shown;

[0090] An ion implantation process is used to form an N-type first implantation region 301 in the second implantation region 302. The N-type first implantation region 301 is in contact with the P-type starting third implantation region 3031. The doping concentration is 10 19 cm -3 , with a depth of 0.2 μm, such as Figure 7 (d) as shown;

[0091] SiO2 is deposited on the preliminary drift layer 202 and the partial source region structure 30 located on both sides of the preliminary drift layer 202 by a deposition process to form a planar gate oxide layer 51. Figure 7 (e) as shown;

[0092] A polysilicon material is deposited on the side of the planar gate oxide layer 51 away from the substrate 10 by a deposition process to form a planar gate 52. Figure 7 (f) as shown;

[0093] A dielectric layer 60 is formed on the planar gate oxide layer 51 and a portion of the source region structure 30 by a deposition process. Figure 7 (g) as shown;

[0094] A metal nickel material is deposited on the side of the partial source region structure 30 away from the substrate 10 by a deposition process to form a first conductive layer 41. The first conductive layer 41 is in contact with the third injection region 303 and the partial source region structure 30. Figure 7 (g) as shown;

[0095] A metal aluminum material is deposited on the first conductive layer 41 and the drift layer 20 on the side away from the substrate by a deposition process to form a second conductive layer 42. The second conductive layer 42 is in contact with the dielectric layer, the drift layer 20 and the first conductive layer 41. Figure 7 (h) as shown;

[0096] A metal aluminum material is deposited on the side of the substrate 10 away from the drift layer 20 by a deposition process to form a third conductive layer 43. Figure 7 (h) shown.

[0097] Example 2

[0098] The method for preparing the planar gate MOS device provided in this embodiment comprises the following steps: Figure 8 As shown:

[0099] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Figure 8 (a) as shown;

[0100] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 cm-3 ,like Figure 8 (a) as shown;

[0101] The P-type fourth implantation region 304 is formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, such as Figure 8 (b) as shown;

[0102] A plurality of P-type third implantation regions 303 are formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, the third injection region 303 is located on one side of the P-type fourth injection region 304, such as Figure 8 (c) as shown;

[0103] An ion implantation process is used to form a P-type second implantation region 302 on the side of the starting third implantation region 3031 away from the remaining third implantation regions 3032, with a doping concentration of 10 17 cm -3 , with a depth of 0.7 μm, the P-type second injection region 302 is in contact with the fourth injection region 304, such as Figure 8 (d) as shown;

[0104] An N-type first implantation region 301 is formed in the P-type second implantation region 302 by an ion implantation process. The N-type first implantation region is in contact with the P-type starting third implantation region 3031. The doping concentration of the N-type first implantation region 301 is 10 19 cm -3 , with a depth of 0.2 μm, such as Figure 8 (e) as shown;

[0105] SiO2 is deposited on the preliminary drift layer 202 and the partial source region structures 30 located on both sides of the preliminary drift layer 202 by a deposition process to form a planar gate oxide layer 51, wherein the preliminary drift layer 202 is a partial region of the drift layer 20 located between adjacent source region structures 30, such as Figure 8 (f) as shown;

[0106] A polysilicon material is deposited on the side of the planar gate oxide layer 51 away from the substrate 10 by a deposition process to form a planar gate 52. Figure 8 (g) as shown;

[0107] A dielectric layer 60 is formed on the planar gate oxide layer 51 and a portion of the source region structure 30 by a deposition process. Figure 8 (h) as shown;

[0108] A metal nickel material is deposited on the side of the partial source region structure 30 away from the substrate 10 by a deposition process to form a first conductive layer 41. The first conductive layer 41 is in contact with the third injection region 303 and the partial source region structure 30. Figure 8 (h) as shown;

[0109] A metal aluminum material is deposited on the first conductive layer 41 and the drift layer 20 on the side away from the substrate by a deposition process to form a second conductive layer 42. The second conductive layer 42 is in contact with the dielectric layer, the drift layer 20 and the first conductive layer 41. Figure 8 (i) as shown;

[0110] A metal aluminum material is deposited on the side of the substrate 10 away from the drift layer 20 by a deposition process to form a third conductive layer 43. Figure 8 (i) shown.

[0111] Example 3

[0112] The method for preparing the planar gate MOS device provided in this embodiment comprises the following steps: Fig. 9 As shown:

[0113] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Fig. 9 (a) as shown;

[0114] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 cm -3 ,like Fig. 9 (a) as shown;

[0115] The P-type fourth implantation region 304 is formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, such as Fig. 9 (b) as shown;

[0116] A plurality of P-type third implantation regions 303 are formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, the third injection region 303 is located on one side of the P-type fourth injection region 304, such as Fig. 9 (c) as shown;

[0117] An ion implantation process is used to form a P-type second implantation region 302 on the side of the starting third implantation region 3031 away from the remaining third implantation regions 3032, with a doping concentration of 10 17 cm -3, with a depth of 1.7 μm, the second injection region 302 is in contact with the fourth injection region 304, such as Fig. 9 (d) as shown;

[0118] An ion implantation process is used to form an N-type first implantation region 301 in the second implantation region 302. The N-type first implantation region is in contact with the P-type third implantation region 303, and the doping concentration is 10 19 cm -3 , with a depth of 0.2 μm, such as Fig. 9 (e) as shown;

[0119] The P-type junction field effect transistor 70 is formed in the preliminary drift layer by ion implantation process, and the doping concentration is 10 17 cm -3 , with a depth of 0.7 μm, such as Fig. 9 (f) as shown;

[0120] SiO2 is deposited on the P-type junction field effect transistor 70 and a portion of the source region structure 30 located on both sides of the P-type junction field effect transistor 70 by a deposition process to form a planar gate oxide layer 51, as shown in FIG. Fig. 9 (g) as shown;

[0121] A polysilicon material is deposited on the side of the planar gate oxide layer 51 away from the substrate 10 by a deposition process to form a planar gate 52. Fig. 9 (h) as shown;

[0122] A dielectric layer 60 is formed on the planar gate oxide layer 51 and the adjacent portion of the source region structure 30 by a deposition process. Fig. 9 (i) as shown;

[0123] A metal nickel material is deposited on the side of the partial source region structure 30 away from the substrate 10 by a deposition process to form a first conductive layer 41. The first conductive layer 41 is in contact with the third injection region 303 and the partial source region structure 30. Fig. 9 (i) as shown;

[0124] A metal aluminum material is deposited on the first conductive layer 41 and the drift layer 20 on the side away from the substrate 10 by a deposition process to form a second conductive layer 42. The second conductive layer 42 is in contact with the dielectric layer 60, the drift layer 20 and the first conductive layer 41. Fig. 9 (j) as shown;

[0125] A metal aluminum material is deposited on the side of the substrate 10 away from the drift layer 20 by a deposition process to form a third conductive layer 43. Fig. 9 (j) shown.

[0126] Example 4

[0127] The method for preparing the planar gate MOS device provided in this embodiment comprises the following steps: Fig.10 As shown:

[0128] Provide an N-type SiC substrate 10, whose resistivity is 0.02Ωcm, such as Fig.10 (a) as shown;

[0129] An N-type SiC drift layer 20 is formed on an N-type SiC substrate 10 by using an epitaxial growth process. The doping concentration of the N-type SiC drift layer 20 is 10 15 cm -3 ,like Fig.10 (a) as shown;

[0130] The P-type fourth implantation region 304 is formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, such as Fig.10 (b) as shown;

[0131] A plurality of P-type third implantation regions 303 are formed in the N-type SiC drift layer 20 by an ion implantation process, and the doping concentration is 10 19 cm -3 , with a depth of 1.2 μm, the third injection region 303 is located on one side of the P-type fourth injection region 304, such as Fig.10 (c) as shown;

[0132] An ion implantation process is used to form a P-type second implantation region 302 on the side of the starting third implantation region 3031 away from the remaining third implantation regions 3032, with a doping concentration of 10 17 cm -3 , with a depth of 1.7 μm, the second injection region 302 is in contact with the fourth injection region 304, such as Fig.10 (d) as shown;

[0133] An ion implantation process is used to form an N-type first implantation region 301 in the second implantation region 302. The N-type first implantation region is in contact with the P-type third implantation region 303. The doping concentration of the first implantation region 301 is 10 19 cm -3 , with a depth of 0.2 μm, such as Fig.10 (e) as shown;

[0134] A first trench 531 penetrating the source region structure 30 and extending to the N-type SiC drift layer 20 is formed in the above structure by an etching process. The first trench 531 has a depth of 1.3 μm and a width of 0.8 μm. Fig.10 (f) as shown;

[0135] The sidewall of the first trench 531 is oxidized by an oxidation process to form a trench gate oxide layer 53. The thickness of the trench gate oxide layer 53 is 0.05 μm. The remaining area in the first trench is the second trench 532. Fig.10 (g) as shown;

[0136] A deposition process is used to fill the second trench 532 with polysilicon material to form a trench gate 54. Fig.10 (h) as shown;

[0137] A metal nickel material is deposited on a side of the source region structure 30 away from the substrate 10 by a deposition process to form a first conductive layer 41. Fig.10 (i) as shown;

[0138] A metal aluminum material is deposited on the side of the trench gate 54 away from the substrate by a deposition process to form a fourth conductive layer 44. Fig.10 (i) as shown;

[0139] A silicon oxide material is deposited on the substrate by a deposition process to form a dielectric layer 60. The dielectric layer 60 is in contact with the trench gate 54, a portion of the source region structure 30, the first conductive layer 41 and the second conductive layer 42, respectively. Fig.10 (i) as shown;

[0140] A metal aluminum material is deposited on the side of the first conductive layer 41 and the dielectric layer 60 facing away from the substrate 10 by a deposition process to form a second conductive layer 42. The second conductive layer 42 is in contact with the first conductive layer 41 and the dielectric layer 60, respectively. Fig.10 (j) as shown;

[0141] A metal aluminum material is deposited on the side of the substrate 10 away from the drift layer 20 by a deposition process to form a third conductive layer 43. Fig.10 (i) shown.

[0142] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0143] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A MOS device, characterized in that: The MOS device comprises a substrate and a drift layer on one side of the substrate, wherein the drift layer has a first surface facing away from the substrate, and the MOS device further comprises a plurality of cells, wherein the cells are located on a side of the drift layer facing away from the substrate, and the cells comprise: a source region structure, the source region structure being arranged in the drift layer and extending in a direction from the first surface to the substrate, the source region structure comprising a first injection region, a second injection region and a plurality of third injection regions, the first injection region being arranged in the drift layer and extending in a direction from the first surface to the substrate, the first injection region having a first side surface and a second side surface, the second injection region respectively contacting a bottom surface of the first injection region and the first side surface, the plurality of third injection regions being arranged at intervals in the drift layer and extending in a direction from the first surface to the substrate, the second side surface contacting one of the third injection regions, the bottom surface of at least one of the third injection regions contacting the drift layer, the first injection region having a first doping type, and the second injection region and the third injection region having a second doping type; A fourth injection region is located in the drift layer and contacts a bottom surface of the second injection region, and the fourth injection region has a second doping type.

2. The MOS device according to claim 1, characterized in that: The depth of the third injection region is greater than the depth of the second injection region in a first direction, and the first direction is perpendicular to the first surface.

3. The MOS device according to claim 1, characterized in that: The third implantation region has different widths in a second direction, and the second direction is parallel to the first surface.

4. The MOS device according to any one of claims 1 to 3, characterized in that: The doping concentration of the third implantation region and / or the fourth implantation region is greater than the doping concentration of the second implantation region.

5. The MOS device according to claim 1, characterized in that: The MOS device further comprises: A first conductive layer, the first conductive layer is located on the surface of the substrate and is in contact with the third injection region and a portion of the first injection region facing away from the substrate; A second conductive layer is located on the surface of the substrate, covers the first conductive layer, and contacts the drift layer region between the adjacent third injection regions and a portion of the first injection region facing away from the substrate.

6. The MOS device according to claim 1, characterized in that: The MOS device further comprises: A junction field effect transistor, wherein the junction field effect transistor is located in the drift layer and extends from the first surface to the substrate, the source region structure is symmetrically arranged on both sides of the junction field effect transistor, and the junction field effect transistor is in contact with the second injection region respectively; or A gate trench structure, wherein the gate trench structure is located in the drift layer and extends from the first surface to the direction of the substrate, the source region structure is symmetrically arranged on both sides of the gate trench structure, the gate trench structure is respectively in contact with the second injection region, the gate trench structure includes a gate and a gate oxide layer, and the gate oxide layer is respectively located between the gate and the drift layer and between the gate and the source region structure.

7. A method for preparing a MOS device, characterized in that: Used to prepare the MOS device according to any one of claims 1 to 6, the preparation method comprising the steps of: providing a substrate; forming a drift layer on the substrate, the drift layer having a first surface facing away from the substrate; forming a source region structure, wherein the source region structure is arranged in the drift layer and extends in a direction from the first surface to the substrate, the source region structure comprises a first injection region, a second injection region and a plurality of third injection regions, the first injection region is arranged in the drift layer and extends in a direction from the first surface to the substrate, the first injection region has a first side surface and a second side surface, the second injection region contacts the bottom surface of the first injection region and the first side surface respectively, the third injection regions are arranged in the drift layer at intervals and extend in a direction from the first surface to the substrate, the third injection regions contact the second side surface, the bottom surface of at least one of the third injection regions contacts the drift layer, the first injection region has a first doping type, and the second injection region and the third injection region have a second doping type; A fourth injection region is formed, wherein the fourth injection region is located in the drift layer and contacts a bottom surface of the second injection region, and the fourth injection region has a second doping type.

8. The preparation method according to claim 7, characterized in that: The steps of forming the source region structure include: forming a plurality of third implantation regions in the drift layer by an ion implantation process, wherein the third implantation regions are alternately located in the drift layer and extend from the first surface to the substrate; Using an ion implantation process, a second implantation region is formed on a side of the starting third implantation region away from the remaining third implantation regions, wherein the second implantation region contacts a sidewall of the starting third implantation region, wherein the starting third implantation region is a third implantation region located at an edge of the plurality of third implantation regions; The first implantation region is formed in the second implantation region by using an ion implantation process, and the first implantation region is in contact with the third implantation region.

9. The preparation method according to claim 7, characterized in that: Before forming the source region structure, the method further comprises: An ion implantation process is used to form a fourth implantation region in the drift layer, the fourth implantation region has the first doping type, and after the source region structure is formed, the fourth implantation region is located at the bottom surface of the second implantation region and contacts the second implantation region.

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