On-chip process angle monitoring unit and method based on ring oscillator structure

Abstract

The present invention relates to the field of integrated circuit design, and proposes an on-chip process angle monitoring unit and method based on a ring oscillator structure, wherein the monitoring unit includes a process sensing module and a frequency counting module; the process sensing module is signal-connected to the frequency counting module, and is used to generate an oscillation signal affected by process changes and temperature changes through an oscillator; the frequency counting module is signal-connected to the process sensing module, and is used to count and process the oscillation signal output by the process sensing module. The process conditions of the chip after manufacturing are measured by using the circuit structure of the ring oscillator, and two different ring oscillator circuits are designed so that the two oscillators have the same temperature characteristics but different process sensitivities, and the temperature correlation of the measurement results is eliminated by using the frequency difference method.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an on-chip process angle monitoring unit and method based on a ring oscillator structure. Background Art

[0002] With the development of semiconductors, process feature sizes are shrinking, chip integration is increasing, and the complexity of integrated circuit design and manufacturing is also increasing. When device feature sizes reach the nanometer scale, the process has a significant impact on device performance, seriously restricting the performance, power consumption, and yield of integrated circuits. To detect process changes, process angle monitors have been widely researched.

[0003] Traditional monitoring methods usually rely on external equipment and ignore the impact of temperature on measurement results, which not only increases the area cost of the monitoring unit but also leads to large measurement errors due to temperature changes. Summary of the Invention

[0004] In view of this, the present invention proposes an on-chip process angle monitoring unit and method based on a ring oscillator structure. By adopting two oscillators with different sensitivities to process changes and temperature, a control experiment is carried out to eliminate the influence of temperature on the measurement results, accurately monitor process changes, and solve the problem that existing monitoring methods are greatly affected by temperature changes.

[0005] The technical solution of the present invention is implemented as follows: On the one hand, the present invention provides an on-chip process angle monitoring unit based on a ring oscillator structure, wherein the monitoring unit includes a process sensing module and a frequency counting module;

[0006] The process sensing module is signal-connected to the frequency counting module and is used to generate an oscillation signal affected by process variation and temperature variation through an oscillator;

[0007] The frequency counting module is signal-connected to the process sensing module and is used to count and process the oscillation signal output by the process sensing module.

[0008] On the basis of the above technical solution, preferably, the process sensing module includes a demultiplexer, a first oscillator, a second oscillator, and a multiplexer;

[0009] The demultiplexer is signal-connected to the first oscillator and the second oscillator, and is used to output a start signal START1 to the first oscillator or the second oscillator;

[0010] The first oscillator is signal-connected to the demultiplexer and the multiplexer, and is used to output an oscillation signal with low sensitivity to process variations;

[0011] The second oscillator is signal-connected to the demultiplexer and the multiplexer, and is used to output an oscillation signal with high sensitivity to process variations;

[0012] The multiplexer is signal-connected to the first oscillator, the second oscillator, and the frequency counting module, and is used to transmit the oscillation signal output by the first oscillator or the second oscillator to the frequency counting module.

[0013] On the basis of the above technical solution, preferably, the first oscillator includes a plurality of first delay units;

[0014] The first delay unit includes NMOS tubes N0, N1, N2, N3, and PMOS tubes P0, P1;

[0015] The gate of the NMOS transistor N0 is connected to the VCC voltage, the drain of the NMOS transistor N0 and the gate of the PMOS transistor P0 are connected to the start signal START1, the source of the NMOS transistor N0 is electrically connected to the gate of the NMOS transistor N1, the source of the PMOS transistor P0 is connected to the VCC voltage, the drain of the PMOS transistor P0 is electrically connected to the source of the NMOS transistor N1, the gate of the PMOS transistor P1, and the drain of the NMOS transistor N2, the drain of the NMOS transistor N1 is grounded, the gate of the NMOS transistor N2 is connected to the VCC voltage, the source of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N3, the source of the PMOS transistor P1 is connected to the VCC voltage, the drain of the NMOS transistor N3 is grounded, and the drain of the PMOS transistor P1 and the source of the NMOS transistor N3 output an oscillation signal.

[0016] On the basis of the above technical solution, preferably, the second oscillator includes a plurality of second delay units;

[0017] The second delay unit includes NMOS transistors N4, N5, N6, N7, N8, N9, N10, N11, and PMOS transistors P2 and P3;

[0018] The gate of the PMOS transistor P2, the gate of the NMOS transistor N4, and the drain of the NMOS transistor N5 are connected to the start signal START1, the source of the PMOS transistor P2 is connected to the VCC voltage, the drain of the PMOS transistor P2 is electrically connected to the source of the NMOS transistor N4 and the gate of the NMOS transistor N7, the drain of the NMOS transistor N4 is grounded, the gate of the NMOS transistor N5 is connected to the VCC voltage, the source of the NMOS transistor N5 is electrically connected to the gate of the NMOS transistor N6, the drain of the NMOS transistor N6 is grounded, the source of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N7, the gate of the PMOS transistor P3, The gate of the NMOS transistor N8 and the drain of the NMOS transistor N9 are electrically connected, the source of the NMOS transistor N7 is connected to the VCC voltage, the source of the PMOS transistor P3 is connected to the VCC voltage, the drain of the PMOS transistor P3 is electrically connected to the source of the NMOS transistor N8 and the gate of the NMOS transistor N11, the source of the NMOS transistor N11 is connected to the VCC voltage, the drain of the NMOS transistor N8 is grounded, the source of the NMOS transistor N9 is electrically connected to the gate of the NMOS transistor N10, the drain of the NMOS transistor N10 is grounded, and the source of the NMOS transistor N10 and the drain of the NMOS transistor N11 output an oscillation signal.

[0019] On the basis of the above technical solution, preferably, the NMOS transistor N0 adopts a normal threshold transistor with a width-to-length ratio of 120:60, the NMOS transistor N1 adopts a high threshold transistor with a width-to-length ratio of 120:360, and the PMOS transistor adopts an ultra-high threshold transistor with a width-to-length ratio of 120:360;

[0020] The NMOS transistors N5, N6, and N7 are ordinary threshold transistors with a width-to-length ratio of 120:240, the NMOS transistor N4 is an ultra-high threshold transistor with a width-to-length ratio of 120:240, and the PMOS transistor P2 is an ultra-high threshold transistor with a width-to-length ratio of 120:180.

[0021] On the basis of the above technical solution, preferably, the frequency counting module includes a 12-bit counter, a 16-bit counter, and a four-to-one multiplexer;

[0022] The 12-bit counter is connected to the four-to-one multiplexer signal and is used to count the reference clock;

[0023] The 16-bit counter is connected to the four-to-one multiplexer signal and is used to count the number of pulses of the oscillation signal;

[0024] The four-to-one multiplexer is connected to the 12-bit counter signal and is used to output a counting time control signal.

[0025] On the other hand, the present invention also provides an on-chip process angle monitoring method based on a ring oscillator structure, comprising:

[0026] S1, receives the oscillator selection signal RO Select and the start signal START1 through the demultiplexer;

[0027] S2, set the oscillator selection signal RO Select to 0, and set the start signal START1 to 1, output the start signal START1 to the first oscillator through the demultiplexer, after the first oscillator oscillates stably, input the reset signal to the frequency counting module, output the first oscillation signal to the frequency counting module through the first oscillator, set the start signal START2 to 1 and input it to the frequency counting module, wait for a preset time period, and then record the first counting frequency of the frequency counting module;

[0028] S3, setting the oscillator selection signal RO Select to 1, and setting the start signal START1 to 1, outputting the start signal START1 to the second oscillator through the demultiplexer, inputting the reset signal to the frequency counting module after the second oscillator oscillates stably, outputting the second oscillation signal to the frequency counting module through the second oscillator, setting the start signal START2 to 1 and inputting it to the frequency counting module, waiting for a preset time period, and recording the second counting frequency of the frequency counting module;

[0029] S4: Calculate a process angle calibration reference frequency based on the first counting frequency and the second counting frequency.

[0030] Based on the above technical solution, preferably, the frequency counting module sends a counting time control signal [S0, S1] to a 12-bit counter through a four-to-one multiplexer, reads the reference clock through the 12-bit counter, and reads the oscillator clock through the 16-bit counter. The calculation formula of the control signal is:

[0031]

[0032] When the count time control signal is 00, select Q8 of the 12-bit counter; when the count time control signal is 01, select Q9 of the 12-bit counter; when the count time control signal is 10, select Q 10 When the count time control signal is 11, select Q of the 12-bit counter. 11 Bit.

[0033] On the basis of the above technical solution, preferably, the first counting frequency and the second counting frequency are read by the values ​​of the 12-bit counter and the 16-bit counter of the frequency counting module, and the calculation formula is:

[0034]

[0035] Among them, f osc1 is the first counting frequency, fosc2 is the second counting frequency, M1 is the value of the 16-bit counter when the first oscillator starts, M2 is the value of the 16-bit counter when the second oscillator starts, n1 is the number of bits selected by the 12-bit counter when the first oscillator starts, n2 is the number of bits selected by the 12-bit counter when the second oscillator starts, f ref1 The reference clock frequency of the 12-bit counter input when the first oscillator starts, f ref2 This is the reference clock frequency for the 12-bit counter input when the second oscillator is started.

[0036] Based on the above technical solution, preferably, step S4 includes:

[0037] Based on the first counting frequency f osc1 and the second counting frequency f osc2 The process angle calibration reference frequency Q is obtained by subtracting the process angle calibration reference frequency Q, and the process angle distribution of the chip is obtained by comparing the process angle calibration reference frequency Q with the values ​​obtained by simulating the chip at different process angles.

[0038] The on-chip process angle monitoring unit and method based on a ring oscillator structure of the present invention have the following beneficial effects compared with the prior art:

[0039] (1) The process conditions of the manufactured chip are measured by using the circuit structure of a ring oscillator. Two different ring oscillator circuits are designed so that the two oscillators have the same temperature characteristics but different process sensitivities. The temperature dependence of the measurement results is eliminated by using a frequency difference method.

[0040] (2) The oscillation signal is counted and processed by the frequency counting module, which reduces the measurement error caused by temperature changes and improves the measurement accuracy;

[0041] (3) The process conditions of the chip after manufacturing are measured through the circuit structure of the ring oscillator, which realizes on-chip process corner monitoring and reduces the dependence on external equipment. The oscillator is used to generate an oscillation signal affected by process changes and temperature changes. Combined with the processing of the frequency counting module, the process conditions of the on-chip process corner can be efficiently perceived and analyzed. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1This is a structural diagram of an on-chip process angle monitoring unit based on a ring oscillator structure according to the present invention;

[0044] Figure 2 This is a structural diagram of an oscillator of an on-chip process angle monitoring unit based on a ring oscillator structure according to the present invention;

[0045] Figure 3 This is a structural diagram of a first delay unit of an on-chip process angle monitoring unit based on a ring oscillator structure of the present invention;

[0046] Figure 4 This is a structural diagram of a second delay unit of an on-chip process angle monitoring unit based on a ring oscillator structure of the present invention;

[0047] Figure 5 This is a structural diagram of a frequency counting module of an on-chip process angle monitoring unit based on a ring oscillator structure of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0049] See also Figure 1 , the present invention provides an on-chip process angle monitoring unit based on a ring oscillator structure, the monitoring unit includes a process perception module 1 and a frequency counting module 2;

[0050] The process sensing module 1 is signal-connected to the frequency counting module 2 and is used to generate an oscillation signal affected by process variation and temperature variation through an oscillator;

[0051] The frequency counting module 2 is signal-connected to the process sensing module 1 and is used to count and process the oscillation signal output by the process sensing module.

[0052] Specifically, the monitoring unit measures the process conditions of the chip after manufacturing by using the circuit structure of a ring oscillator. Two different ring oscillator circuits are designed so that the two oscillators have the same temperature characteristics but different process sensitivities. The temperature correlation of the measurement results is eliminated by frequency difference.

[0053] The entire monitoring unit circuit consists of two parts: process sensing module 1 and frequency counting module 2. Process sensing module 1 uses a ring oscillator circuit to sense the chip's process conditions, whose oscillation frequency contains process information. The frequency counting module counts pulses in the oscillator's output waveform over a certain period of time and calculates its output frequency. Finally, the difference between the two oscillator output frequencies is used to eliminate the influence of temperature and obtain a frequency that represents process variations.

[0054] See also Figure 1 , the process sensing module 1 includes a demultiplexer 11, a first oscillator 12, a second oscillator 13, and a multiplexer 14;

[0055] The demultiplexer 11 is signal-connected to the first oscillator 12 and the second oscillator 13, and is configured to output a start signal START1 to the first oscillator 12 or the second oscillator 13;

[0056] The first oscillator 12 is signal-connected to the demultiplexer 11 and the multiplexer 14, and is used to output an oscillation signal with low sensitivity to process variations;

[0057] The second oscillator 13 is signal-connected to the demultiplexer 11 and the multiplexer 14, and is used to output an oscillation signal with high sensitivity to process variations;

[0058] The multiplexer 14 is signal-connected to the first oscillator 12 , the second oscillator 13 , and the frequency counting module 2 , and is configured to transmit the oscillation signal output by the first oscillator 12 or the second oscillator 13 to the frequency counting module 2 .

[0059] See also Figure 2 , the first oscillator 12 includes a plurality of first delay units;

[0060] See also Figure 3 , the first delay unit includes NMOS tubes N0, N1, N2, N3, and PMOS tubes P0 and P1;

[0061] The gate of the NMOS transistor N0 is connected to the VCC voltage, the drain of the NMOS transistor N0 and the gate of the PMOS transistor P0 are connected to the start signal START1, the source of the NMOS transistor N0 is electrically connected to the gate of the NMOS transistor N1, the source of the PMOS transistor P0 is connected to the VCC voltage, the drain of the PMOS transistor P0 is electrically connected to the source of the NMOS transistor N1, the gate of the PMOS transistor P1, and the drain of the NMOS transistor N2, the drain of the NMOS transistor N1 is grounded, the gate of the NMOS transistor N2 is connected to the VCC voltage, the source of the NMOS transistor N2 is electrically connected to the gate of the NMOS transistor N3, the source of the PMOS transistor P1 is connected to the VCC voltage, the drain of the NMOS transistor N3 is grounded, and the drain of the PMOS transistor P1 and the source of the NMOS transistor N3 output an oscillation signal.

[0062] Specifically, the oscillator of this embodiment consists of a NAND gate and several delay units connected end to end. When the START signal is 0, the output of the NAND gate is 1 regardless of the value of the other input. This logical 1 propagates backward, causing the input and output ports of each delay unit to be high. At this time, the oscillator is locked in this state and does not oscillate. When the START signal changes from 0 to 1, since both inputs of the NAND gate are 1, the output of the NAND gate is 0. The logical 0 is transmitted through the delay unit and reaches the input of the NAND gate. At this time, the two inputs of the NAND gate are logical 1 and 0, so the output of the NAND gate becomes 1. Thereafter, the logic of the circuit flips at regular intervals, generating oscillations. The oscillation frequency depends on the propagation delay of the logic signal in the loop, which is affected by process variations.

[0063] When designing the circuits of the two oscillators, the key is to ensure that the two ring oscillators have different process sensitivities and are consistent in temperature characteristics. The goal is to cancel out only temperature-related variables during frequency differentiation without canceling out frequency-related process variable information. In this example, the first oscillator 12 is designed to have low process sensitivity. The specific circuit structure of the first delay unit is as follows: Figure 3 As shown, the first delay unit uses an inverter structure with a transmission transistor added to the input. The low-to-high inversion delay is determined by the charging time of the node corresponding to P0, and the high-to-low inversion delay is determined by the charge and discharge time of the nodes corresponding to N0 and N1. To adjust the process sensitivity of this circuit structure, the degree to which the oscillation period is affected by the process of a specific MOS transistor can be adjusted by adjusting the proportion of the delay caused by that MOS transistor in the entire oscillation period.

[0064] For this circuit structure, delay can be adjusted by changing the width-to-length ratio of the threshold transistors. However, since it is difficult to simultaneously reduce the ratio of the PMOS and NMOS delays in the overall oscillation period, only the NMOS delay is increased to reduce delay. Furthermore, considering low power consumption, different types of threshold transistors were used in the design. The final threshold transistor width-to-length ratio and type were adjusted as follows: N0 uses a standard threshold transistor with a width-to-length ratio of 120 / 60, N1 uses a high-threshold transistor with a width-to-length ratio of 120 / 360, and P0 uses an ultra-high threshold transistor with a width-to-length ratio of 120 / 360.

[0065] See also Figure 2 , the second oscillator 13 includes a plurality of second delay units;

[0066] See also Figure 4 The second delay unit includes NMOS tubes N4, N5, N6, N7, N8, N9, N10, N11, and PMOS tubes P2 and P3;

[0067] The gate of the PMOS transistor P2, the gate of the NMOS transistor N4, and the drain of the NMOS transistor N5 are connected to the start signal START1, the source of the PMOS transistor P2 is connected to the VCC voltage, the drain of the PMOS transistor P2 is electrically connected to the source of the NMOS transistor N4 and the gate of the NMOS transistor N7, the drain of the NMOS transistor N4 is grounded, the gate of the NMOS transistor N5 is connected to the VCC voltage, the source of the NMOS transistor N5 is electrically connected to the gate of the NMOS transistor N6, the drain of the NMOS transistor N6 is grounded, the source of the NMOS transistor N6 is electrically connected to the drain of the NMOS transistor N7, the gate of the PMOS transistor P3, The gate of the NMOS transistor N8 and the drain of the NMOS transistor N9 are electrically connected, the source of the NMOS transistor N7 is connected to the VCC voltage, the source of the PMOS transistor P3 is connected to the VCC voltage, the drain of the PMOS transistor P3 is electrically connected to the source of the NMOS transistor N8 and the gate of the NMOS transistor N11, the source of the NMOS transistor N11 is connected to the VCC voltage, the drain of the NMOS transistor N8 is grounded, the source of the NMOS transistor N9 is electrically connected to the gate of the NMOS transistor N10, the drain of the NMOS transistor N10 is grounded, and the source of the NMOS transistor N10 and the drain of the NMOS transistor N11 output an oscillation signal.

[0068] Specifically, in this embodiment, the second oscillator 13 is designed to have a high sensitivity to the process. If the structure of the first oscillator 12 is still used, it is necessary to reduce the width-to-length ratio of the NMOS to increase the delay. Although this can increase the process sensitivity, it will cause the proportion of the discharge current in the temperature characteristics of the entire oscillator to increase with temperature, thereby making the temperature characteristics of the two circuits different. To address this problem, it is necessary to reduce the charging current, that is, to reduce the width-to-length ratio of the PMOS. However, it is difficult to modulate the sensitivity by changing the two MOS tubes at the same time, so it is necessary to insert the charging circuit into the NMOS for control. Finally, the unit structure of the second oscillator 13 is as follows: Figure 4As shown, this design employs two-stage inversion logic for each delay unit, with one stage consisting of four NMOS transistors and one PMOS transistor. The low-to-high inversion delay is determined by the charge and discharge times of the corresponding nodes P2 and N7, while the high-to-low inversion delay is determined by the charge and discharge times of the corresponding nodes N5 and N6. This configuration reduces the contribution of PMOS delay to the total inversion delay and increases the contribution of NMOS transistors to charge and discharge, significantly improving the circuit's sensitivity to process variations and facilitating temperature adjustment to maintain consistency with the temperature characteristics of the first oscillator 12 structure. In this example, the circuit operating voltage is set at 1.2V. To ensure proper circuit operation, the condition of 1.2V > Vthn1 + Vthn2 + Vthn3 must also be met. Therefore, N5, N6, and N7 use standard threshold transistors with a width-to-length ratio of 120 / 240. Furthermore, to reduce power consumption, NMOS transistors N4 and P2 use ultra-high threshold transistors with width-to-length ratios of 120 / 240 and 120 / 180, respectively.

[0069] In a specific embodiment, the monitoring unit is designed in Huahong 55nm process and built in Cadence Virtuoso software based on Figure 1 The circuit of the on-chip process corner monitoring unit based on the ring oscillator structure is shown and simulated.

[0070] The structures of the first oscillator and the second oscillator of this embodiment are as follows: Figure 2 shown.

[0071] The NMOS transistor N0 uses a normal threshold transistor with a width-to-length ratio of 120:60, the NMOS transistor N1 uses a high threshold transistor with a width-to-length ratio of 120:360, and the PMOS transistor uses an ultra-high threshold transistor with a width-to-length ratio of 120:360;

[0072] The NMOS transistors N5, N6, and N7 are ordinary threshold transistors with a width-to-length ratio of 120:240, the NMOS transistor N4 is an ultra-high threshold transistor with a width-to-length ratio of 120:240, and the PMOS transistor P2 is an ultra-high threshold transistor with a width-to-length ratio of 120:180.

[0073] Specifically, by fine-tuning the transistor's width-to-length ratio, the temperature characteristics of the two circuits can be made as consistent as possible. Differentiating the two output frequencies effectively eliminates the impact of temperature characteristics while preserving the process characteristics of the output.

[0074] See also Figure 5 , the frequency counting module 2 includes a 12-bit counter 21, a 16-bit counter 22, and a four-to-one multiplexer 23;

[0075] The 12-bit counter 21 is signal-connected to the four-to-one multiplexer 23 for counting the reference clock;

[0076] The 16-bit counter 22 is signal-connected to the four-to-one multiplexer 23 for counting the number of pulses of the oscillation signal;

[0077] The four-to-one multiplexer 23 is signal-connected to the 12-bit counter 21 for outputting a counting time control signal.

[0078] Specifically, the structure of the frequency counting module 2 of this embodiment is as follows: Figure 5 As shown, it primarily consists of a 12-bit counter 21, a 16-bit counter 22, and a four-to-one multiplexer 23. It uses a clock of known frequency to measure the clock frequency generated by the oscillator. The counter's operation is controlled by input signals CLK, RST, and enable. CLK is the counter's input clock, which counts clock pulses; RST is the reset signal, which must be reset before each count to clear the counter value; and enable is the enable signal. When it is high, the counter operates, and when it is low, counting stops. Four-to-one multiplexer 23 is used to select the length of the count time. The values ​​of S0 and S1 select one of the last four bits of the 12-bit counter 21 as the output. The count time is shortest when Q8 is output, and longest when Q11 is output.

[0079] The present invention also provides an on-chip process angle monitoring method based on a ring oscillator structure, comprising:

[0080] S1, receives the oscillator selection signal RO Select and the start signal START1 through the demultiplexer;

[0081] S2, set the oscillator selection signal RO Select to 0, and set the start signal START1 to 1, output the start signal START1 to the first oscillator through the demultiplexer, after the first oscillator oscillates stably, input the reset signal to the frequency counting module, output the first oscillation signal to the frequency counting module through the first oscillator, set the start signal START2 to 1 and input it to the frequency counting module, wait for a preset time period, and then record the first counting frequency of the frequency counting module;

[0082] S3, setting the oscillator selection signal RO Select to 1, and setting the start signal START1 to 1, outputting the start signal START1 to the second oscillator through the demultiplexer, inputting the reset signal to the frequency counting module after the second oscillator oscillates stably, outputting the second oscillation signal to the frequency counting module through the second oscillator, setting the start signal START2 to 1 and inputting it to the frequency counting module, waiting for a preset time period, and recording the second counting frequency of the frequency counting module;

[0083] S4: Calculate a process angle calibration reference frequency based on the first counting frequency and the second counting frequency.

[0084] Specifically, the frequency counting module's example circuit operates as follows: After resetting the circuit, the START signal is set high. At this point, both inputs of the AND gate are 1, causing the enable signal to transition from low to high. The two counters begin counting their respective input clocks, with the reference CLK connected to the system clock and the count CLK connected to the clock generated by the internal oscillator. For example, when S[1:0] = 00, after the 12-bit counter counts 256 pulses, Q8 transitions from 0 to 1, causing the enable signal to transition to 0, halting both counters. At this point, the value of the 16-bit counter can be read, and the oscillator's output frequency can be derived from this value.

[0085] The frequency counting module sends the counting time control signal [S0, S1] to the 12-bit counter through a four-to-one multiplexer, reads the reference clock through the 12-bit counter, and reads the oscillator clock through the 16-bit counter. The calculation formula of the control signal is:

[0086]

[0087] When the count time control signal is 00, select Q8 of the 12-bit counter; when the count time control signal is 01, select Q9 of the 12-bit counter; when the count time control signal is 10, select Q 10 When the count time control signal is 11, select Q of the 12-bit counter. 11 Bit.

[0088] The first counting frequency and the second counting frequency are read by the values ​​of the 12-bit counter and the 16-bit counter of the frequency counting module, and the calculation formula is:

[0089]

[0090] Among them, f osc1 is the first counting frequency, f osc2 is the second counting frequency, M1 is the value of the 16-bit counter when the first oscillator starts, M2 is the value of the 16-bit counter when the second oscillator starts, n1 is the number of bits selected by the 12-bit counter when the first oscillator starts, n2 is the number of bits selected by the 12-bit counter when the second oscillator starts, f ref1 The reference clock frequency of the 12-bit counter input when the first oscillator starts, f ref2 This is the reference clock frequency for the 12-bit counter input when the second oscillator is started.

[0091] Based on the first counting frequency f osc1 and the second counting frequency f osc2 The process angle calibration reference frequency Q is obtained by subtracting the process angle calibration reference frequency Q, and the process angle distribution of the chip is obtained by comparing the process angle calibration reference frequency Q with the values ​​obtained by simulating the chip at different process angles.

[0092] Specifically, during circuit design, a process angle monitoring circuit is built, and then the circuit is simulated at different process angles. The values ​​of the process angle calibration reference frequency Q obtained from simulations at different process angles will vary. For example, the process angle calibration reference frequency Q value at the FF process angle will be greater than the value at TT, while the process angle calibration reference frequency Q value at the SS process angle will be less than the value at the typical process. Therefore, after the chip is manufactured, the actual chip is tested, and the process angle calibration reference frequency Q value is compared with the values ​​at different process angles. Based on the comparison results, the process angle distribution of the manufactured chip can be determined.

[0093] Specifically, certain measures can be taken to reduce the errors introduced by the two steps of the frequency counting module. For example, the error introduced when generating a fixed high level can be reduced by increasing the frequency of the reference clock, increasing the number of reference clock counts N, and so on. The error introduced when counting pulses can be reduced by increasing the counting time T, increasing the oscillator frequency, and so on. In this embodiment, the error is reduced by increasing the counting time. In a simulation verification, the reference clock is set to 1MHz and the S[1:0] value is set to 00. The relative errors introduced by the counting module for the two oscillator frequencies are measured to be 0.66% and 0.45%.

[0094] By calculating the frequencies of the two oscillators using this frequency counter and performing differential processing, a frequency value can be obtained that is independent of temperature and can be calibrated for different process angles. This method can accurately monitor process variations on the chip.

[0095] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An on-chip process angle monitoring unit based on a ring oscillator structure, characterized in that: The monitoring unit comprises a process sensing module (1) and a frequency counting module (2); The process sensing module (1) is signal-connected to the frequency counting module (2) and is used to generate an oscillation signal affected by process changes and temperature changes through an oscillator; The frequency counting module (2) is signal-connected to the process sensing module (1) and is used to count and process the oscillation signal output by the process sensing module; The process sensing module (1) comprises a demultiplexer (11), a first oscillator (12), a second oscillator (13), and a multiplexer (14); The demultiplexer (11) is signal-connected to the first oscillator (12) and the second oscillator (13), and is used to output a start signal START1 to the first oscillator (12) or the second oscillator (13); The first oscillator (12) is signal-connected to the demultiplexer (11) and the multiplexer (14) and is used to output an oscillation signal with low sensitivity to process variations; The second oscillator (13) is signal-connected to the demultiplexer (11) and the multiplexer (14) and is used to output an oscillation signal with high sensitivity to process variations; The multiplexer (14) is signal-connected to the first oscillator (12), the second oscillator (13), and the frequency counting module (2), and is used to transmit the oscillation signal output by the first oscillator (12) or the second oscillator (13) to the frequency counting module (2).

2. The on-chip process angle monitoring unit based on the ring oscillator structure according to claim 1, characterized in that: The first oscillator (12) includes a plurality of first delay units; The first delay unit includes NMOS tubes N0, N1, N2, N3, and PMOS tubes P0, P1; The gate of the NMOS tube N0 is connected to the VCC voltage, the drain of the NMOS tube N0 and the gate of the PMOS tube P0 are connected to the start signal START1, the source of the NMOS tube N0 is electrically connected to the gate of the NMOS tube N1, the source of the PMOS tube P0 is connected to the VCC voltage, the drain of the PMOS tube P0 is electrically connected to the source of the NMOS tube N1, the gate of the PMOS tube P1, and the drain of the NMOS tube N2, the drain of the NMOS tube N1 is grounded, the gate of the NMOS tube N2 is connected to the VCC voltage, the source of the NMOS tube N2 is electrically connected to the gate of the NMOS tube N3, the source of the PMOS tube P1 is connected to the VCC voltage, the drain of the NMOS tube N3 is grounded, and the drain of the PMOS tube P1 and the source of the NMOS tube N3 output an oscillation signal.

3. The on-chip process angle monitoring unit based on the ring oscillator structure according to claim 2, characterized in that: The second oscillator (13) comprises a plurality of second delay units; The second delay unit includes NMOS tubes N4, N5, N6, N7, N8, N9, N10, N11, and PMOS tubes P2 and P3; The gate of PMOS tube P2, the gate of NMOS tube N4, and the drain of NMOS tube N5 are connected to the start signal START1, the source of PMOS tube P2 is connected to the VCC voltage, the drain of PMOS tube P2 is electrically connected to the source of NMOS tube N4 and the gate of NMOS tube N7, the drain of NMOS tube N4 is grounded, the gate of NMOS tube N5 is connected to the VCC voltage, the source of NMOS tube N5 is electrically connected to the gate of NMOS tube N6, the drain of NMOS tube N6 is grounded, the source of NMOS tube N6 is connected to the drain of NMOS tube N7, the gate of PMOS tube P3, The gate of the NMOS tube N8 and the drain of the NMOS tube N9 are electrically connected, the source of the NMOS tube N7 is connected to the VCC voltage, the source of the PMOS tube P3 is connected to the VCC voltage, the drain of the PMOS tube P3 is electrically connected to the source of the NMOS tube N8 and the gate of the NMOS tube N11, the source of the NMOS tube N11 is connected to the VCC voltage, the drain of the NMOS tube N8 is grounded, the source of the NMOS tube N9 is electrically connected to the gate of the NMOS tube N10, the drain of the NMOS tube N10 is grounded, and the source of the NMOS tube N10 and the drain of the NMOS tube N11 output an oscillation signal.

4. The on-chip process angle monitoring unit based on the ring oscillator structure according to claim 3, characterized in that: The NMOS transistor N0 uses a common threshold transistor with a width-to-length ratio of 120:60, the NMOS transistor N1 uses a high threshold transistor with a width-to-length ratio of 120:360, and the PMOS transistor uses an ultra-high threshold transistor with a width-to-length ratio of 120:360; The NMOS tubes N5, N6, and N7 use ordinary threshold transistors with a width-to-length ratio of 120:240, the NMOS tube N4 uses an ultra-high threshold transistor with a width-to-length ratio of 120:240, and the PMOS tube P2 uses an ultra-high threshold transistor with a width-to-length ratio of 120:

180.

5. The on-chip process angle monitoring unit based on the ring oscillator structure according to claim 1, characterized in that: The frequency counting module (2) comprises a 12-bit counter (21), a 16-bit counter (22), and a four-to-one multiplexer (23); The 12-bit counter (21) is connected to the four-to-one multiplexer (23) signal and is used to count the reference clock; The 16-bit counter (22) is connected to the four-to-one multiplexer (23) for counting the number of pulses of the oscillation signal; The four-to-one multiplexer (23) is connected to the 12-bit counter (21) signal and is used to output a counting time control signal.

6. An on-chip process angle monitoring method based on a ring oscillator structure, characterized in that: The method is implemented based on the on-chip process angle monitoring unit based on the ring oscillator structure according to any one of claims 1 to 5, comprising: S1, receives the oscillator selection signal RO Select and the start signal START1 through the demultiplexer; S2, set the oscillator selection signal RO Select to 0, and set the start signal START1 to 1, output the start signal START1 to the first oscillator through the demultiplexer, after the first oscillator oscillates stably, input the reset signal to the frequency counting module, output the first oscillation signal to the frequency counting module through the first oscillator, set the start signal START2 to 1 and input it to the frequency counting module, wait for a preset time period, and record the first counting frequency of the frequency counting module; S3, set the oscillator selection signal RO Select to 1, and set the start signal START1 to 1, output the start signal START1 to the second oscillator through the demultiplexer, after the second oscillator oscillates stably, input the reset signal to the frequency counting module, output the second oscillation signal to the frequency counting module through the second oscillator, set the start signal START2 to 1 and input it to the frequency counting module, wait for a preset time period, and record the second counting frequency of the frequency counting module; S4: Calculate a process angle calibration reference frequency based on the first counting frequency and the second counting frequency.

7. The on-chip process angle monitoring method based on the ring oscillator structure according to claim 6, characterized in that: The frequency counting module sends the counting time control signal [S0, S1] to the 12-bit counter through a four-to-one multiplexer, reads the reference clock through the 12-bit counter, and reads the oscillator clock through the 16-bit counter. The calculation formula of the control signal is: When the count time control signal is 00, select Q8 of the 12-bit counter; when the count time control signal is 01, select Q9 of the 12-bit counter; when the count time control signal is 10, select Q 10 When the count time control signal is 11, select Q of the 12-bit counter. 11 Bit.

8. The on-chip process angle monitoring method based on the ring oscillator structure according to claim 7, characterized in that: The first counting frequency and the second counting frequency are read through the values ​​of the 12-bit counter and the 16-bit counter of the frequency counting module, and the calculation formula is: Among them, f osc1 is the first counting frequency, f osc2 is the second counting frequency, M1 is the value of the 16-bit counter when the first oscillator starts, M2 is the value of the 16-bit counter when the second oscillator starts, n1 is the number of bits selected by the 12-bit counter when the first oscillator starts, n2 is the number of bits selected by the 12-bit counter when the second oscillator starts, f ref1 is the reference clock frequency of the 12-bit counter input when the first oscillator starts, f ref2 This is the reference clock frequency for the 12-bit counter input when the second oscillator is started.

9. The on-chip process angle monitoring method based on the ring oscillator structure according to claim 8, characterized in that: Step S4 includes: Based on the first counting frequency f osc1 and the second counting frequency f osc2 The process angle calibration reference frequency Q is obtained by subtraction, and the process angle calibration reference frequency Q is compared with the values ​​obtained by simulating the chip at different process angles to obtain the process angle distribution of the chip.

Images