Double Heterojunction Bipolar Transistor

Abstract

The present application provides a double heterojunction bipolar transistor. The double heterojunction bipolar transistor comprises an N-type GaAs sub-collector layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer, and an N-type InGaAs contact layer stacked in sequence, wherein the P-type base layer is a P-type GaAs （1‑x） Sb x , A, d 1 / GaAs,B,d 2 / GaAs （1‑y） Sb y , C, d 3 / GaAs,B,d 2 The multi-periodic repeating structure of the four-layer lattice layer can bind the electrons in the base layer to the GaAs （1‑x） Sb x layer, trapping the holes in the base layer in the GaAs （1‑y） Sb y The GaAs layer is spaced in the middle of the layer, which effectively separates electrons and holes in physical space and reduces their recombination probability in the base region, thereby effectively increasing the collector current I c , thereby increasing the current gain β value.

Description

Technical Field

[0001] The present invention belongs to the technical field of transistors, and in particular, relates to a double heterojunction bipolar transistor. Background Art

[0002] Compared with the traditional Si-based bipolar transistor, the heterojunction bipolar transistor (HBT) is characterized by using different semiconductor materials for the emitter and base, and having different energy band structures. The current gain no longer depends on the difference in doping concentration between the two, but exponentially depends on the difference in valence band and conduction band between the two. Therefore, it has a higher current gain cutoff frequency, lower base resistance, lower BE junction capacitance and higher early voltage. Among them, the InGaP / GaAs / GaAs HBT based on GaAs and InGaP materials is a typical representative.

[0003] Double heterojunction bipolar transistor (DHBT) is a structure of HBT, and its typical feature is that the emitter, base and collector are all made of different semiconductor materials, and their different band structures are used to further improve the performance of HBT. For example, the GaInP / GaAsSb / GaAs DHBT, which has attracted much attention, uses GaInP / GaAsSb / junction instead of GaInP / GaAs junction from the emitter-base junction theory analysis compared to the traditional InGaP / GaAs / GaAs HBT. From the band structure, GaAsSb / GaInP junction has a larger band difference, specifically, the conduction band energy level difference (ΔEc) is significantly reduced. Therefore, it can effectively reduce the turn-on voltage Von of the emitter and base, and reduce the offset voltage (Voff) of the emitter-collector.

[0004] However, the GaInP / GaAsSb / GaAs DHBT structure has a problem in actual production. Since the lattice constant of GaAsSb is greater than that of GaAs and GaInP, when growing the DHBT epitaxial structure by metal organic chemical vapor deposition (MOCVD), the GaAsSb base region is grown on the GaAs substrate, which will produce stress or lattice mismatch, defects in the base material, and an increased recombination probability of electrons and holes in the base region, resulting in a base current I b increases, resulting in a current gain β (β = I c / I b ) becomes lower. Therefore, how to improve the current gain β value of GaInP / GaAsSb / GaAs DHBT transistors becomes a problem that needs to be solved. Summary of the invention

[0005] The technical problem solved by the present invention is: how to improve the current gain β value of a double heterojunction bipolar transistor.

[0006] The present application provides a double heterojunction bipolar transistor, which includes an N-type GaAs subset electrode layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer, and an N-type InGaAs contact layer stacked in sequence. The P-type base layer is P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure, where x and y represent the percentage of Sb component in the GaAsSb layer, and the relationship between x and y satisfies x≥y, A, B, and C represent the P-type carrier concentration values, satisfying A<B<C, and d1, d2, and d3 are the thicknesses of each layer.

[0007] Optionally, the percentage of Sb component in the GaAs （1-x） Sb x and GaAs （1-y） Sb y layers are both less than 15%.

[0008] Optionally, the number of periods of the P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer is 15 - 20.

[0009] Optionally, the multi-periodic repeating structure of the P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer satisfies the following weighted doping concentration relational formula:

[0010] D = (A×d1 + 2×B×d2 + C×d3) / (d1 + 2d2 + d3)

[0011] Wherein, D represents the P-type carrier concentration value of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor, and the value range of D is 2.5E19 / cm 3 to 5E19 / cm 3 .

[0012] Optionally, the P-type GaAs （1-x） Sbx A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi - period repeating structure of four lattice layers of C, d3 / GaAs, B, d2 satisfies the following weighted average lattice plane spacing relation:

[0013] (6.0954 - 0.4420×(1 - z)) = [(6.0954 - 0.4420×(1 - x))×d1+(6.0954 - 0.4420×(1 - y))×d3 + 5.6533×2×d2] / (d1 + 2d2 + d3)

[0014] Among them, z represents the percentage of the Sb component in the P - type GaAsSb base layer in a conventional double - heterojunction bipolar transistor, and the value range of z is from 3% to 6%.

[0015] Optionally, the doping source of the P - type base layer is CCl4 or CBr4.

[0016] Optionally, the N - type GaAs sub - collector layer is an Si - doped N - type GaAs material layer, the N - type GaAs collector layer is an Si - doped N - type GaAs material layer, the N - type GaInP emitter layer is an Si - doped N - type GaInP material layer, and the N - type InGaAs contact layer is an Si - doped N - type InGaAs material layer.

[0017] Optionally, the double - heterojunction bipolar transistor further includes a GaAs substrate layer, and the N - type GaAs sub - collector layer is stacked on the GaAs substrate layer.

[0018] A double - heterojunction bipolar transistor provided by the present application has the following technical effects:

[0019] Replacing the base region material from P - type GaAs （1-z） Sb z with P - type GaAs （1-x） Sb x A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi - period repeating structure of four lattice layers of C, d3 / GaAs, B, d2. Since the p - type carrier concentration A < B < C, for GaAs （1-x） Sb x A / GaAs, B / GaAs （1-y） Sb y C / GaAs, B, the energy band results of the four lattice layers show that the valence band Ec(GaAs （1-x） Sb x , A) < Ec(GaAs （1-x）Sb x , C) < Ec(GaAs, B), conduction band Ev(GaAs （1-x） Sb x , A) < Ev(GaAs, B) < Ev(GaAs （1-x） Sb x , C). This energy band structure can confine the electrons in the base layer in the GaAs （1-x） Sb x , A layer, and confine the holes in the base layer in the GaAs （1-y） Sb y , C layer, with a GaAs, B layer in between. This structure can more effectively achieve the physical separation of electrons and holes, reduce their recombination probability in the base region, and thus effectively increase the collector current I c , and further increase the current gain β value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a double heterojunction bipolar transistor of the prior art;

[0021] Figure 2 is a schematic diagram of a double heterojunction bipolar transistor according to Embodiment 1 of the present invention;

[0022] Figure 3 is the P-type GaAs in Embodiment 1 of the present invention （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure schematic diagram;

[0023] Figure 4 is the P-type GaAs in Embodiment 1 of the present invention （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure energy band diagram.

[0024] The correspondence between the reference numerals and the component names is as follows:

[0025] 10 - N-type GaAs subset collector layer, 20 - N-type GaAs collector layer, 30 - P-type base layer, 40 - N-type GaInP emitter layer, 50 - N-type InGaAs contact layer, 60 - GaAs substrate layer. DETAILED DESCRIPTION OF THE INVENTION

[0026] To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0027] Before describing the embodiments of the present application in detail, the technical concept of the present application will be briefly described first: In current GaInP / GaAsSb / GaAs DHBT transistors, electrons and holes are prone to recombination in the base, resulting in a problem of reduced current gain. To this end, the present application provides a double heterojunction bipolar transistor, where the base region material of the DHBT transistor is composed of P-type GaAs （1-z） Sb z , and the D body material is replaced with P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure, whose energy band structure can achieve the physical separation of electrons and holes, reduce their recombination probability in the base region, and thus can effectively increase the collector current I c , and further increase the current gain β value. The specific principle of the double heterojunction bipolar transistor of the present application will be described below with more embodiments.

[0028] Specifically, as Figure 2 shown, the double heterojunction bipolar transistor of Embodiment 1 includes an N-type GaAs sub-collector layer 10, an N-type GaAs collector layer 20, a P-type base layer 30, an N-type GaInP emitter layer 40, and an N-type InGaAs contact layer 50 stacked in sequence. The P-type base layer 30 is P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure 30, where x and y represent the percentage of Sb component in the GaAsSb layer, and the relationship between x and y satisfies x≥y, and A, B, and C represent the P-type carrier concentration values, satisfying A<B<C, and d1, d2, and d3 are the thicknesses of each layer.

[0029] Exemplarily, as Figure 3 shown, the GaAs （1-x） Sb x layers 31, GaAs layers 32, GaAs （1-y） Sb y layers 33, and GaAs layers 34 in the P-type base layer 30 are alternately stacked with multiple periods. In one or more embodiments, GaAs（1-x） Sb x The percentage x of the Sb component in the layer, GaAs （1-y） Sb y The percentage y of the Sb component in the layer is less than 15%, and the number of periods of the multi-period repeating structure is 15 - 20. By adjusting the percentages x and y of the Sb component within the above ranges, GaAs （1-x） Sb x layer, GaAs （1-y） Sb y layer thicknesses are such that the average lattice plane spacing of the superlattice base layer is the same as that of the conventional GaAsSb base layer.

[0030] As Figure 4 shown, since the p-type carrier concentration A < B < C, for GaAs （1-x） Sb x , A / GaAs, B / GaAs （1-y） Sb y , C / GaAs, the energy band results of the B four-layer lattice layers show that the valence band Ec(GaAs （1-x） Sb x , A) < Ec(GaAs （1-x） Sb x , C) < Ec(GaAs, B), and the conduction band Ev(GaAs （1-x） Sb x , A) < Ev(GaAs, B) < Ev(GaAs （1-x） Sb x , C). Using the multi-period repeating structure of these four-layer lattice layers can confine the electrons in the base layer to the GaAs （1-x） Sb x , A, d1 layer, and confine the holes in the base layer to the GaAs （1-y） Sb y , C, d3 layer, and there is a GaAs, B layer in between. This structure can more effectively achieve the physical separation of electrons and holes, reduce their recombination probability in the base region, and thus can effectively increase the collector current I c , and further increase the current gain β value.

[0031] By adjusting the relative thicknesses of the GaAs （1-x） Sb x layer, GaAs （1-y） Sb y layer and the GaAs layer and the percentages x and y of the Sb component in the multi-period repeating structure, the lattice plane spacing of the superlattice material is the same as that of the conventional base region GaAsSb bulk material, and the required energy band structure is obtained, as Figure 4As shown, its energy band structure is a type II energy band structure, which can ensure that the turn-on voltage of the BE junction is consistent with the turn-on voltage of a conventional double heterojunction bipolar transistor.

[0032] For example, P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi-periodic repeating structure of the four-layer lattice layer of C, d3 / GaAs, B, d2 satisfies the following weighted doping concentration relationship:

[0033] D=(A×d1+2×B×d2+C×d3) / (d1+2d2+d3)

[0034] Where D represents the P-type carrier concentration of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor. The value range of D is 2.5E19 / cm 3 To 5E19 / cm 3 .

[0035] For example, P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi-periodic repeating structure of the four-layer lattice layer of C, d3 / GaAs, B, d2 satisfies the following weighted average crystal plane spacing relationship:

[0036] (6.0954 -0.4420×(1-z))=[(6.0954 -0.4420×(1-x))×d1+(6.0954 -0.4420×(1-y))×d3+5.6533×2×d2] / (d1+2d2+d3)

[0037] Wherein, z represents the percentage of the Sb component in the P-type GaAsSb base layer in the conventional double heterojunction bipolar transistor, and the value of z ranges from 3% to 6%.

[0038] Exemplarily, the doping source of the P-type base layer 30 is CCl4 or CBr4.

[0039] In one or more embodiments, the N-type GaAs subcollector layer 10 is a Si-doped N-type GaAs material layer, the N-type GaAs collector layer 20 is a Si-doped N-type GaAs material layer, the N-type GaInP emitter layer 40 is a Si-doped N-type GaInP material layer, and the N-type InGaAs contact layer 50 is a Si-doped N-type InGaAs material layer. The doping concentration and thickness of each layer can be set as required.

[0040] Furthermore, the double heterojunction bipolar transistor further includes a GaAs substrate layer 60 , and the N-type GaAs sub-collector layer 10 is stacked on the GaAs substrate layer 60 .

[0041] For example, in order to illustrate the advantages of the double heterojunction bipolar transistor of this embodiment over the traditional double heterojunction bipolar transistor, two samples of double heterojunction bipolar transistors were prepared for testing. The thickness of each layer, doping concentration, thickness of the superlattice layer, number of periods and other parameters of the double heterojunction bipolar transistor of this embodiment are as follows:

[0042] N-type GaAs sub-collector layer 10: Si doping concentration is 4E18 / cm 3 , thickness is 600nm;

[0043] N-type GaAs collector layer 20: Si doping concentration is 3E16 / cm 3 , thickness is 1500nm;

[0044] P-type GaAs 0.9 Sb 0.1 , 2E19 / cm 3 , 1nm / GaAs, 3E19 / cm 3 , 1nm / GaAs 0.9 Sb 0.1 , 4E19 / cm 3 , 1nm / GaAs, 3E19 / cm 3 , the period number of the multi-periodic repeating structure of the four-layer lattice layer of 1nm is 20, and the total thickness is 80nm;

[0045] N-type GaInP emitter layer 40: Si doping concentration is 5E17 / cm 3 , thickness is 40nm;

[0046] N-type InGaAs contact layer 50: Si doping concentration is 1E19 / cm3 and thickness is 100nm.

[0047] As a comparison, Figure 1 As shown, the thickness, doping concentration and other parameters of each layer of the conventional double heterojunction bipolar transistor are as follows:

[0048] N-type GaAs sub-collector layer: Si doping concentration is 4E18 / cm 3 , thickness is 600nm;

[0049] N-type GaAs collector layer: Si doping concentration is 3E16 / cm 3 , thickness is 1500nm;

[0050] P-type GaAs （1-z） Sb z , D base layer: the percentage z of Sb component is 0.05, the percentage (1-z) of As component is 0.95, the P-type doping concentration is 3E19 / cm3, and the thickness is 80nm;

[0051] N-type GaInP emitter layer: Ga component percentage is 0.515, Si doping concentration is 5E17 / cm 3 , thickness is 40nm;

[0052] N-type InGaAs contact layer: Si doping concentration is 1E19 / cm 3 , thickness is 100nm.

[0053] Among them, when preparing the two types of double heterojunction bipolar transistors, MOCVD is used to grow each layer, and the growth conditions of other functional layers are the same. The difference lies in the structure and process of the base layer.

[0054] Then, the test was conducted, and the various indicators of the double heterojunction bipolar transistor of the present embodiment were Von=1.061V, Voff=0.049V, β=82, and the various indicators of the conventional double heterojunction bipolar transistor were Von=1.061V, Voff=0.049V, β=65. According to the test results, the current gain value β of the double heterojunction bipolar transistor of the present embodiment was increased from 65 to 82, and the current gain was increased by 26%, which was significantly improved compared with the conventional double heterojunction bipolar transistor.

[0055] The specific implementation methods of the present invention are described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that these embodiments can be modified and improved without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents. These modifications and improvements should also be within the scope of protection of the present invention.

Claims

1. A double heterojunction bipolar transistor, characterized in that: The double heterojunction bipolar transistor includes an N-type GaAs sub-collector layer, an N-type GaAs collector layer, a P-type base layer, an N-type GaInP emitter layer, and an N-type InGaAs contact layer that are stacked in sequence. The P-type base layer is P-type GaAs. （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2 four-layer lattice layer multi-periodic repeating structure, where x and y represent the percentage of Sb component in the GaAsSb layer, and the relationship between x and y satisfies x≥y. A, B, and C represent the numerical values of the P-type carrier concentration, satisfying A < B < C, and d1, d2, and d3 are the thicknesses of each layer; the GaAs （1-x） Sb x , GaAs （1-y） Sb y The percentage x and y of the Sb component in the layer are both less than 15%.

2. The double heterojunction bipolar transistor according to claim 1, characterized in that: The P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y , C, d3 / GaAs, B, d2, the period number of the four lattice layers is 15-20.

3. The double heterojunction bipolar transistor according to claim 1, characterized in that: The P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi-periodic repeating structure of the four-layer lattice layer of C, d3 / GaAs, B, d2 satisfies the following weighted doping concentration relationship: D=(A×d1+2×B×d2+C×d3) / (d1+2d2+d3) Where D represents the P-type carrier concentration of the P-type GaAsSb base layer in a conventional double heterojunction bipolar transistor. The value range of D is 2.5E19 / cm 3 To 5E19 / cm 3 .

4. The double heterojunction bipolar transistor according to claim 1, characterized in that: The P-type GaAs （1-x） Sb x , A, d1 / GaAs, B, d2 / GaAs （1-y） Sb y The multi-periodic repeating structure of the four-layer lattice layer of C, d3 / GaAs, B, d2 satisfies the following weighted average crystal plane spacing relationship: (6.0954 -0.4420×(1-z))=[(6.0954 -0.4420×(1-x))× d1+(6.0954 -0.4420×(1-y))×d3+5.6533×2×d2] / (d1+2d2+d3) Wherein, z represents the percentage of the Sb component in the P-type GaAsSb base layer in the conventional double heterojunction bipolar transistor, and the value of z ranges from 3% to 6%.

5. The double heterojunction bipolar transistor according to claim 1, characterized in that: The doping source of the P-type base layer is CCl4 or CBr4.

6. The double heterojunction bipolar transistor according to claim 1, characterized in that: The N-type GaAs subcollector layer is a Si-doped N-type GaAs material layer, the N-type GaAs collector layer is a Si-doped N-type GaAs material layer, the N-type GaInP emitter layer is a Si-doped N-type GaInP material layer, and the N-type InGaAs contact layer is a Si-doped N-type InGaAs material layer.

7. The double heterojunction bipolar transistor according to claim 1, characterized in that: The double heterojunction bipolar transistor further comprises a GaAs substrate layer, and the N-type GaAs sub-collector layer stack is arranged on the GaAs substrate layer.

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