A multi-channel power-on and power-off testing system and method

Abstract

The present invention relates to the technical field of electronic equipment testing, and in particular to a multi-channel power-on and power-off testing system and method. The multi-channel power-on and power-off testing system comprises: a plurality of signal receiving modules, a plurality of switch devices and a microprocessor. The signal receiving module and the switch device are respectively connected to the microprocessor for communication, and the signal receiving module is connected to the communication port of the device under test, wherein the device under test is loaded with a test program; when the test program is running, the device under test can send a power-off instruction to the signal receiving module; the switch device is connected to the power supply port of the device under test. The signal receiving module corresponds to the switch device one by one to form a plurality of test loops. The signal receiving module transmits the power-off instruction to the microprocessor; the microprocessor controls the on and off of the switch device according to the power-off instruction, and when the microprocessor does not receive the power-off instruction, it will not trigger a power-off, so that the device under test can maintain a fault state, which is convenient for the tester to record and analyze the fault.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment testing, and in particular to a multi-channel power-on and power-off testing system and method. Background Art

[0002] As society develops, we have entered the information age. The number and types of electronic devices that people come into contact with in their lives and are hidden in all walks of life have experienced explosive growth. The faster the electronic equipment is updated, the greater the development and testing pressure between R&D and manufacturing companies. For R&D and manufacturing companies, being able to quickly debug products with excellent performance, stable operation, and high reliability, and being able to solve reliability testing problems in R&D, means being able to bring products to market faster, win reputation, and gain an advantage in the fierce industry competition.

[0003] Failures of electronic equipment often occur during the power-on and power-off process, and abnormal power failure is the most severe scenario in power-on and power-off. The test results of abnormal power failure can best reflect the reliability level of an electronic product. However, there is currently no unified universal abnormal power failure test tool in the industry.

[0004] Currently, there are the following conventional methods for abnormal power failure testing:

[0005] 1. The tester manually turns on and off the power supply, observes whether the equipment has any abnormal working conditions during the power on and off process, and records the number of tests. This method allows the tester to observe and record in real time whether any abnormalities occur. If an abnormality occurs, the current state of the fault can be kept so that R&D personnel can conduct targeted analysis and debugging; however, this method is inefficient and consumes a lot of time and energy of the tester, resulting in huge personnel and time costs, and cannot meet the needs of batch testing scenarios.

[0006] 2. Use the timing switch, set the interval time T1 to turn on the power of the device, and then turn off the power of the device after the interval time T2, and keep cycling until it is manually stopped. And record the number of tests through the counting module. For example, the Chinese patent application with publication number CN116107825A discloses a storage controller mainboard power-on and power-off test device, storage device and server. Through the coordination of the timing module, the control module and the first controllable switch, when the storage controller mainboard starts to power on, the timing module starts timing accordingly, stops timing after the first preset time and sends a first control signal to the input end of the control module, so that the control module controls the first controllable switch to turn off, and the storage controller mainboard enters the power-off state; after the second preset time, the control module controls the first controllable switch to turn on, and the storage controller mainboard enters the power-on state. At this time, the timing module starts a new round of timing again, thereby realizing the power-on and power-off test of the storage controller mainboard.

[0007] The existing technology can only determine whether the tested device is successfully powered on and off, but cannot determine whether the program loaded by the tested device is successfully running. When the tested device is successfully powered on but an abnormal fault occurs during program operation, after the set power-off countdown expires, the tested device will be directly powered off regardless of whether the tested device has an abnormality or not, and the fault phenomenon will not be retained, making it impossible to count the fault occurrence rate and analyze the fault problem. Summary of the invention

[0008] The purpose of the present invention is to overcome the problem that the prior art only determines whether the power on and off are successful during power on and off tests, but cannot determine whether the program loaded by the tested device is successfully running, and cannot retain the failure status of the program running of the tested device, and provides a multi-path power on and off test system and method.

[0009] In the first aspect, the present invention provides a multi-channel power-on and power-off test system. The multi-channel power-on and power-off test system provided by the present invention may include: a plurality of signal receiving modules, used to connect the communication port of the device under test, wherein the device under test is loaded with a test program; when the test program is running, the device under test can send a power-off instruction to the signal receiving module through the communication port; a plurality of switch devices, used to connect the power supply port of the device under test to realize the power on and off of the device under test; the signal receiving module and the switch device are respectively connected to a microprocessor for communication; and the signal receiving module corresponds to the switch device one by one to form a plurality of test loops. The signal receiving module transmits the power-off instruction to the microprocessor; the microprocessor controls the on and off of the switch device in the same test loop as the signal receiving module according to the power-off instruction; wherein, when the microprocessor receives the power-off instruction, the corresponding switch device is turned off, and the switch device is turned on after the preset power-off duration; when the microprocessor does not receive the power-off instruction, the corresponding switch device is kept on, and the device under test is continuously powered, so that the device under test maintains the current state.

[0010] According to a preferred embodiment, upon receiving the power-off instruction, the microprocessor disconnects the switch device to power off the device under test, and after a first preset time, turns on the switch device to power on the device under test.

[0011] According to a preferred embodiment, the power-on and power-off test system further includes: a time setting module and a display module. The time setting module and the display module are respectively connected to the microprocessor data. The time setting module is used to set the value of the first preset time length. The display module is used to display the setting result when setting the value of the first preset time length; during the test, the power-off information of each test circuit is displayed.

[0012] According to a preferred embodiment, the signal receiving module is connected to the microprocessor via a delay and manual trigger circuit. The delay and manual trigger circuit includes: a delay circuit for filtering out invalid power-off instructions and converting valid power-off instructions into valid signals; and a manual trigger circuit for sending valid signals to the microprocessor.

[0013] According to a preferred embodiment, the signal receiving module receives the power-off instruction sent by the device under test and transmits the power-off instruction to the delay circuit. The delay circuit determines whether the power-off instruction is valid and filters out invalid power-off instructions; the manual trigger circuit outputs a valid signal representing a valid power-off instruction to the microprocessor.

[0014] According to a preferred embodiment, the power-off instruction is a continuous high-level signal. The delay circuit determines whether the power-off instruction is valid by determining whether the high-level duration of the power-off instruction meets a second preset duration. The delay circuit filters out high-level signals whose duration is shorter than the second preset duration, ensuring that the power-off instruction transmitted to the microprocessor is a high-level signal whose duration meets the second preset duration.

[0015] According to a preferred implementation, the switch device is connected to a power supply module, and the switch device switches on or cuts off the power supply module supplying power to the device under test in response to regulation by the microprocessor.

[0016] The present invention also provides a multi-channel power-on and power-off testing method, which is characterized by at least comprising the following steps:

[0017] S1: Connecting the communication port of the tested device to a signal receiving module; connecting the power supply port of the tested device to a switch device; loading a test program for the tested device, and when the test program is running, the tested device can send a power-off instruction to the microprocessor through the communication port;

[0018] S2: Set the power-off duration through the time setting module;

[0019] S3: Send a power-off command to the microprocessor through the delay and manual trigger circuit to start the test.

[0020] According to a preferred implementation, the test method further includes: S4, the microprocessor receives a valid power-off instruction, turns off the corresponding switch device, and turns on the switch device after the power-off duration has elapsed.

[0021] According to a preferred implementation, the testing method further includes: S5, when the microprocessor does not receive a valid power-off instruction, the switch device remains turned on, and continues to supply power to the device under test, so that the device under test remains in a current state.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] In the present invention, the signal receiving module corresponds to the switch device one by one, forming several test loops, which can simultaneously connect multiple devices under test for testing, and the power supply of each device under test can be controlled separately. The test arrangement is simpler, the cost is lower, and the efficiency is higher. During the test, the device under test sends a power-off instruction to the microprocessor by running the test program. When the microprocessor does not receive the power-off instruction sent by the device under test, it will not trigger a power-off, so that the device under test can maintain a fault state when a program operation failure occurs, which is convenient for testers to record and analyze program operation failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a multi-channel power-on and power-off test system according to a preferred embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a time delay and manual trigger circuit according to a preferred embodiment of the present invention;

[0026] Figure 3 The present invention is a flowchart of a multi-channel power-on and power-off test system for performing a test according to a preferred embodiment of the present invention.

[0027] 110 - signal receiving module, 120 - switch device, 130 - microprocessor, 140 - time setting module, 150 - display module, 160 - delay and manual trigger circuit, 170 - power supply module, 200 - tested equipment. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below in conjunction with specific embodiments. However, this should not be understood as the scope of the above subject matter of the present invention being limited to the following embodiments, and all technologies realized based on the content of the present invention belong to the scope of the present invention.

[0029] Unless otherwise specified, in the description of the specific embodiments of the present invention, the terms indicating the orientation or position relationship such as "up", "down", "left", "right", "center", "inside", "outside", etc. are all expressions based on the orientation or position relationship shown in the drawings, or are the orientation or position relationship when the invented product / equipment / device is usually used. These terms of orientation or position relationship are only for the convenience of describing the scheme of the present invention or simplifying the description in the specific embodiments, so as to facilitate the technicians to quickly understand the scheme, and do not indicate or imply that a specific device / component / element must have a specific orientation, or be constructed and operated in a specific position relationship, and therefore cannot be understood as a limitation on the present invention.

[0030] In addition, if the terms "horizontal", "vertical", "overhanging", "parallel" and the like appear, it does not mean that the corresponding devices / components / elements are required to be absolutely horizontal or vertical or overhanging or parallel, but may be slightly tilted or have deviations. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but may be slightly tilted. Alternatively, it can be simplified to mean that the corresponding devices / components / elements are set in directions such as "horizontal", "vertical", "overhanging", "parallel", etc., and can have an error / deviation of ±10% relative to the corresponding direction setting, more preferably an error / deviation within ±8%, more preferably an error / deviation within ±6%, more preferably an error / deviation within ±5%, and more preferably an error / deviation within ±4%. As long as the corresponding device / component / element is within the error / deviation range, it can still achieve its role in the scheme of the present invention.

[0031] In addition, the expressions “first”, “second”, “third”, etc., which appear in the terms, are merely used to distinguish the description of the same or similar components and should not be understood as emphasizing or implying the relative importance of specific components.

[0032] In addition, in the description of the embodiments of the present invention, "several", "plurality" and "a number" represent at least 2. It can be any number such as 2, 3, 4, 5, 6, 7, 8, 9, and even more than 9.

[0033] In addition, in the description of the technical solution of the present invention, unless otherwise clearly specified / defined / restricted, the terms "set", "install", "connect", "connected", "provided with", "laid", and "arranged" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection, and can be welding, riveting, bolting, threading, and other commonly used connection means in the field. This connection can be a mechanical connection, an electrical connection, or a communication connection; it can be a direct connection, or an indirect connection through an intermediate medium, and it can be the internal connection of two elements.

[0034] Example 1

[0035] This embodiment provides a multi-channel power-on and power-off test system. Figure 1 The multi-channel power-on and power-off test system provided in this embodiment may include: a plurality of signal receiving modules 110, a plurality of switch devices 120 and a microprocessor 130. The plurality of signal receiving modules 110 are used to connect to the communication port of the device under test 200 and receive the power-off instruction sent by the device under test 200. The device under test 200 is loaded with a test program; when the test program is running, the device under test 200 can send a power-off instruction to the signal receiving module 110 through the communication port. The plurality of switch devices 120 are used to connect to the power supply port of the device under test 200 to realize the power on and off of the device under test 200. The signal receiving module 110 and the switch device 120 are respectively connected to the microprocessor 130 in communication; and the signal receiving module 110 corresponds to the switch device 120 one by one to form a plurality of test loops. The signal receiving module 110 transmits the power-off instruction to the microprocessor 130. The microprocessor 130 controls the on and off of the switch device 120 in the same test loop as the signal receiving module 110 according to the power-off instruction. Preferably, when the microprocessor 130 receives a power-off instruction, it turns off the corresponding switch device 120, and turns on the switch device 120 after a preset power-off duration; when the microprocessor 130 does not receive a power-off instruction, it keeps the corresponding switch device 120 turned on, continuously supplies power to the device under test 200, and keeps the device under test 200 in the current state.

[0036] The signal receiving module 110 corresponds to the switch device 120 one by one, forming several test loops, which can connect multiple devices under test for simultaneous testing, and the power supply of each device under test can be controlled separately. The test arrangement is simpler, the cost is lower, and the efficiency is higher. In addition, when the microprocessor 130 does not receive the power-off instruction sent by the device under test 200, it will not trigger the power-off, so that the device under test 200 can maintain the fault state, which is convenient for the tester to record and analyze the fault.

[0037] Example 2

[0038] This embodiment is a further improvement of the embodiment 1, and the repeated contents are not repeated. In this embodiment, when the microprocessor 130 receives the power-off instruction, it turns off the switch device 120 to power off the device under test 200, and after the first preset time, it turns on the switch device 120 to power on the device under test 200. The first preset time is the power-off duration.

[0039] Preferably, the power-on and power-off test system further includes: a time setting module 140 and a display module 150. The time setting module 140 and the display module 150 are respectively connected to the microprocessor 130. The time setting module 140 is used to set the value of the first preset time length. The display module 150 is used to display the setting result when setting the value of the first preset time length; during the test, the power-off information of each test circuit is displayed.

[0040] Preferably, the signal receiving module 110 is connected to the microprocessor 130 via a delay and manual trigger circuit 160. The delay and manual trigger circuit 160 includes: a circuit for filtering out invalid power-off instructions and converting valid power-off instructions into valid signals; and a manual trigger circuit for sending valid signals to the microprocessor 130.

[0041] The delay circuit allows a high level that lasts for a period of time to be transmitted, which can filter out the burr interference and abnormal signal fluctuations generated during the power-on and power-off process of the tested device 200, ensuring that the signals transmitted to the microprocessor 130 are valid signals, and avoiding the situation where the test fails due to signal abnormalities caused by abnormal signals generated during the uncontrolled stage of the device and module.

[0042] Preferably, the signal receiving module 110 receives the power-off instruction sent by the device under test 200 and transmits the power-off instruction to the delay circuit. The delay circuit determines whether the power-off instruction is valid and filters out invalid power-off instructions; the manual trigger circuit outputs the valid signal representing the valid power-off instruction to the microprocessor 130.

[0043] Preferably, the power-off instruction is a continuous high-level signal. The delay circuit determines whether the power-off instruction is valid by determining whether the high-level duration of the power-off instruction meets the second preset duration. The delay circuit filters out high-level signals with a duration shorter than the second preset duration, ensuring that the power-off instruction transmitted to the microprocessor 130 is a high-level signal with a duration meeting the second preset duration.

[0044] Preferably, the switch device 120 is connected to the power supply module 170, and the switch device 120 switches on or off the power supply module 170 to the tested device 200 in response to the regulation of the microprocessor 130. Preferably, the power supply module 170 can use an AC power output or a DC power output, so that the present embodiment can support abnormal power-on and power-off tests of AC power output or DC power output, can cover the test of AC equipment or DC equipment, and increase the coverage of test equipment types.

[0045] In the traditional method of manual power-off testing by testers, one tester works 8 hours a day, assuming that 6 hours of the work can be done uninterruptedly for the test of plugging and unplugging the power supply. However, when testing with this embodiment, the time for configuring the test program and configuration tool running in the device under test is only about 3 minutes, which is negligible. After the test starts, the test can be done uninterruptedly for 24 hours, and the test efficiency of a single device is increased by 4 times.

[0046] This embodiment supports simultaneous testing of multiple devices. The tested devices 200 are all powered by the power supply module 170, and the tests between multiple devices are performed independently without affecting each other. In the traditional manual testing method, assuming that a tester reasonably utilizes the waiting time during the boot process, two devices can be tested at the same time. The tool used by the present invention can support simultaneous testing of 8-way devices under test, and its testing efficiency is equivalent to that of 4 testers testing at the same time. In addition to its advantage of uninterrupted testing, its testing efficiency can reach 16 times the efficiency of traditional manual testing. Greatly reduce the manpower input for testing and shorten the testing time.

[0047] Example 3

[0048] This embodiment is a further improvement of Embodiment 1 and Embodiment 2, and the repeated contents are not repeated here.

[0049] The signal receiving module 110 may be a USB to IO module. Preferably, the device under test 200 is configured with at least one USB interface, supports power-on, and can run a test program. When the test program is running and the conditions for active power-off are met, the device under test 200 can operate the register of the USB to IO module through the test program, so that the USB to IO module outputs a high level from the IO port, triggering the subsequent power-off process of the power-on and power-off test system.

[0050] In this embodiment, the signal receiving module 110 uses a common interface form of a USB interface to connect to the communication port of the device under test 200. The test program running on the device under test 200 can control the power on and off of the device through this USB to IO module. This method can cover many electronic devices with USB interfaces, and has strong versatility and practicality.

[0051] Preferably, the USB to IO module uses a universal USB interface to connect to the USB communication port of the device under test 200, so that the test program running on the device under test 200 can directly write to its IO register, thereby raising and lowering the level of the IO port of the USB to IO module, so that the USB to IO module can output high and low level signals.

[0052] In the actual test process, since the tested device 200 and the USB to IO module are frequently powered on and off abnormally, during the power on and off process, the IO output cannot be controlled, and abnormal high-level glitches may occur.

[0053] See also Figure 2 The delay circuit in the delay and manual trigger circuit 160 allows a high level (valid power-off instruction) that meets the time T1 (second preset time length) to pass, while a glitch signal shorter than the time T1 is filtered and not received by the microprocessor 130. The T1 time length can be set, specifically, by adjusting the resistance value of the resistor R2 to change the delay time T1 of the RC delay circuit.

[0054] The manual trigger circuit in the delay and manual trigger circuit 160 can realize a manual trigger function. There is a button in the manual trigger circuit. After pressing the button, a valid signal can be sent to the microprocessor 130.

[0055] See also Figure 2 The delay circuit is composed of a pull-down resistor R1, a resistor R2, a capacitor C1, an N-type MOSFET tube Q1, and a pull-up resistor R3. When there is no power-off instruction input to the delay circuit or the input level of the delay circuit is low, due to the existence of the pull-down resistor R1, the G pole voltage of the N-type MOSFET Q1 is low, and the Q1 tube is cut off. Due to the existence of the pull-up resistor R3, the output of the effective signal output end is high level. At this time, the microprocessor 130 believes that there is no effective signal input and does not perform switch control.

[0056] When a continuous high-level signal is input into the delay circuit, the duration of the high-level signal is defined as Tm. When Tm>T1 (the second preset duration), it can be considered that the input to the delay circuit is a continuous high-level signal (valid power-off instruction). At this time, the G pole voltage VGS of Q1 is greater than the turn-on threshold VGSth, the D pole and S pole of Q1 are turned on, and the voltage at the effective signal output end is pulled down. At this time, the microprocessor 130 receives a valid signal (low level) and controls the switch device 120 of the corresponding port to disconnect the power supply.

[0057] The duration of T1 is related to the input voltage value VS of the delay circuit, the value of resistor R2, the value of capacitor C1, and the VGSth value of the N-type MOSFET. The specific calculation formula is: VGSth=VS[1-e (-T1 / RC)], then T1=-RCln(1-VGSth / VS), e is a natural constant. Preferably, VS=5V. Preferably, R2=10KOhm, C1=100uF, VGSth of Q1=2V, and T1≈0.51s is calculated. That is, if the input 5V high level lasts for more than 0.51s, the D pole and S pole of Q1 are turned on, the effective signal output terminal is grounded, and the microprocessor 130 obtains a low-level effective signal. By adjusting the values ​​of R2 and C1, the delay time T1 of the delay circuit can be adjusted to filter glitches and interference.

[0058] See also Figure 2 The manual trigger circuit is a normally open self-recovery button SW1, one end of which is connected to the effective signal output terminal and the other end is grounded. When the button is pressed, both ends of SW1 are connected, the effective signal output terminal is grounded, and a low-level effective signal is output to the microprocessor 130, thereby realizing manual triggering.

[0059] Preferably, the external power supply supplies power to the multi-channel power-on and power-off test system through the power supply module 170. Preferably, the power that the power supply module 170 can provide needs to be greater than the sum of the power of the multi-channel power-on and power-off test system and all the tested devices 200.

[0060] Preferably, the switch device 120 may be a power load switch such as a relay or a field effect transistor.

[0061] Preferably, the microprocessor 130 can switch the state of the switch device 120 by outputting a control signal. When the switch device 120 is in the on state, the switch device 120 can connect the power supply channel from the power supply module 170 to the device under test 200, so that the device under test 200 is powered on and operated. When the switch device 120 is in the off state, the switch device 120 disconnects the power supply channel from the power supply module 170 to the device under test 200, so that the device under test 200 is powered off.

[0062] Preferably, when the output of the microprocessor 130 is in a default initial state, the switch device 120 is in an off state, and the current output from the power supply module 170 cannot enter the tested device 200 to turn it on.

[0063] Preferably, there are multiple signal receiving modules 110, delay and manual trigger circuits 160, and switch devices 120, and the number of signal receiving modules 110, delay and manual trigger circuits 160, and switch devices 120 is the same. The signal receiving modules 110, delay and manual trigger circuits 160, and switch devices 120 correspond one to one, and form multiple test loops with different IO ports of the microprocessor 130 and different devices under test 200. Each test loop operates independently without interfering with each other.

[0064] See also Figure 1 Preferably, n signal receiving modules 110, n delay and manual trigger circuits 160, n switch devices 120 and n test loops. Preferably, the microprocessor 130 and the n IO ports for receiving valid signals are numbered as signal receiving ports 1 to n, respectively, and the n IO ports of the microprocessor 130 for the control signal for controlling the on and off of the switch device 120 are numbered as signal output ports 1 to n.

[0065] The signal receiving module 110, the delay and manual trigger circuit 160, the signal receiving port of the microprocessor 130, the signal output port of the microprocessor 130, the switch device 120, and the tested device 200 form a test loop.

[0066] Preferably, the multi-channel power-on and power-off testing system provided in this embodiment may include n test loops.

[0067] In a test loop, the preset program built into the microprocessor 130 can adjust the control signal output according to the effective signal, thereby controlling the on and off of the switch device 120 in the test loop. The effective signal is: the effective power-off instruction sent by the device under test 200, which is converted and generated by the signal receiving module 110 and the delay and manual trigger circuit 160. Preferably, the preset program of the microprocessor 130 is stored in the non-volatile storage inside the microprocessor 130, and the program is not lost after power failure.

[0068] Preferably, the time setting module 140 may use a time setting button. The time setting button is connected to the microprocessor 130. The tester can set the value of the first preset time length stored in the microprocessor 130 through the time setting button.

[0069] When the value of the first preset time is set, the microprocessor 130 saves it immediately, and when it is powered on again after a power outage, the microprocessor 130 runs by default according to the first preset time set last time until the tester resets the value of the first preset time using the time setting button.

[0070] When a valid signal enters a certain IO port of the microprocessor 130, the microprocessor 130 immediately outputs a control signal to turn off the corresponding switch device 120, thereby powering off the device under test 200 in the corresponding test loop. After the countdown of the first preset time, the microprocessor 130 re-outputs a control signal to turn on the corresponding switch device 120, thereby powering on the device under test 200 in the corresponding test loop.

[0071] Preferably, the display module 150 is communicatively connected to the microprocessor 130 .

[0072] When the tester uses the time setting button, the display module 150 can provide display feedback to facilitate the tester to set the delayed power-on time of each test loop, that is, the value of the first preset time length.

[0073] When the microprocessor 130 receives a valid signal of a certain test loop X (X≤n) and outputs a power-off control signal to the corresponding switch device 120, the display module 150 can display the test loop number X and the countdown starting from the first preset time length. When the countdown reaches 0, the microprocessor 130 reopens the switch device 120 of the test loop X, so that the tested device 200 in the test loop X is powered on again. When a test system has multiple test loops in use at the same time, the display module alternately displays the countdown for each test loop to be powered on again.

[0074] This embodiment uses the microprocessor 130, the time setting module 140 and the display module 150 to conveniently set the countdown time and observe the running status of the tool, thereby lowering the operating threshold and saving the operating time of the test.

[0075] Preferably, after the multi-channel power-on and power-off test system provided in this embodiment is connected to an external power supply, the microprocessor 130 loads a preset program, completes initialization, and turns off all switch devices 120 by default, so that the tested devices 200 in all test loops are in a power-off state; and waits for valid signal input.

[0076] When the microprocessor 130 receives a valid signal on a certain test loop, the microprocessor 130 turns off the switch device 120 of this test loop, and the microprocessor 130 starts a countdown from a first preset time length. When the countdown returns to zero, the microprocessor 130 outputs a control signal to the switch device 120 of the test loop, turning on the switch device 120, supplying power to the device under test 200 of this test loop, and then starting the device under test 200.

[0077] See also Figure 3 The process of testing the device under test 200 in a test loop may include the following steps:

[0078] S100, external power is input into the multi-channel power-on and power-off test system through the interface of the power supply module 170, and then step S200 is executed.

[0079] S200, the microprocessor 130 is powered on and initialized, and then step S300 is executed.

[0080] S300: Whether the value of the first preset duration has been set; if not, execute step S310; if it has been set, execute step S400.

[0081] S310, setting a first preset duration through the time setting module 140 and storing it in the microprocessor 130, and executing step S400.

[0082] S400, the tester presses the manual trigger button to send a valid signal to the microprocessor 130, and then executes step S500.

[0083] S500, the microprocessor 130 detects whether a valid signal is received; if a valid signal is received, step S600 is executed; if no valid signal is received, step S500 is continued to be executed.

[0084] S600, the microprocessor 130 turns off the switch device 120 corresponding to the valid signal, and displays the set countdown through the display module 150. When the countdown returns to zero, the microprocessor 130 sends a conduction signal to the corresponding switch device 120, and executes step S700.

[0085] S700 , the switch device 120 is turned on to power on the device under test 200 in the test loop, and then step S800 is executed.

[0086] S800: Whether the test program loaded in the tested device 200 sends a valid signal to the signal receiving module 110; if yes, execute step S500; if no, execute step S900.

[0087] S900, the switch device 120 remains turned on, continuously supplies power to the device under test 200, and the device under test 200 remains in a fault state, waiting for the tester to record and analyze; then execute step S1000;

[0088] S1000, after recording and analyzing the fault, the tester determines whether to continue testing; if so, the test returns to step S400; if not, the test is not continued, step S1100 is executed.

[0089] S1100, end the test.

[0090] Preferably, during the testing process, this embodiment can retain the fault scene, waiting for the testers and developers to analyze and debug the fault problem.

[0091] The traditional test method uses the power-on and power-on signals of the device under test 200 as the conditions for executing the power-off test. In this method, as long as the device under test 200 is successfully powered on, it is considered that the device under test 200 has been powered on normally once, and the conditions for performing the power-off test are met. In actual situations, from the power-on of the device under test 200 to the smooth entry of the operating system of the device under test 200 and the normal startup of the service program carried by the device under test 200, there is still a possibility of failure in this process. In this embodiment, the test program running on the device under test 200 sends a power-off instruction, and the prerequisites for performing the power-off test cycle may include: the test program carried by the device under test 200 can run normally; thereby ensuring that before the power-off test cycle is performed, the device under test 200 has completed a complete and successful power-on startup process. When the test program carried by the device under test 200 does not run normally, the power off will not be triggered.

[0092] Based on the requirements for test start control and test continuation after test interruption in the actual test process, in order to cover a wider range of test scenarios, this embodiment sets a manual trigger button. At the beginning of the test, the button is pressed to manually trigger the first countdown. After the countdown ends, the tested device 200 is powered on and a normal test cycle begins. In the event of an abnormal phenomenon causing the test to be suspended, if the test needs to be continued, the manual trigger button can be pressed to continue the test.

[0093] Example 4

[0094] This embodiment provides a multi-channel power-on and power-off test method. The multi-channel power-on and power-off test method provided by this embodiment can be performed using the multi-channel power-on and power-off test system involved in Embodiment 1, Embodiment 2 and Embodiment 3.

[0095] The multi-channel power-on and power-off testing method provided in this embodiment may include the following steps:

[0096] S1: Connect the communication port of the device under test 200 to the signal receiving module 110; connect the power supply port of the device under test 200 to the switch device 120; load the test program to the device under test 200; when the test program is running, the device under test 200 can send a power-off instruction to the microprocessor 130 through the communication port;

[0097] S2: Setting the power-off duration through the time setting module 140;

[0098] S3: Sending a valid power-off instruction to the microprocessor 130 through the delay and manual trigger circuit 160 to start the test;

[0099] S4, the microprocessor 130 receives a valid power-off instruction, turns off the corresponding switch device 120, and turns on the switch device 120 after the power-off duration has elapsed;

[0100] S5. When the microprocessor 130 does not receive a valid power-off instruction, the switch device 120 remains turned on and continues to supply power to the device under test 200, so that the device under test 200 remains in the current state.

[0101] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-channel power-on and power-off test system, characterized in that: include: A plurality of signal receiving modules (110) for connecting to a communication port of a device under test (200), wherein the device under test (200) is loaded with a test program; when the test program is running, the device under test (200) can send a power-off instruction to the signal receiving module (110) through the communication port; A plurality of switch devices (120) used to connect the power supply port of the device under test (200) to realize power on and off of the device under test (200); The signal receiving module (110) and the switch device (120) are respectively connected to a microprocessor (130) for communication; and the signal receiving module (110) corresponds to the switch device (120) one by one, forming a plurality of test loops; The signal receiving module (110) transmits the power-off instruction to the microprocessor (130); the microprocessor (130) controls the on / off of the switch device (120) in the same test circuit as the signal receiving module (110) according to the power-off instruction; wherein, when the microprocessor (130) receives the power-off instruction, it turns off the corresponding switch device (120), and turns on the switch device (120) after a preset power-off duration; when the microprocessor (130) does not receive the power-off instruction, it keeps the corresponding switch device (120) turned on, and continues to supply power to the device under test (200), so that the device under test (200) maintains a current state.

2. A multi-channel power-on and power-off test system according to claim 1, characterized in that: When receiving the power-off instruction, the microprocessor (130) disconnects the switch device (120) to power off the device under test (200), and after a first preset time, turns on the switch device (120) to power on the device under test (200).

3. A multi-channel power-on and power-off test system according to claim 2, characterized in that: The power-on and power-off test system further comprises: a time setting module (140) and a display module (150); The time setting module (140) and the display module (150) are respectively data-connected to the microprocessor (130); The time setting module (140) is used to set the value of the first preset time length; The display module (150) is used to display the setting result when setting the first preset time value; during testing, it displays the power-off information of each test circuit.

4. A multi-channel power-on and power-off test system according to claim 1, characterized in that: The signal receiving module (110) is connected to the microprocessor (130) via a delay and manual trigger circuit (160); The delay and manual trigger circuit (160) comprises: The delay circuit is used to filter out invalid power-off instructions and convert valid power-off instructions into valid signals; A manual trigger circuit is used to send a valid signal to the microprocessor (130).

5. A multi-channel power-on and power-off test system according to claim 4, characterized in that: The signal receiving module (110) receives a power-off instruction sent by the device under test (200) and transmits the power-off instruction to the delay line; The delay circuit determines whether the power-off instruction is valid, and filters out invalid power-off instructions; The manual trigger circuit inputs a valid signal representing a valid power-off instruction to the microprocessor (130).

6. A multi-channel power-on and power-off test system according to claim 5, characterized in that: The power-off instruction is a continuous high-level signal; The delay circuit determines whether the power-off instruction is valid by: determining whether the high level duration of the power-off instruction meets a second preset duration; The delay circuit filters out high-level signals whose duration is shorter than the second preset time length, thereby ensuring that the power-off instruction transmitted to the microprocessor (130) is a high-level signal whose duration meets the second preset time length.

7. A multi-channel power-on and power-off test system according to claim 1, characterized in that: The switch device (120) is connected to a power supply module (170), and the switch device (120) switches on or off the power supply module (170) to the device under test (200) in response to regulation by the microprocessor (130).

8. A multi-channel power-on and power-off testing method, characterized in that: At least the following steps are included: S1: connecting the communication port of the device under test (200) to the signal receiving module (110); connecting the power supply port of the device under test (200) to the switch device (120); loading a test program for the device under test (200), and when running the test program, the device under test (200) can send a power-off instruction to the microprocessor (130) through the communication port; wherein, upon receiving the power-off instruction, the microprocessor (130) turns off the corresponding switch device (120), and turns on the switch device (120) after a preset power-off duration; and, upon not receiving the power-off instruction, the microprocessor (130) keeps the corresponding switch device (120) turned on, continuously supplies power to the device under test (200), and keeps the device under test (200) in the current state; S2: Setting the duration of power-off through the time setting module (140); S3: Sending a power-off instruction to the microprocessor (130) via the delay and manual trigger circuit (160) to start the test.

9. A multi-channel power-on and power-off testing method according to claim 8, characterized in that: The test methods also include: S4: The microprocessor (130) receives a valid power-off instruction, turns off the corresponding switch device (120), and turns on the switch device (120) after the power-off duration has elapsed.

10. A multi-channel power-on and power-off testing method according to claim 8, characterized in that: The test method also includes: S5. When the microprocessor (130) does not receive a valid power-off instruction, the switch device (120) remains turned on and continues to supply power to the device under test (200), so that the device under test (200) remains in a current state.

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