Memory Protection Unit and System

Abstract

The present invention belongs to the field of chip design, and provides a memory protection unit and a system. The memory protection system comprises a memory protection unit and at least one data transceiver unit, the data transceiver unit comprises a data transceiver interface and a buffer area, the memory protection unit comprises a memory protection data interface and a channel control circuit, when the memory protection unit transmits and receives data to be transmitted through the data transceiver interface through the memory protection data interface, the data to be transmitted is buffered in the buffer area, and the channel control circuit controls the conduction and disconnection of a data transmission channel for the data to be transmitted according to a protection control instruction; the buffer area inside the upstream / downstream data transceiver unit is used to replace the original self-set buffer area of ​​the memory protection unit, so as to optimize the structure of the memory protection unit and improve the link access efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of chip design, and in particular relates to a memory protection unit and system. Background Art

[0002] The memory protection unit (MPU) isolates the kernel data code and user data code of the memory by setting the memory access characteristics (such as supporting only privileged access or full access) and memory attributes (such as cacheable, bufferable, and shareable) of different storage areas to avoid memory trampling, thereby improving system reliability.

[0003] In the system-on-chip (SOC), the Advanced Microcontroller Bus Architecture (AMBA) is usually used for layout. This layout not only needs to meet the requirements of memory protection, but also needs to ensure that the data transmission between devices meets the bus protocol requirements. As an independent individual, the existing MPU usually sets corresponding data buffers at the sending data port a and the receiving data port b to meet the bus protocol requirements. Figure 1 , each MPU stores the data from the sender in the data buffer area A corresponding to the send data port a, transmits it to the data buffer area B corresponding to the receive data port b through the data transmission channel, and forwards it to the receiver from the data buffer area B. However, medium and large-scale SOC systems have a large number of ports to be protected, and the MPU needs to set up data ports and buffer areas corresponding to these protected ports. As the MPU buffer area increases, the MPU's PPA (Power, Performance, Area) overhead will increase exponentially. At the same time, the MPU needs to complete storage-forwarding in the MPU itself during the data transmission protection process, which increases the latency of the entire link access.

[0004] Therefore, it is necessary to provide a memory protection unit and system to solve the above problems existing in the prior art. Summary of the invention

[0005] In order to solve the problem in the prior art that a cache area for each data port is set inside the MPU, and too many cache area settings cause the PPA overhead in the MPU to increase exponentially and the link access delay to increase, the present application provides a memory protection unit and system.

[0006] The present application provides a memory protection unit and system, which adopts the following technical solutions:

[0007] A memory protection system comprises a memory protection unit and at least one data transceiver unit, wherein the data transceiver unit comprises a data transceiver interface and a buffer area, and the memory protection unit comprises a memory protection data interface and a channel control circuit;

[0008] When the memory protection unit receives and sends data to be transmitted through the data transceiver interface through the memory protection data interface, the data to be transmitted is cached in the cache area; and the channel control circuit controls the conduction and disconnection of the data transmission channel through which the data to be transmitted passes according to the protection control instruction.

[0009] By adopting the above technical solution, when the data transceiver unit uses the memory protection unit to perform data transceiver protection, the cache area is set at the data transceiver unit, and the memory protection unit only needs to set the corresponding memory protection data interface and channel control circuit, and the memory protection unit is structurally optimized to ensure the PPA overhead in the memory protection unit and improve the link access efficiency in the memory protection unit. In addition, the cooperation between the memory protection unit and the data transceiver unit ensures the integrity of the link access.

[0010] Optionally, the data transceiver interface is connected to the memory protection data interface and complies with a preset data transmission protocol, so that the data transceiver interface, the memory protection data interface and the cache area constitute a protocol virtual unit.

[0011] By adopting the above technical solution, the data transceiver interface, the memory protection data interface and the cache area constitute a protocol virtual unit, which can transmit command signals (including write command signals and read command signals), perform data transmission and realize data caching. The virtual unit ensures the coordination completion of the data transmission protocol, and does not require the memory protection unit MPU to independently guarantee the function of the preset data transmission protocol. Instead, from the perspective of coordination of the upstream / downstream data transceiver units, the cache area inside the upstream / downstream data transceiver units is utilized, and no additional cache area is designed inside the memory protection unit MPU.

[0012] Optionally, the data transmission protocol is an AXI protocol.

[0013] By adopting the above technical solution, the data transmission protocol is set to the AXI protocol, ensuring that the SOC system where the data transceiver unit and the memory protection unit are located can meet the data protection requirements of many ports.

[0014] Optionally, the protection control instruction includes a data protection instruction and a data transmission instruction. The channel control circuit generates a back pressure signal according to the data protection instruction to disconnect the data transmission channel and intercept the command signal. The channel control circuit controls the data transmission channel to be turned on and executes the operation corresponding to the command signal according to the data transmission instruction.

[0015] By adopting the above technical solution, the data transmission instruction indicates the normal working mode. At this time, the channel control circuit directly turns on the data transmission channel so that the data to be transmitted at the beginning can be transmitted to the end. In other words, the data transceiver unit connected to itself can freely send and receive data and execute command signals through the data transmission channel.

[0016] The data protection instruction indicates the protection working mode. At this time, the channel control circuit generates a back pressure signal to shut down the data transmission channel. The data to be transmitted at the beginning cannot be transmitted to the end. In other words, the data transceiver unit cannot transmit data through the data transmission channel. At the same time, the command signal corresponding to the channel control circuit is intercepted, and the execution of the operation corresponding to the command signal is interrupted to avoid data leakage.

[0017] Optionally, the data transceiver unit includes a data sending unit, a data transceiver interface of the data sending unit serves as a first transceiver interface, and a buffer area of ​​the data sending unit serves as a first buffer area; a memory protection data interface cooperating with the first transceiver interface serves as a first memory interface;

[0018] When the channel control circuit turns on the data transmission channel, the data to be transmitted in the first buffer area passes through the first transceiver interface and the first memory interface connected to each other, and then is transmitted to the target unit connected to the memory protection unit through the data transmission channel.

[0019] By adopting the above technical solution, the cache area originally set in the memory protection unit is set in the data sending unit, that is, the "first cache area" in the "first cache area, first transceiver interface, first memory interface" is mounted on one side of the data sending unit.

[0020] Optionally, the data transceiver unit includes a data receiving unit, the data transceiver interface of the data receiving unit serves as a second transceiver interface, and the buffer area of ​​the data receiving unit serves as a second buffer area; the memory protection data interface cooperating with the second transceiver interface serves as a second memory interface;

[0021] When the channel control circuit turns on the data transmission channel, the starting unit connected to the memory protection unit transmits the data to be transmitted through the data transmission channel, and then reaches the second cache area through the second memory interface and the second transceiver interface connected to each other.

[0022] By adopting the above technical solution, the cache area originally set in the memory protection unit is set in the data receiving unit, that is, the "second cache area" in the "second memory interface, second transceiver interface, second cache area" is mounted on one side of the data receiving unit.

[0023] Optionally, the data transceiver unit includes a data sending unit and a data receiving unit, the data transceiver interface of the data sending unit serves as a first transceiver interface, and the buffer area of ​​the data sending unit serves as a first buffer area; the memory protection data interface cooperating with the first transceiver interface serves as a first memory interface; the data transceiver interface of the data receiving unit serves as a second transceiver interface, and the buffer area of ​​the data receiving unit serves as a second buffer area; the memory protection data interface cooperating with the second transceiver interface serves as a second memory interface;

[0024] When the channel control circuit turns on the data transmission channel, the data to be transmitted in the first buffer area passes through the interconnected first transceiver interface and the first memory interface, and then through the data transmission channel, the interconnected second memory interface and the second transceiver interface to reach the second buffer area.

[0025] By adopting the above technical solution, the cache area originally intended to be set in the memory protection unit is set in the data sending unit and the data receiving unit, that is, the "first cache area" in the "first cache area, first transceiver interface, first memory interface" is mounted on a single side of the data sending unit, and the "second cache area" in the "second memory interface, second transceiver interface, second cache area" is mounted on a single side of the data receiving unit.

[0026] Optionally, when the channel control circuit shuts down the data transmission channel according to the data protection instruction, the memory protection unit intercepts the write command signal from the data sending unit, sends the data to be transmitted from the data sending unit back to the first cache area through the data transmission channel, generates a write operation response signal according to the write command signal, and transmits the write operation response signal to the first cache area and the second cache area respectively through the operation data return channel.

[0027] By adopting the above technical solution, the channel control circuit not only controls the data transmission channel to be shut down according to the data protection instruction, but also intercepts the write command signal, thereby interrupting the execution of the write command signal to avoid data interference.

[0028] Optionally, when the channel control circuit shuts down the data transmission channel according to the data protection instruction, the memory protection unit intercepts the read command signal from the data receiving unit, generates a read operation response signal according to the read command signal, and transmits the read operation response signal to the first cache area and the second cache area respectively through the operation data return channel.

[0029] By adopting the above technical solution, the channel control circuit not only controls the data transmission channel to be shut down according to the data protection instruction, but also intercepts the read command signal, thereby interrupting the execution of the read command signal to avoid data interference.

[0030] The present invention also provides a memory protection unit, which has a memory protection data interface and a channel control circuit. The memory protection data interface cooperates with a data transceiver interface of a data transceiver unit connected to the memory protection unit. The memory protection data interface, the data transceiver interface and a cache area located in the data transceiver unit constitute a protocol virtual unit that meets a preset data transmission protocol. The channel control circuit controls the on and off of the data transmission channel according to the protection control instruction.

[0031] By adopting the above technical solution, the cache area originally set with the memory protection unit is modified to the data transceiver unit connected to the memory protection unit. The memory protection unit only needs to set the corresponding memory protection data interface and channel control circuit, and the memory protection unit is structurally optimized to ensure the PPA overhead in the memory protection unit and improve the link access efficiency in the memory protection unit. In addition, the cooperation between the memory protection unit and the data transceiver unit ensures the integrity of the link access.

[0032] In summary, the present application includes at least one of the following beneficial technical effects:

[0033] 1. Modify the cache area originally set with the memory protection unit to the data transceiver unit connected to the memory protection unit. The memory protection unit only needs to set the corresponding memory protection data interface and channel control circuit, optimize the structure of the memory protection unit, reduce PPA overhead, and improve link access efficiency.

[0034] 2. While the channel control circuit controls the shutdown of the data transmission channel according to the data protection instruction, it also intercepts the command signal, thereby interrupting the execution of the command signal to avoid data interference.

[0035] 3. The memory protection data interface, the data transceiver interface and the buffer area located in the data transceiver unit constitute a protocol virtual unit that meets the preset data transmission protocol. The integrity of the link access is ensured through the cooperation between the memory protection unit and the data transceiver unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of the structure of a storage protection unit in the background technology;

[0037] Figure 2 A schematic diagram of the structure of the memory protection system provided by the present invention;

[0038] Figure 3 yes Figure 2 A schematic diagram of the protocol virtual unit formed;

[0039] Figure 4 yes Figure 2A schematic diagram showing a data transceiver unit being configured as a data sending unit;

[0040] Figure 5 yes Figure 2 A schematic diagram showing a data transceiver unit being configured as a data receiving unit;

[0041] Figure 6 yes Figure 3 A schematic diagram in which the data transceiver unit is configured as a data sending unit and a data receiving unit;

[0042] Figure 7 yes Figure 6 The transmission diagram of the write command signal when the data transmission channel is turned on;

[0043] Figure 8 yes Figure 6 The transmission diagram of the write command signal when the data transmission channel is turned off;

[0044] Fig. 9 yes Figure 6 The transmission diagram of the read command signal when the data transmission channel is turned on;

[0045] Fig.10 yes Figure 6 FIG. 1 is a transmission diagram of a read command signal when the data transmission channel is turned off.

[0046] The reference numerals in the accompanying drawings are:

[0047] 10. Memory protection unit; 20. Data transceiver unit; 201. Data transceiver interface; 202. Cache area; 101. Memory protection data interface; 102. Channel control circuit; 103. Data transmission channel; 104. Command transmission channel; 20-1. Data sending unit; 201-1. First transceiver interface; 202-1. First cache area; 101-1. First memory interface; 20-2. Data receiving unit; 201-2. Second transceiver interface; 202-2. Second cache area; 101-2. Second memory interface; aw. Write command signal; b. Write operation response signal; ar. Read command signal; r. Read operation response signal. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0049] In view of the problems existing in the prior art, an embodiment of the present invention provides a memory protection system. Figure 2 , the memory protection system includes a memory protection unit 10 and at least one data transceiver unit 20. The data transceiver unit 20 includes a data transceiver interface 201 and a buffer area 202, and the memory protection unit 10 includes a memory protection data interface 101, a channel control circuit 102, a data transmission channel 103, and a command transmission channel 104. When the memory protection unit 10 receives and sends data to be transmitted through the data transceiver interface 201 through the memory protection data interface 101, the data to be transmitted is buffered in the buffer area 202; the channel control circuit 102 controls the data transmission channel 103 to be turned on and off according to the protection control instruction. The protection control instruction includes a data protection instruction and a data transmission instruction. The channel control circuit 102 generates a back pressure signal according to the data protection instruction to disconnect the data transmission channel 103 and intercept the command signal. The channel control circuit 102 controls the data transmission channel 103 to be turned on and executes the operation corresponding to the command signal according to the data transmission instruction.

[0050] In this solution, the memory protection unit 10 of the memory protection system is connected to at least one data transceiver unit 20, which means that the memory protection unit 10 can be connected to one data transceiver unit 20, or multiple data transceiver units 20, or can be connected to the data transceiver unit 20 while also being connected to a data transmission matrix, other data units, etc. Moreover, the data transceiver unit 20 can send data to be transmitted through the memory protection unit 10, or can receive data to be transmitted through the memory protection unit 10.

[0051] For the connection relationship between the data transceiver unit 20 and the memory protection unit 10: Figure 1 In the prior art, a buffer area for the memory protection data interface 101 connected to the data transceiver unit 20 is set in the memory protection unit 10, and in this case, reference Figure 2, the cache area is transferred to the connected data transceiver unit 20, and the stability of the data transmission link in the system is ensured through the cooperation between the "cache area 202-data transceiver interface 201-memory protection data interface 101". This case optimizes the structure of the memory protection unit 10, greatly reducing the proportion of the cache area in the memory protection unit 10 in the overall storage space, ensuring the stability of the PPA overhead in the memory protection unit, and improving the link access efficiency in the memory protection unit 10.

[0052] For the memory protection unit 10, the on and off of the data transmission channel 103 has the following key points:

[0053] (1) The source of the protection control instruction can be generated by the staff manually adjusting the system (for example, during the system debugging process), or it can be generated by other devices connected to the system and captured by the system, etc. The protection control instruction can only be one of the data protection instruction and the data transmission instruction. One protection control instruction can control one data transmission channel 103 or multiple data transmission channels 103.

[0054] (2) The data transmission instruction indicates the normal working mode. At this time, the channel control circuit 102 directly turns on the data transmission channel 103 so that the data to be transmitted at the beginning can be transmitted to the end. In other words, the data transceiver unit 20 connected to itself can freely send and receive data and execute command signals through the data transmission channel 103. The data protection instruction indicates the protection working mode. At this time, the channel control circuit 102 generates a back pressure signal to shut down the data transmission channel 103. The data to be transmitted at the beginning cannot be transmitted to the end. In other words, the data transceiver unit 20 cannot perform data transmission through the data transmission channel 103.

[0055] (3) The memory protection unit 10 receives the command signal sent by the data transceiver unit 20 through the data transceiver interface through the memory protection data interface 101, and also receives the command signal generated by the connected data unit, data transmission matrix, etc. through the memory protection data interface 101 or other data interfaces. These command signals reach the memory protection unit 10 through the command transmission channel 104. In the normal working mode, the memory protection unit 10 reads the data to be transmitted in the direction indicated by these command signals, transmits the data to be transmitted in the direction indicated by these command signals, etc., and directly executes these command signals. In the protection working mode, the memory protection unit 10 directly cuts off the command transmission channel 104, thereby intercepting the command signal and interrupting the execution of the operation corresponding to the command signal to avoid data leakage.

[0056] In some examples, reference Figure 3The data transceiver interface 201 is connected to the memory protection data interface 101 and complies with the preset data transmission protocol, so that the data transceiver interface 201, the memory protection data interface 101 and the buffer area 202 constitute a protocol virtual unit. The virtual unit can transmit command signals (including write command signals and read command signals), perform data transmission, and realize data caching to ensure the coordination completion of the data transmission protocol. The memory protection unit 10 does not need to set up an additional buffer area to guarantee the function of the data transmission protocol alone. Instead, from the perspective of coordination between the upstream / downstream data transceiver unit 20, the buffer area 202 inside the upstream / downstream data transceiver unit 20 is used to achieve the same effect.

[0057] The data transmission protocol is preferably the AXI protocol. Correspondingly, the memory protection data interface 101 in the memory protection unit 10 and the data transceiver interface 201 of the data transceiver unit 20 both use interfaces of the composite AXI protocol, thereby ensuring that the data transmission between the memory protection data interface 101 and the data transceiver interface 201 meets the AXI protocol.

[0058] In some examples, reference Figure 4 As shown, the data transceiver unit 20 includes a data sending unit 20-1, a data transceiver interface 201 of the data sending unit 20-1 serves as a first transceiver interface 201-1, and a buffer area 202 of the data sending unit 20-1 serves as a first buffer area 202; and a memory protection data interface 101 that cooperates with the first transceiver interface 201-1 serves as a first memory interface 101-1. When the channel control circuit 102 turns on the data transmission channel 103, the data to be transmitted in the first buffer area 202 passes through the first transceiver interface 201-1 and the first memory interface 101-1 that are connected to each other, and then is transmitted to the target unit connected to the memory protection unit 10 through the data transmission channel 103.

[0059] In this example, the cache area 202 originally set in the memory protection unit 10 is set on one side of the data sending unit 20-1. One side of the memory protection unit 10 is connected to the data sending unit 20-1 mounted with the cache area 202, and the other side is connected to the target unit. When the data transmission instruction indicates the normal working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned on; the command transmission channel 104 transmits the command signal from the data sending unit 20-1 to the memory protection unit 10 to control the direction, speed and other indicators of data transmission in the data transmission channel 103, and then executes the command signal; the data to be transmitted in the first cache area 202 reaches the target unit through the first transceiver interface 201-1, the first memory interface 101-1, and the data transmission channel 103 that is turned on and complies with the command signal. When the data transmission instruction indicates the protection working mode, the channel control circuit 102 controls the generation of a back pressure signal to shut down the data transmission channel 103, and controls the command transmission channel 104 to be interrupted, thereby cutting off the reception of the command signal and interrupting the execution of the command signal. In addition, the data to be transmitted in the memory protection unit 10 will flow back to the first buffer area 202 of the data sending unit 20-1 through the first memory interface 101-1 and the first transceiver interface 201-1.

[0060] In some examples, reference Figure 5 As shown, the data transceiver unit 20 includes a data receiving unit 20-2, the data transceiver interface 201 of the data receiving unit 20-2 serves as a second transceiver interface 201-2, and the buffer area 202 of the data receiving unit 20-2 serves as a second buffer area 202-2; the memory protection data interface 101 that cooperates with the second transceiver interface 201-2 serves as a second memory interface 101-2. When the channel control circuit 102 turns on the data transmission channel 103, the starting unit connected to the memory protection unit 10 passes the data to be transmitted through the data transmission channel 103, and then reaches the second buffer area 202-2 through the second memory interface 101-2 and the second transceiver interface 201-2 that are connected to each other.

[0061] In this example, the cache area 202 originally set in the memory protection unit 10 is set on one side of the data receiving unit 20-2. One side of the memory protection unit 10 is connected to the starting unit, and the other side is connected to the data receiving unit 20-2 mounted with the second cache area 202-2. When the data transmission instruction indicates the normal working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned on; the command transmission channel 104 transmits the command signal from the data receiving unit 20-2 to the memory protection unit 10 to control the direction, speed and other indicators of data transmission in the data transmission channel 103, and then executes the command signal; the data to be transmitted from the starting unit passes through the data transmission channel 103, and then reaches the second cache area 202-2 of the data receiving unit 20-2 through the second memory interface 101-2 and the second transceiver interface 201-2. When the data transmission instruction indicates the protection working mode, the channel control circuit 102 controls the generation of a back pressure signal to shut down the data transmission channel 103, and controls the command transmission channel 104 to be interrupted, thereby cutting off the reception of the command signal and interrupting the execution of the command signal. In addition, the data to be transmitted retained in the memory protection unit 10 will be stored in the second cache area 202-2 of the data receiving unit 20-2 through the second memory interface 101-2 and the second transceiver interface 201-2.

[0062] In some embodiments, reference Figure 6 As shown, the data transceiver unit 20 includes a data sending unit 20-1 and a data receiving unit 20-2, the data transceiver interface 201 of the data sending unit 20-1 serves as the first transceiver interface 201-1, and the buffer area 202 of the data sending unit 20-1 serves as the first buffer area 202; the memory protection data interface 101 cooperating with the first transceiver interface 201-1 serves as the first memory interface 101-1; the data transceiver interface 201 of the data receiving unit 20-2 serves as the second transceiver interface 201-2, and the buffer area 202 of the data receiving unit 20-2 serves as the second buffer area 202-2; the memory protection data interface 101 cooperating with the second transceiver interface 201-2 serves as the second memory interface 101-2. When the channel control circuit 102 turns on the data transmission channel 103, the data to be transmitted in the first buffer area 202 passes through the interconnected first transceiver interface 201-1 and the first memory interface 101-1, and then through the data transmission channel 103, the interconnected second memory interface 101-2 and the second transceiver interface 201-2, and arrives at the second buffer area 202-2.

[0063] In this embodiment, if the command instruction sent by the data sending unit 20-1 to the command transmission channel 104 matches the command instruction sent by the data receiving unit 20-2 to the command transmission channel 104, the data transmission link of "data sending unit 20-1, memory protection unit 10, data received to Anyuan 20-2" is executed, that is, the data to be transmitted located in the first buffer area 202 arrives at the data receiving unit 20-2 through the first transceiver interface 201-1, the first memory interface 101-1, the turned-on data transmission channel 103, the second memory interface 101-2, and the second transceiver interface 201-2.

[0064] If the command instruction sent by the data sending unit 20-1 to the command transmission channel 104 does not match the command instruction sent by the data receiving unit 20-2 to the command transmission channel 104, it is regarded as Figure 4 The data transmission link on the sending end and Figure 5 The data transmission link on the receiving end side is divided into two separate data transmission links, and the two data transmission links are not integrated with each other.

[0065] The buffer area 202 originally set in the memory protection unit 10 is set on both sides of the data sending unit 20-1 and the data receiving unit 20-2. If the data transmission channel is turned off, in the memory protection unit 10, the data to be transmitted that has not passed through the data transmission channel flows back to the first buffer area 202 of the data sending unit 20-1 through the first memory interface 101-1 and the first transceiver interface 201-1, and the data with transmission that has passed through the data transmission channel is stored in the second buffer area 202-2 of the data receiving unit 20-2 through the second memory interface 101-2 and the second transceiver interface 201-2.

[0066] When the command signal is a write command signal aw:

[0067] (1) Reference Figure 7 , when the data transmission instruction indicates the normal working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned on, and the data sending unit 20-1 generates a write command signal aw, which is transmitted to the memory protection unit 10 through the command transmission channel 104. Since the command transmission channel 104 of the memory protection unit 10 is turned on, the memory protection unit 10 transmits the write command signal aw to the data receiving unit 20-2. The data sending unit 20-1 sends the data to be transmitted, which is cached in the first buffer area 202-1, to the data receiving unit 20-2 through the write operation data transmission channel w (a type of data transmission channel 103) of the memory protection unit 10. After writing the data to be transmitted, the data receiving unit 20-2 generates a write operation response signal b, which is fed back to the data sending unit 20-1 through the command transmission channel 104 again.

[0068] (2) Reference Figure 8 , when the data transmission instruction indicates the protection working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned off and cuts off the command transmission channel 104. The data sending unit 20-1 generates a write command signal aw. Since the command transmission channel 104 of the memory protection unit 10 is cut off, the write command signal aw cannot be transmitted to the data receiving unit 20-2. Since the data transmission channel 103 is turned off, the data to be transmitted that the data sending unit 20-1 caches in the first buffer area 202-1 cannot be transmitted through the write operation data transmission channel w (a type of data transmission channel 103). In addition, the memory protection unit 10 generates a back pressure signal to terminate the transmission of the write operation response signal b. Figure 8 The dashed lines in the figure indicate that transmission is not possible.

[0069] (3) Reference Fig. 9 , when the data transmission instruction indicates the normal working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned on, and the data sending unit 20-1 generates a read command signal ar, which is transmitted to the memory protection unit 10 through the command transmission channel 104. Since the command transmission channel 104 of the memory protection unit 10 is turned on, the memory protection unit 10 transmits the read command signal ar to the data receiving unit 20-2. The data receiving unit 20-2 provides the data to be transmitted, which is cached in the second buffer area 202-2, for the data sending unit 20-1 to read through the data transmission channel 103, and generates a read operation response signal r. The read operation response signal r is fed back to the data sending unit 20-1 through the command transmission channel 104 again.

[0070] (4) Reference Fig.10 , when the data transmission instruction indicates the protection working mode, the channel control circuit 102 controls the data transmission channel 103 to be turned off and cuts off the command transmission channel 104. The data sending unit 20-1 generates a read command signal ar. Since the command transmission channel 104 of the memory protection unit 10 is cut off, the read command signal ar cannot be transmitted to the data receiving unit 20-2. Since the data transmission channel 103 is turned off, the data to be transmitted that the data sending unit 20-1 caches in the first buffer area 202-1 cannot be read by the data sending unit 20-1 through the data transmission channel 103. In addition, the memory protection unit 10 generates a back pressure signal to stop the transmission of the read operation response signal r. Fig.10 The dashed lines in the figure indicate that transmission is not possible.

[0071] The present invention also provides a memory protection unit 10, which has a memory protection data interface 101 and a channel control circuit 102. The memory protection data interface 101 cooperates with the data transceiver interface 201 of the data transceiver unit 20 connected to the memory protection unit 10. The memory protection data interface 101, the data transceiver interface 201 and the cache area 202 located in the data transceiver unit 20 constitute a protocol virtual unit that meets the preset data transmission protocol. The channel control circuit 102 controls the on and off of the data transmission channel 103 according to the protection control instruction.

[0072] Other implementation details and working methods of the memory protection unit 10 disclosed in the present application are the same as or similar to the memory protection system described above and will not be repeated here.

[0073] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A memory protection system, characterized in that: It includes a memory protection unit and at least one data transceiver unit, the data transceiver unit includes a data transceiver interface and a buffer area, and the memory protection unit includes a memory protection data interface and a channel control circuit; When the memory protection unit sends and receives the data to be transmitted through the data transceiver interface through the memory protection data interface, the data to be transmitted is cached in the cache area; The channel control circuit controls the on and off of the data transmission channel through which the data to be transmitted passes according to the protection control instruction; Among them, the protection control instructions include data protection instructions and data transmission instructions. The channel control circuit generates a back pressure signal according to the data protection instruction to disconnect the data transmission channel and intercept the command signal. The channel control circuit controls the data transmission channel to be turned on and executes the operation corresponding to the command signal according to the data transmission instruction.

2. The memory protection system according to claim 1, characterized in that: The data transceiver interface is connected to the memory protection data interface and complies with a preset data transmission protocol, so that the data transceiver interface, the memory protection data interface and the buffer area constitute a protocol virtual unit.

3. The memory protection system according to claim 2, characterized in that: The data transmission protocol is the AXI protocol.

4. The memory protection system according to claim 1, characterized in that: The data transceiver unit includes a data sending unit, a data transceiver interface of the data sending unit is used as a first transceiver interface, and a buffer area of ​​the data sending unit is used as a first buffer area; a memory protection data interface coordinated with the first transceiver interface is used as a first memory interface; When the channel control circuit turns on the data transmission channel, the data to be transmitted in the first buffer area passes through the first transceiver interface and the first memory interface connected to each other, and then is transmitted to the target unit connected to the memory protection unit through the data transmission channel.

5. The memory protection system according to claim 1, characterized in that: The data transceiver unit includes a data receiving unit, a data transceiver interface of the data receiving unit serves as a second transceiver interface, and a buffer area of ​​the data receiving unit serves as a second buffer area; a memory protection data interface coordinated with the second transceiver interface serves as a second memory interface; When the channel control circuit turns on the data transmission channel, the starting unit connected to the memory protection unit transmits the data to be transmitted through the data transmission channel, and then reaches the second cache area through the second memory interface and the second transceiver interface connected to each other.

6. The memory protection system according to claim 1, characterized in that: The data transceiver unit includes a data sending unit and a data receiving unit, the data transceiver interface of the data sending unit serves as a first transceiver interface, and the buffer area of ​​the data sending unit serves as a first buffer area; the memory protection data interface coordinated with the first transceiver interface serves as a first memory interface; the data transceiver interface of the data receiving unit serves as a second transceiver interface, and the buffer area of ​​the data receiving unit serves as a second buffer area; the memory protection data interface coordinated with the second transceiver interface serves as a second memory interface; When the channel control circuit turns on the data transmission channel, the data to be transmitted in the first buffer area passes through the interconnected first transceiver interface and the first memory interface, and then through the data transmission channel, the interconnected second memory interface and the second transceiver interface to reach the second buffer area.

7. The memory protection system according to claim 6, characterized in that: When the channel control circuit follows the data protection instruction, the memory protection unit intercepts the write command signal from the data sending unit, sends the data to be transmitted from the data sending unit back to the first cache area through the data transmission channel, generates a write operation response signal according to the write command signal, and transmits the write operation response signal to the first cache area and the second cache area respectively through the operation data return channel.

8. The memory protection system according to claim 6, characterized in that: When the channel control circuit follows the data protection instruction, the memory protection unit intercepts the read command signal from the data receiving unit, generates a read operation response signal according to the read command signal, and transmits the read operation response signal to the first cache area and the second cache area respectively through the operation data return channel.

9. A memory protection unit, characterized in that: The memory protection unit has a memory protection data interface and a channel control circuit. The memory protection data interface cooperates with the data transceiver interface of the data transceiver unit connected to the memory protection unit. The memory protection data interface, the data transceiver interface and the cache area located in the data transceiver unit constitute a protocol virtual unit that meets the preset data transmission protocol. The channel control circuit controls the on and off of the data transmission channel according to the protection control instruction; wherein the protection control instruction includes a data protection instruction and a data transmission instruction. The channel control circuit generates a back pressure signal according to the data protection instruction to disconnect the data transmission channel and intercept the command signal. The channel control circuit controls the conduction of the data transmission channel according to the data transmission instruction and executes the operation corresponding to the command signal.

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