Bus arbitration control method, device, source loading system and storage medium

Abstract

The present application discloses a bus arbitration control method, device, source loading system and storage medium, the method comprising: when a first control module performs a read and write operation on a synchronous dynamic random access memory, obtaining a chip select signal and a read and write enable signal, both of which are sent by the first control module to the synchronous dynamic random access memory; confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read and write enable signal; if the operating state of the synchronous dynamic random access memory is a read and write self-refresh state, and within a preset self-refresh cycle, the chip select signal does not change to a first level, confirming that the operating state of the synchronous dynamic random access memory is an idle state; when confirming that the operating state of the synchronous dynamic random access memory is an idle state, outputting a first arbitration signal to the first control module, so that the first control module can use the bus to perform read and write operations on a second control module.

Description

Technical Field

[0001] The present application relates to the technical field of source-carrying systems, and in particular to a bus arbitration control method, device, source-carrying system and storage medium. Background Art

[0002] The source load system usually uses a microcontroller unit as the main control device, a synchronous dynamic random access memory as the external memory of the microcontroller unit, and a field programmable gate array for data acquisition, communication forwarding, etc. Among them, the synchronous dynamic random access memory and the field programmable gate array are mounted together on the flexible memory controller (Flexible Memory Controller) of the microcontroller unit. ， However, due to the read and write characteristics of the synchronous dynamic random access memory, its data is not output in real time. When the microcontroller unit reads and writes multiple data to the synchronous dynamic random access memory, it will take a self-refresh cycle after the data reading and writing is completed before the field programmable gate array can be operated.

[0003] At present, the general practice is to block and delay for a period of time after reading and writing the synchronous dynamic random access memory before operating the field programmable gate array. However, since the time when the synchronous dynamic random access memory reads and writes is not fixed in the self-refresh cycle, it is usually delayed for at least two self-refresh cycles after the synchronous dynamic random access memory reads and writes before operating the field programmable gate array, which makes the efficiency of the microcontroller unit low. Summary of the invention

[0004] The present application aims to provide a bus arbitration control method, device, source-carrying system and storage medium, which can improve the efficiency of a microcontroller unit in the source-carrying system.

[0005] In a first aspect, an embodiment of the present application provides a bus arbitration control method, which is applied to a source-load system, wherein the source-load system includes a first control module, a second control module, and a synchronous dynamic random access memory, wherein the first control module, the second control module, and the synchronous dynamic random access memory are interconnected via a bus, and the method includes:

[0006] When the first control module performs a read and write operation on the synchronous dynamic random access memory, a chip select signal and a read and write enable signal are obtained, and the chip select signal and the read and write enable signal are both sent by the first control module to the synchronous dynamic random access memory;

[0007] Confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal;

[0008] If the operation state of the synchronous dynamic random access memory is a read-write self-refresh state, and within a preset self-refresh cycle, the chip select signal does not change to a first level, confirming that the operation state of the synchronous dynamic random access memory is an idle state, and the first level is used to indicate that the chip select signal is valid;

[0009] When it is confirmed that the operating state of the synchronous dynamic random access memory is the idle state, a first arbitration signal is output to the first control module, and the first arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is the idle state, so that the first control module can use the bus to perform read and write operations on the second control module.

[0010] According to some embodiments of the present application, the step of confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal includes:

[0011] If the chip select signal is at the first level and the read / write enable signal is at the third level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the second level and the read / write enable signal is at the fourth level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the first level and the read / write enable signal is at the fourth level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the second level and the read / write enable signal is at the fourth level, it is confirmed that the operating state of the synchronous dynamic random access memory is the read / write self-refresh state; wherein,

[0012] The second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read / write enable signal is valid, and the fourth level is used to indicate that the read / write enable signal is invalid.

[0013] According to some embodiments of the present application, the step of confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal includes:

[0014] If the chip select signal continues to remain at the second level for one self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, confirming that the operating state of the synchronous dynamic random access memory is the idle state, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read-write enable signal is invalid.

[0015] According to some embodiments of the present application, after confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal, the method further includes:

[0016] If the operating state of the synchronous dynamic random access memory is not the idle state, a second arbitration signal is output to the first control module, and the second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is not the idle state, so that the first control module cannot use the bus to perform read and write operations on the second control module.

[0017] In a second aspect, an embodiment of the present application provides a bus arbitration control device, which is applied to a source-loaded system, wherein the source-loaded system includes a first control module, a second control module, and a synchronous dynamic random access memory, wherein the first control module, the second control module, and the synchronous dynamic random access memory are interconnected via a bus, and the device includes:

[0018] A first acquisition module, used for acquiring a chip select signal and a read / write enable signal when the first control module performs a read / write operation on the synchronous dynamic random access memory, wherein the chip select signal and the read / write enable signal are both sent by the first control module to the synchronous dynamic random access memory;

[0019] A first state confirmation module, used for confirming the operation state of the synchronous dynamic random access memory according to the chip selection signal and the read / write enable signal;

[0020] A second state confirmation module is used to confirm that the operation state of the synchronous dynamic random access memory is an idle state if the operation state of the synchronous dynamic random access memory is a read-write self-refresh state and the chip select signal does not change to a first level within a preset self-refresh cycle, and the first level is used to indicate that the chip select signal is valid;

[0021] The first arbitration output module is used to output a first arbitration signal to the first control module when confirming that the operating state of the synchronous dynamic random access memory is the idle state, wherein the first arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is the idle state, so that the first control module can use the bus to perform read and write operations on the second control module.

[0022] According to some embodiments of the present application, the first status confirmation module includes:

[0023] The first state confirmation submodule is used for confirming that the operating state of the synchronous dynamic random access memory is the read-write self-refresh state if the chip select signal is the first level and the read-write enable signal is the third level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the first level and the read-write enable signal is the fourth level, and then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level; wherein,

[0024] The second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read / write enable signal is valid, and the fourth level is used to indicate that the read / write enable signal is invalid.

[0025] According to some embodiments of the present application, the first status confirmation module includes:

[0026] The second state confirmation submodule is used to confirm that the operating state of the synchronous dynamic random access memory is the idle state if the chip select signal continues to remain at the second level for one self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read-write enable signal is invalid.

[0027] According to some embodiments of the present application, it further includes:

[0028] The second arbitration output module is used to output a second arbitration signal to the first control module if the operating state of the synchronous dynamic random access memory is not the idle state, and the second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is not the idle state, so that the first control module cannot use the bus to perform read and write operations on the second control module.

[0029] In a third aspect, an embodiment of the present application provides a source-carrying system, including:

[0030] a first control module;

[0031] A synchronous dynamic random access memory, wherein the synchronous dynamic random access memory is connected to the first control module via a bus;

[0032] A second control module, the second control module is connected to the first control module via the bus, and the second control module is used to execute the bus arbitration control method as described above.

[0033] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a program executable by a processor, and the program executable by the processor is used to implement the bus arbitration control method as described above when executed by the processor.

[0034] In the embodiment of the present application, the operating state of the synchronous dynamic random access memory can be accurately determined based on the chip select signal and the read / write enable signal, that is, when it is confirmed that the operating state of the synchronous dynamic random access memory is an idle state, it indicates that the read / write operation of the synchronous dynamic random access memory is completed, and then the first arbitration signal is output to the first control module, so that the first control module can use the bus to perform read / write operations on the second control module, without blocking and delaying before performing read / write operations on the second control module, thereby improving the efficiency of the first control module.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0037] Figure 1 The timing diagram of the chip select signal and the read / write enable signal when performing a data read operation for a synchronous dynamic random access memory;

[0038] Figure 2 The timing diagram of the chip select signal and the read / write enable signal when performing a data write operation for a synchronous dynamic random access memory;

[0039] Figure 3 The timing diagram of the chip select signal and the read / write enable signal when the synchronous dynamic random access memory performs read / write self-refresh operation;

[0040] Figure 4 The timing diagram of the chip select signal and the read / write enable signal when the synchronous dynamic random access memory performs an idle self-refresh operation;

[0041] Figure 5 A functional block diagram of a source carrier system provided in an embodiment of the present application;

[0042] Figure 6 A flowchart of a bus arbitration control method provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of the structure of a bus arbitration control device provided in an embodiment of the present application.

[0044] Reference numerals:

[0045] The first control module 100 , the second control module 200 , the SDRAM 300 , the bus 400 , the bus arbitration control device 500 , the first acquisition module 510 , the first state confirmation module 520 , the second state confirmation module 530 , and the first arbitration output module 540 . DETAILED DESCRIPTION

[0046] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0047] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0048] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or indicating the order of the indicated technical features.

[0049] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0050] In order to better describe the bus arbitration control method, device, source loading system and storage medium of the embodiment of the present application, the operating state of the synchronous dynamic random access memory 300 is first described here.

[0051] like Figure 1 As shown, Figure 1 The timing diagram of the chip select signal and the read / write enable signal when the first control module 100 performs a data read operation on the synchronous dynamic random access memory 300, that is, the operation state of the synchronous dynamic random access memory 300 is the data read state. Among them, the read / write enable signal is continuously maintained at a high level, and multiple clock pulses of the chip select signal are pulled down to a low level. For example, when the synchronous dynamic random access memory 300 is configured to read four data at a time, the chip select signal is pulled down to a low level of four clock pulses. Both the chip select signal and the read / write enable signal are valid at a low level.

[0052] like Figure 2 As shown, Figure 2 The timing diagram of the chip select signal and the read / write enable signal when the first control module 100 performs a data write operation on the synchronous dynamic random access memory 300, that is, the operation state of the synchronous dynamic random access memory 300 is the data write state. Among them, after the read / write enable signal and the chip select signal are synchronously pulled down by one clock pulse to a low level, the read / write enable signal is restored to a high level, and after the chip select signal is pulled up by one clock pulse to a high level, it is pulled down by one clock pulse to a low level, and then the chip select signal continues to be a high level.

[0053] like Figure 3 As shown, Figure 3 When the synchronous dynamic random access memory 300 performs a read-write self-refresh operation, the timing diagram of the chip select signal and the read-write enable signal, that is, the operation state of the synchronous dynamic random access memory 300 is the read-write self-refresh state. Among them, after the read-write enable signal and the chip select signal are synchronously pulled down by one clock pulse to a low level, the read-write enable signal is restored to a high level, and after the chip select signal is pulled up by one clock pulse to a high level, it is pulled down by one clock pulse to a low level, and then it is continuously maintained at a high level.

[0054] like Figure 4 As shown, Figure 4 The timing diagram of the chip select signal and the read / write enable signal when the synchronous dynamic random access memory 300 performs an idle self-refresh operation, that is, the operation state of the synchronous dynamic random access memory 300 is an idle self-refresh state. Among them, the read / write enable signal is always kept at a high level, and the chip select signal is pulled down to a low level for one clock pulse and then restored to a high level.

[0055] The SDRAM 300 performs a self-refresh operation in each self-refresh cycle. When the SDRAM 300 reads and writes data, the read-write self-refresh operation is performed in the corresponding self-refresh cycle. When the SDRAM 300 is idle, the idle self-refresh operation is performed in the corresponding self-refresh cycle.

[0056] Since the first control module 100, the second control module 200 and the SDRAM 300 are all mounted on the FMC bus of the first control module 100, if the first control module 100 performs read and write operations on the SDRAM 300 through the FMC bus, and also performs operations on the second control module 200 through the FMC bus, the read and write operations of the SDRAM 300 will be interfered. Therefore, after the read and write operations are completed, a self-refresh cycle must pass before the second control module 200 can be operated. Since the time when the read and write operations of the SDRAM 300 are completed is not fixed in the self-refresh cycle, it is usually delayed by at least two self-refresh cycles after the read and write operations of the SDRAM 300 are completed before the second control module 200 is operated, which makes the efficiency of the first control module 100 low.

[0057] In order to solve the above problems, the embodiments of the present application provide a bus arbitration control method, device, source loading system and storage medium.

[0058] Refer to the following Figures 5 to 7 A bus arbitration control method, device, source loading system and storage medium according to an embodiment of the present application are described.

[0059] The present application embodiment provides a bus arbitration control method, which is applied to a source-load system, such as Figure 5 As shown, the source-carrying system includes a first control module 100, a second control module 200 and a synchronous dynamic random access memory 300, and the first control module 100, the second control module 200 and the synchronous dynamic random access memory 300 are connected to each other via a bus 400. The bus arbitration control method can be executed by the second control module 200, such as Figure 6 As shown, the bus arbitration control method includes but is not limited to step S100, step S200, step S300 and step S400.

[0060] Step S100: When the first control module 100 performs a read / write operation on the synchronous dynamic random access memory 300, a chip select signal and a read / write enable signal are obtained, and both the chip select signal and the read / write enable signal are sent by the first control module 100 to the synchronous dynamic random access memory 300;

[0061] In this step, the chip select signal and the read / write enable signal are sent from the first control module 100 to the synchronous dynamic random access memory 300, and the chip select operation is performed on the synchronous dynamic random access memory 300 through the chip select signal, and the read / write enable operation is performed on the synchronous dynamic random access memory 300 through the read / write enable signal. Both the chip select signal and the read / write enable signal are effective at low levels. When the first control module 100 performs read / write operations on the synchronous dynamic random access memory 300, the second control module 200 obtains the chip select signal and the read / write enable signal, and the operating state of the synchronous dynamic random access memory 300 can be determined by the levels of the clock pulses of the chip select signal and the read / write enable signal.

[0062] The first control module 100 may be a micro control unit, a digital signal processor, etc. The second control module 200 may be a field programmable gate array, a complex programmable logic device, etc. The bus 400 may be an FMC bus, etc.

[0063] Step S200: confirming the operation status of the synchronous dynamic random access memory 300 according to the chip selection signal and the read / write enable signal;

[0064] In this step, the second control module 200 can determine the operating state of the SDRAM 300 according to the levels of the clock pulses of the chip selection signal and the read / write enable signal.

[0065] Step S300: if the operation state of the synchronous dynamic random access memory 300 is the read-write self-refresh state, and within a preset self-refresh cycle, the chip select signal does not change to the first level, it is confirmed that the operation state of the synchronous dynamic random access memory 300 is the idle state, and the first level is used to indicate that the chip select signal is valid;

[0066] In this step, the second control module 200 performs a timing operation when confirming that the operation state of the synchronous dynamic random access memory 300 is the read-write self-refresh state according to the chip select signal and the read-write enable signal. If the chip select signal does not change to the first level within a preset self-refresh cycle, it is confirmed that the read-write operation of the synchronous dynamic random access memory 300 is completed, and the operation state of the synchronous dynamic random access memory 300 is the idle state. Since the chip select signal is valid at a low level, the first level is a low level.

[0067] Step S400: When confirming that the operating state of the synchronous dynamic random access memory 300 is an idle state, output a first arbitration signal to the first control module 100, and the first arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory 300 is an idle state, so that the first control module 100 can use the bus 400 to perform read and write operations on the second control module 200.

[0068] In this step, when it is confirmed that the operation state of the synchronous dynamic random access memory 300 is the idle state, the second control module 200 outputs the first arbitration signal to the first control module 100. When the first control module 100 receives the first arbitration signal, it confirms that the read and write operations of the synchronous dynamic random access memory 300 are completed, and the bus 400 can be used to perform read and write operations on the second control module 200.

[0069] In this embodiment, the second control module 200 can accurately determine the operating state of the synchronous dynamic random access memory 300 according to the chip select signal and the read / write enable signal, that is, when it is confirmed that the operating state of the synchronous dynamic random access memory 300 is an idle state, it indicates that the read / write operation of the synchronous dynamic random access memory 300 is completed, and then outputs the first arbitration signal to the first control module 100, so that the first control module 100 can use the bus 400 to perform read / write operations on the second control module 200, without blocking and delaying the read / write operations on the second control module 200, thereby improving the efficiency of the first control module 100.

[0070] In one embodiment of the present application, the step S200 of “confirming the operating state of the synchronous dynamic random access memory 300 according to the chip select signal and the read / write enable signal” is further explained, and the step S200 includes but is not limited to the step S210.

[0071] Step S210: If the chip select signal is at the first level and the read / write enable signal is at the third level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the second level and the read / write enable signal is at the fourth level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the first level and the read / write enable signal is at the fourth level, then at the next clock pulse of the chip select signal and the read / write enable signal, the chip select signal is at the second level and the read / write enable signal is at the fourth level, confirming that the operating state of the synchronous dynamic random access memory 300 is the read / write self-refresh state; wherein,

[0072] The second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read / write enable signal is valid, and the fourth level is used to indicate that the read / write enable signal is invalid.

[0073] In this embodiment, if four consecutive clock pulses of the chip select signal are respectively the first level, the second level, the first level, and the second level, and at the same time, four consecutive clock pulses of the read-write enable signal are respectively the third level, the fourth level, the fourth level, and the fourth level, the second control module 200 confirms that the operating state of the synchronous dynamic random access memory 300 is the read-write self-refresh state.

[0074] Among them, the second level is a high level, the third level is a low level, and the fourth level is a high level.

[0075] In one embodiment of the present application, the step S200 of “confirming the operating state of the synchronous dynamic random access memory 300 according to the chip select signal and the read / write enable signal” is further explained, and the step S200 includes but is not limited to the step S220.

[0076] Step S220: If the chip select signal continues to remain at the second level for a self-refresh cycle, the chip select signal changes to the first level and the read / write enable signal is at the fourth level, confirming that the operating state of the synchronous dynamic random access memory 300 is the idle state, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read / write enable signal is invalid.

[0077] In this embodiment, if the chip select signal continues to remain at the second level for a self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, the second control module 200 confirms that the operating state of the synchronous dynamic random access memory 300 is an idle self-refresh state, indicating that the read and write operations of the synchronous dynamic random access memory 300 are completed and the operating state of the synchronous dynamic random access memory 300 is an idle state.

[0078] In one embodiment of the present application, after "confirming the operating state of the synchronous dynamic random access memory 300 according to the chip select signal and the read / write enable signal" in step S200, it also includes but is not limited to step S500.

[0079] Step S500: If the operating state of the synchronous dynamic random access memory 300 is not the idle state, output a second arbitration signal to the first control module 100, and the second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory 300 is not the idle state, so that the first control module 100 cannot use the bus 400 to perform read and write operations on the second control module 200.

[0080] In this embodiment, when it is confirmed that the operating state of the synchronous dynamic random access memory 300 is not an idle state, the second control module 200 outputs a second arbitration signal to the first control module 100, and the first control module 100 confirms that the synchronous dynamic random access memory 300 is performing read and write operations, so that the first control module 100 cannot use the bus 400 to perform read and write operations on the second control module 200.

[0081] The first arbitration signal and the second arbitration signal may be output through the IO interface of the second control module 200 , wherein the first arbitration signal is a low level signal and the second arbitration signal is a high level signal.

[0082] In addition, the embodiment of the present application further provides a bus arbitration control device 500, which is applied to a source-carrying system. The source-carrying system includes a first control module 100, a second control module 200 and a synchronous dynamic random access memory 300. The first control module 100, the second control module 200 and the synchronous dynamic random access memory 300 are interconnected via a bus 400. Figure 7 As shown, the device comprises:

[0083] The first acquisition module 510 is used to acquire a chip selection signal and a read / write enable signal when the first control module 100 performs a read / write operation on the synchronous dynamic random access memory 300. The chip selection signal and the read / write enable signal are both sent by the first control module 100 to the synchronous dynamic random access memory 300.

[0084] A first state confirmation module 520, used to confirm the operation state of the synchronous dynamic random access memory 300 according to the chip selection signal and the read / write enable signal;

[0085] The second state confirmation module 530 is used to confirm that the operation state of the synchronous dynamic random access memory 300 is an idle state if the operation state of the synchronous dynamic random access memory 300 is a read-write self-refresh state and the chip select signal does not change to a first level within a preset self-refresh cycle, and the first level is used to indicate that the chip select signal is valid;

[0086] The first arbitration output module 540 is used to output a first arbitration signal to the first control module 100 when it is confirmed that the operating state of the synchronous dynamic random access memory 300 is an idle state. The first arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory 300 is an idle state, so that the first control module 100 can use the bus 400 to perform read and write operations on the second control module 200.

[0087] In one embodiment of the present application, the first status confirmation module 520 includes:

[0088] The first state confirmation submodule is used for confirming that the operating state of the synchronous dynamic random access memory 300 is the read-write self-refresh state if the chip select signal is at the first level and the read-write enable signal is at the third level, at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal changes to the second level and the read-write enable signal changes to the fourth level, at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal changes to the first level and the read-write enable signal changes to the fourth level, at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal changes to the second level and the read-write enable signal changes to the fourth level; wherein,

[0089] The second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read / write enable signal is valid, and the fourth level is used to indicate that the read / write enable signal is invalid.

[0090] In one embodiment of the present application, the first status confirmation module 520 includes:

[0091] The second state confirmation submodule is used to confirm that the operating state of the synchronous dynamic random access memory 300 is an idle state if the chip select signal continues to remain at the second level for a self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read-write enable signal is invalid.

[0092] An embodiment of the present application further includes:

[0093] The second arbitration output module is used to output a second arbitration signal to the first control module 100 if the operating state of the synchronous dynamic random access memory 300 is not an idle state. The second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory 300 is not an idle state, so that the first control module 100 cannot use the bus 400 to perform read and write operations on the second control module 200.

[0094] The bus arbitration control device 500 provided in the embodiment of the present application can implement each process implemented in the above method embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described again here.

[0095] In addition, the embodiment of the present application further provides a source-carrying system, including:

[0096] A first control module 100;

[0097] A synchronous dynamic random access memory 300, wherein the synchronous dynamic random access memory 300 is connected to the first control module 100 via a bus 400;

[0098] The second control module 200 is connected to the first control module 100 via the bus 400 . The second control module 200 is used to execute the bus arbitration control method as described above.

[0099] The source-carrying system provided in the embodiment of the present application can implement each process implemented in the above method embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described again here.

[0100] In addition, an embodiment of the present application further provides a computer-readable storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to implement the bus arbitration control method as described above.

[0101] The computer-readable storage medium provided in the embodiment of the present application can implement each process implemented in the above method embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0102] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0103] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A bus arbitration control method, characterized in that: Applied to a source-carrying system, the source-carrying system comprises a first control module, a second control module and a synchronous dynamic random access memory, the first control module, the second control module and the synchronous dynamic random access memory are interconnected via a bus, and the method comprises: When the first control module performs a read and write operation on the synchronous dynamic random access memory, a chip select signal and a read and write enable signal are obtained, and the chip select signal and the read and write enable signal are both sent by the first control module to the synchronous dynamic random access memory; Confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal; If the operation state of the synchronous dynamic random access memory is the read-write self-refresh state, and within a preset self-refresh cycle, the chip select signal does not change to the first level, it is confirmed that the operation state of the synchronous dynamic random access memory is the idle state, and the first level is used to indicate that the chip select signal is valid; wherein, if the chip select signal is the first level and the read-write enable signal is the third level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the first level and the read-write enable signal is the fourth level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level, it is confirmed that the operation state of the synchronous dynamic random access memory is the read-write self-refresh state; the second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read-write enable signal is valid, and the fourth level is used to indicate that the read-write enable signal is invalid; When it is confirmed that the operating state of the synchronous dynamic random access memory is the idle state, a first arbitration signal is output to the first control module, and the first arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is the idle state, so that the first control module can use the bus to perform read and write operations on the second control module.

2. The bus arbitration control method according to claim 1, characterized in that: The step of confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal comprises: If the chip select signal continues to remain at the second level for one self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, confirming that the operating state of the synchronous dynamic random access memory is the idle state, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read-write enable signal is invalid.

3. The bus arbitration control method according to claim 1, characterized in that: After confirming the operating state of the synchronous dynamic random access memory according to the chip select signal and the read / write enable signal, the method further includes: If the operating state of the synchronous dynamic random access memory is not the idle state, a second arbitration signal is output to the first control module, and the second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is not the idle state, so that the first control module cannot use the bus to perform read and write operations on the second control module.

4. A bus arbitration control device, characterized in that: Applied to a source-carrying system, the source-carrying system comprises a first control module, a second control module and a synchronous dynamic random access memory, the first control module, the second control module and the synchronous dynamic random access memory are interconnected via a bus, and the device comprises: A first acquisition module, used for acquiring a chip select signal and a read / write enable signal when the first control module performs a read / write operation on the synchronous dynamic random access memory, wherein the chip select signal and the read / write enable signal are both sent by the first control module to the synchronous dynamic random access memory; A first state confirmation module, used for confirming the operation state of the synchronous dynamic random access memory according to the chip selection signal and the read / write enable signal; A second state confirmation module is used to confirm that the operation state of the synchronous dynamic random access memory is an idle state if the operation state of the synchronous dynamic random access memory is a read-write self-refresh state and the chip select signal does not change to a first level within a preset self-refresh cycle, and the first level is used to indicate that the chip select signal is valid; a first arbitration output module, configured to output a first arbitration signal to the first control module when confirming that the operation state of the synchronous dynamic random access memory is the idle state, wherein the first arbitration signal is used to indicate that the operation state of the synchronous dynamic random access memory is the idle state, so that the first control module can use the bus to perform read and write operations on the second control module; The first status confirmation module includes: The first state confirmation submodule is used for confirming that the operating state of the synchronous dynamic random access memory is the read-write self-refresh state if the chip select signal is the first level and the read-write enable signal is the third level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level, then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the first level and the read-write enable signal is the fourth level, and then at the next clock pulse of the chip select signal and the read-write enable signal, the chip select signal is the second level and the read-write enable signal is the fourth level; wherein, The second level is used to indicate that the chip select signal is invalid, the third level is used to indicate that the read / write enable signal is valid, and the fourth level is used to indicate that the read / write enable signal is invalid.

5. The bus arbitration control device according to claim 4, characterized in that: The first status confirmation module also includes: The second state confirmation submodule is used to confirm that the operating state of the synchronous dynamic random access memory is the idle state if the chip select signal continues to remain at the second level for one self-refresh cycle, the chip select signal changes to the first level and the read-write enable signal is at the fourth level, the second level is used to indicate that the chip select signal is invalid, and the fourth level is used to indicate that the read-write enable signal is invalid.

6. The bus arbitration control device according to claim 4, characterized in that: Also includes: The second arbitration output module is used to output a second arbitration signal to the first control module if the operating state of the synchronous dynamic random access memory is not the idle state, and the second arbitration signal is used to indicate that the operating state of the synchronous dynamic random access memory is not the idle state, so that the first control module cannot use the bus to perform read and write operations on the second control module.

7. A source-carrying system, characterized in that: include: a first control module; A synchronous dynamic random access memory, wherein the synchronous dynamic random access memory is connected to the first control module via a bus; A second control module, wherein the second control module is connected to the first control module via the bus, and the second control module is used to execute the bus arbitration control method according to any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that: A processor-executable program is stored therein, and when the processor-executable program is executed by the processor, it is used to implement the bus arbitration control method as described in any one of claims 1 to 3.

Images