A method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip
By numbering the IP of the automotive electronic chip on the bus matrix and generating verification data using the FIFO queue, the problem of missing verification codes caused by inconsistent data bit widths is solved, and the chip's security level and the correctness of data transmission are improved.
Patent Information
- Application Number
- CN202411415078.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2044-10-11
AI Technical Summary
In the prior art, in automotive electronic chips, the data bit widths of each master-slave endpoint on the bus are inconsistent, resulting in inconsistent verification data widths, resulting in a lack of verification codes when data transmission is converted from IP through data width to the bus matrix, which reduces security. score.
By numbering the IP of the main endpoint on the bus matrix and using the FIFO queue to generate verification data during data transmission, we ensure that the verification code is generated during IP end-to-end data transmission, and the correctness of data transmission is protected.
It realizes effective verification code generation in IP end-to-end data transmission, improves the chip's security level, and ensures the correctness and security of data transmission.
Smart Images
Figure CN118939470B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip data transmission detection, and in particular to a method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip. Background Art
[0002] Automotive electronic chips have high requirements for security levels. The data sent from the master endpoint to the slave endpoint and the data read back from the slave endpoint on the bus must be added with a check bit (generally transmitted through the bus matrix), which can detect whether there are errors in the data from end to end. Errors in 1-bit data can be corrected, and errors in data greater than 1 bit can be reported. However, the check bit is different for different data widths. For example, the check bit for 64-bit wide data is 8 bits, the check bit for 32-bit wide data is 7 bits, and the check bit for 128-bit wide data is 9 bits. Since the data bit widths of each master and slave endpoint on the bus may not be consistent, the width of the check data is also inconsistent.
[0003] The existing solution is to first convert the data of the master endpoint and the slave endpoint to the same width through the width transfer IP. Then generate a check code for the data of the same width and transmit it. The block diagram can be found in the attached manual. Figure 1 The data width of all master and slave endpoints on the bus matrix is 64 bits. However, there is a data width conversion from the actual IP to the bus matrix. For example, the data width of ENET is 32 bits, and the data width must be converted to 64 bits before it reaches the bus matrix. This implementation method brings a problem that there is no checksum during the data width conversion from IP to the bus matrix, which reduces the security score.
[0004] To this end, we propose an IP end-to-end data transmission detection and correction method in a system-on-chip to solve the above problems. Summary of the invention
[0005] The main purpose of the present invention is to provide an IP end-to-end data transmission detection and correction method in a system-on-chip chip, which utilizes the numbering of the IPs of the master endpoints on the bus matrix and the generation of check bits when IP data is transmitted with different widths, thereby generating check codes from the data at the IP end to protect the correctness of data transmission, and can effectively solve the problems in the background technology.
[0006] To achieve the above object, the present invention provides a method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip, the detection and correction method comprising:
[0007] The IPs of the master endpoints and slave endpoints on the bus matrix in the system-on-chip chip are numbered, and the IP numbering signal can be transmitted on the port of the bus matrix;
[0008] When the IP on the target master endpoint sends data to the IP on the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined, thereby generating verification data and putting it into the FIFO of the verification data from the target master endpoint to the target slave endpoint;
[0009] Since the data width of the IP connected to the master and slave endpoints on the bus matrix in the chip and the maximum amount of data sent and received at one time are fixed during design, the data width and depth of the check data FIFO from the master endpoint to the slave endpoint and from the slave endpoint to the master endpoint can be calculated to evaluate the chip area and power consumption.
[0010] Based on the above technical solution, the present invention can also be improved as follows.
[0011] Furthermore, the IP numbering of the master endpoint and the slave endpoint on the bus matrix in the system-on-chip chip includes:
[0012] The IPs that will be connected to the master endpoints on the bus matrix are numbered 0-N; correspondingly, the IPs that will be connected to the slave endpoints on the bus matrix are also numbered 0-N.
[0013] Furthermore, the IP number signal can be transmitted on the port of the bus matrix, including:
[0014] The bus of the system on chip will carry some redundant signals, which can be used to transmit the number of the master endpoint IP.
[0015] Further, when the IP on the target master endpoint sends data to the IP of the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined, thereby generating verification data, and putting it into the FIFO of the target master endpoint to the target slave endpoint verification data, and then further comprising:
[0016] After the target slave endpoint receives the data from the master endpoint on the bus matrix, it will determine the IP number of the master endpoint based on the redundant signal, and then determine which master endpoint sent the data;
[0017] When the target slave endpoint recognizes that the data is sent by the target master endpoint, it reads the verification data from the FIFO of the target slave endpoint verification data from the target master endpoint while receiving the data;
[0018] The target slave endpoint obtains the status information of the received data by performing operations on the check data and the received data.
[0019] Further, when the IP on the target master endpoint sends data to the IP on the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target slave endpoint data are determined to generate verification data, and the verification data is also generated.
[0020] When the target master endpoint wants to read the data on the target slave endpoint, before the slave endpoint returns the data, it first splits the data of the corresponding width of the target slave endpoint into the data of the corresponding width of the target master endpoint to generate verification data, and then puts it into the verification data FIFO from the target slave endpoint to the target master endpoint;
[0021] However, after the target master endpoint receives the data returned by the target slave endpoint, it simultaneously takes out the corresponding verification data from the verification data FIFO from the target slave endpoint to the target master endpoint;
[0022] The target master endpoint calculates the status of the received data by performing operations on the check data and the received data.
[0023] The beneficial effects of the present invention are:
[0024] The present invention utilizes the numbering of the IPs of the main endpoints on the bus matrix and the FIFO etc. to realize the generation of check bits when IP data of different widths are transmitted, thereby realizing the generation of check codes from the data at the IP end to protect the correctness of data transmission, realizing true IP data protection from endpoint to endpoint, and improving the security level of the chip.
[0025] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. The specific implementation of the present invention is given in detail by the following embodiments and their accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0027] Figure 1 It is a schematic diagram of the prior art structure.
[0028] Figure 2 The present invention is a schematic diagram of the IP numbering of the master endpoint and the slave endpoint on the bus matrix of the IP end-to-end data transmission detection and correction method in the system-on-chip chip of the present invention.
[0029] Figure 3 It is a schematic diagram of data transmission between a master endpoint and a slave endpoint of the IP end-to-end data transmission detection and correction method in the system-on-chip chip of the present invention. DETAILED DESCRIPTION
[0030] The following is combined with Figure 1-Figure 3 The principles and features of the present invention are described, and the examples are only used to explain the present invention and are not used to limit the scope of the present invention. In the following paragraphs, the present invention is described in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0031] It should be noted that when a component is referred to as being "fixed to" another component, it may be directly on the other component or there may also be a component centered. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may also be a component centered. When a component is considered to be "set on" another component, it may be directly set on the other component or there may also be a component centered. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0033] Embodiment 1
[0034] The present invention provides a method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip, the method comprising:
[0035] The IPs of the master endpoints and slave endpoints on the bus matrix in the system-on-chip chip are numbered, and the IP numbering signal can be transmitted on the port of the bus matrix;
[0036] When the IP on the target master endpoint sends data to the IP on the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined to generate verification data, which is placed in the FIFO (first-in, first-out queue) of the verification data from the target master endpoint to the target slave endpoint;
[0037] Since the data width of the IP connected to the master and slave endpoints on the bus matrix in the chip and the maximum amount of data sent and received at one time are fixed during design, the data width and depth of the verification data FIFO (first-in, first-out queue) from the master endpoint to the slave endpoint and from the endpoint to the master endpoint can be calculated to evaluate the chip area and power consumption.
[0038] Embodiment 2
[0039] Based on the first embodiment, the following improvements are made:
[0040] In this embodiment, the step of numbering the IP addresses of the master endpoints and the slave endpoints on the bus matrix in the system-on-chip chip includes:
[0041] The IPs that will be connected to the master endpoints on the bus matrix are numbered 0-N; correspondingly, the IPs that will be connected to the slave endpoints on the bus matrix are also numbered 0-N.
[0042] In this embodiment, the IP number signal can be transmitted on the port of the bus matrix, including:
[0043] The bus of the system on chip will carry some redundant signals, which can be used to transmit the number of the master endpoint IP. For example, the AMBA bus can transmit some user signals, which can be used to transmit the number of the master endpoint IP.
[0044] In this embodiment, when the IP on the target master endpoint sends data to the IP of the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined, thereby generating verification data, and putting it into the FIFO (first in first out queue) of the verification data from the target master endpoint to the target slave endpoint, and then further comprising:
[0045] After the target slave endpoint receives the data from the master endpoint on the bus matrix, it will determine the IP number of the master endpoint based on the redundant signal, and then determine which master endpoint sent the data;
[0046] When the target slave endpoint recognizes that the data is sent by the target master endpoint, it reads the verification data from the FIFO (first-in, first-out queue) of the target master endpoint to the target slave endpoint verification data at the same time as receiving the data;
[0047] The target slave endpoint obtains the status information of the received data by performing operations on the check data and the received data.
[0048] In this embodiment, when the IP on the target master endpoint sends data to the IP on the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target slave endpoint data are determined to generate verification data, and the verification data is also generated.
[0049] When the target master endpoint wants to read the data on the target slave endpoint, before the slave endpoint returns the data, it first splits the data of the corresponding width of the target slave endpoint into the data of the corresponding width of the target master endpoint to generate verification data, and then puts it into the verification data FIFO (first in first out queue) from the target slave endpoint to the target master endpoint;
[0050] However, after the target master endpoint receives the data returned by the target slave endpoint, it simultaneously takes out the corresponding verification data from the verification data FIFO (first-in-first-out queue) from the target slave endpoint to the target master endpoint;
[0051] The target master endpoint calculates the status of the received data by performing operations on the check data and the received data.
[0052] For example, Figure 2 For example, the IPs connected to the master endpoints on the bus matrix are numbered 0 to 7. The IPs connected to the slave endpoints on the bus matrix are numbered 0 to 7.
[0053] like Figure 3 As shown in the figure, when master0 wants to transfer data to slave0, it needs to combine two 32-bit data into 64-bit data to generate verification data, and then put it into the FIFO (first in first out queue) of master0 to slave0 verification data.
[0054] When slave0 receives data, it first determines which master sent it based on redundant signals, such as the user signal in the AMBA bus protocol.
[0055] If it is sent by master0, then when the data is received, it will read the verification data from the FIFO (first in first out queue) of master0 to slave0 verification data. The status information of the received data is obtained by calculating the verification data and the received data.
[0056] If master0 wants to read data from slave0, when slave returns data, it first splits the 64-bit data into two 32-bit data and generates verification data for each. It is put into the verification data FIFO (first-in, first-out queue) from slave0 to master0. When master0 receives the data returned by slave0, it simultaneously takes out the corresponding verification data from the verification data FIFO (first-in, first-out queue) from slave0 to master0. The verification data and the received data are calculated to obtain the status of the received data. Similarly, from master0 to other slave ends, and from master1 to master7 to access other slave ends.
[0057] Among them, slave is the slave endpoint on the bus matrix, and master is the master endpoint on the bus matrix.
[0058] The present invention utilizes the numbering of the IPs of the main endpoints on the bus matrix and the FIFO etc. to realize the generation of check bits when IP data of different widths are transmitted, thereby realizing the generation of check codes from the data at the IP end to protect the correctness of data transmission, realizing true IP data protection from endpoint to endpoint, and improving the security level of the chip.
[0059] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any ordinary technician in the industry can smoothly implement the present invention as shown in the drawings and described above. However, any equivalent changes, modifications and evolutions made by technicians familiar with the profession without departing from the scope of the technical solution of the present invention using the technical content disclosed above are all equivalent embodiments of the present invention. At the same time, any equivalent changes, modifications and evolutions made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the technical solution of the present invention.
Claims
1. A method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip, characterized in that: The detection and correction methods include: Number the IPs of the master endpoint and slave endpoint on the bus matrix in the system-on-chip chip. The bus matrix will carry some redundant signals, which are used to transmit the number of the master endpoint IP; When the IP on the target master endpoint sends data to the IP on the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined, thereby generating verification data and putting it into the FIFO of the verification data from the target master endpoint to the target slave endpoint; After the target slave endpoint receives the data from the master endpoint on the bus matrix, it will determine the IP number of the master endpoint based on the redundant signal, and then determine which master endpoint sent the data; When the target slave endpoint recognizes that the data is sent by the target master endpoint, it reads the verification data from the FIFO of the target slave endpoint verification data from the target master endpoint while receiving the data; The target slave endpoint processes the check data and the received data to obtain the status information of the received data; The data width of the IP connected to the master and slave endpoints on the bus matrix in the chip and the maximum amount of data sent and received at one time are fixed during design. The data width and depth of the check data FIFO from the master endpoint to the slave endpoint and from the endpoint to the master endpoint can be calculated.
2. The method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip according to claim 1, characterized in that: The method of numbering the IPs of the master endpoints and the slave endpoints on the bus matrix in the system-on-chip chip includes: The IPs that will be connected to the master endpoints on the bus matrix are numbered 0-N; correspondingly, the IPs that will be connected to the slave endpoints on the bus matrix are also numbered 0-N.
3. The method for detecting and correcting IP end-to-end data transmission in a system-on-chip chip according to claim 1, characterized in that: When the IP on the target master endpoint transmits data to the IP of the target slave endpoint through the bus matrix, the width of the target slave endpoint data and the data width of the target master endpoint itself are determined to generate verification data, and the method further includes: When the target master endpoint wants to read the data on the target slave endpoint, before the slave endpoint returns the data, it first splits the data of the corresponding width of the target slave endpoint into the data of the corresponding width of the target master endpoint to generate verification data, and then puts it into the verification data FIFO from the target slave endpoint to the target master endpoint; However, after the target master endpoint receives the data returned by the target slave endpoint, it simultaneously takes out the corresponding verification data from the verification data FIFO from the target slave endpoint to the target master endpoint; The target master endpoint calculates the status of the received data by performing operations on the check data and the received data.