Reset type charge sensitive amplifier circuit, data signal amplification and reset method

Abstract

The present invention provides a reset type charge sensitive amplifier circuit, a data signal amplification and reset method, which can be applied to the field of amplifier circuit technology. The reset type charge sensitive amplifier circuit includes: a signal input buffer module, a signal output amplifier module and a reset pulse signal generating module; the signal input buffer module is connected to the signal output amplifier module, the first end of the signal input buffer unit is electrically connected to the semiconductor radiation detector, and the second end of the signal input buffer unit is electrically connected to the voltage bias unit; the signal output amplifier module is connected to the reset pulse signal generating module; the reset pulse signal generating module includes a voltage comparison unit, a reset pulse width modulation unit and a reset pulse amplifier unit, the first end of the voltage comparison unit is electrically connected to the signal output amplifier module, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplifier unit.

Description

Technical Field

[0001] The present invention relates to the technical field of amplifier circuits, and more specifically to a reset-type charge-sensitive amplifier circuit and a data signal amplification and reset method. Background Art

[0002] Radiation detector technology has important application prospects in the frontier direction of disciplines and industrial applications. In the radiation detector system, the amplifier circuit is an important circuit component. The amplifier circuit in the prior art usually uses charge-sensitive, voltage-sensitive or current-sensitive amplifiers for circuit design.

[0003] In the process of realizing the above-mentioned inventive concept, the inventors discovered that in the related technology, since the junction field effect transistors made of existing silicon materials cannot meet the requirements of normal operation in a high temperature and high radiation environment, technical problems such as failure of the amplifier circuit and radiation detector system where the silicon-based junction field effect transistors are located occur. Summary of the invention

[0004] In view of the above problems, the present invention provides a reset-type charge-sensitive amplifier circuit and a method for amplifying and resetting a data signal.

[0005] According to a first aspect of the present invention, a reset-type charge-sensitive amplifier circuit is provided, comprising: a signal input buffer module, a signal output amplifier module and a reset pulse signal generating module; wherein the signal input buffer module is electrically connected to the signal output amplifier module, the signal input buffer module comprises a signal input buffer unit and a voltage bias unit, the first end of the signal input buffer unit is used to be electrically connected to the semiconductor radiation detector, the second end of the signal input buffer unit is electrically connected to the voltage bias unit, and is used to read a first output signal output by the semiconductor radiation detector, amplify the first output signal and output a first amplified signal to the signal output amplifier module, the first amplified signal represents a signal obtained after amplifying the first output signal; the signal output amplifier module is electrically connected to the reset pulse signal generating ... The generating module is electrically connected and used to amplify and high-pass filter the first amplified signal to obtain and output the target signal; the reset pulse signal generating module includes a voltage comparison unit, a reset pulse width modulation unit and a reset pulse amplifying unit, the first end of the voltage comparison unit is electrically connected to the signal output amplification module, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplifying unit, and the voltage comparison unit outputs a first control signal of a high level to the reset pulse width modulation unit based on the first amplified signal, and the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplifying unit based on the high-level first control signal, so as to reset the reset charge sensitive amplifier circuit.

[0006] According to an embodiment of the present invention, the signal input buffer unit includes a silicon carbide-based junction field effect transistor and a diode; wherein the first end of the signal input buffer unit is electrically connected to the semiconductor radiation detector, and the second end of the signal input buffer unit is electrically connected to the voltage bias unit, including: the gate of the silicon carbide-based junction field effect transistor is electrically connected to the first end of the diode and the semiconductor radiation detector, the drain of the silicon carbide-based junction field effect transistor is electrically connected to the voltage bias unit, and the source of the silicon carbide-based junction field effect transistor is grounded, which is used to amplify the first output signal to obtain a first amplified signal, and output the first amplified signal to the signal output amplification module; the first end of the diode is electrically connected to the gate of the silicon carbide-based junction field effect transistor and the semiconductor radiation detector, and the second end of the diode is electrically connected to the second end of the reset pulse amplification unit, which is used to make the first end of the diode a high-level first output signal when the reset pulse signal at the second end of the diode is a high pulse signal.

[0007] According to an embodiment of the present invention, the voltage bias unit includes a first power supply and a first bias resistor, and the first power supply is a power supply with a constant voltage; wherein the first power supply is used to provide a constant voltage to the first bias resistor; the first end of the first bias resistor is electrically connected to the first power supply, and the second end of the first bias resistor is electrically connected to the drain of the silicon carbide-based junction field effect transistor, and is used to adjust the bias current of the drain of the silicon carbide-based junction field effect transistor, and provide a stable static operating point to the silicon carbide-based junction field effect transistor.

[0008] According to an embodiment of the present invention, the signal output amplification module includes a charge-sensitive amplification unit and a high-pass filtering unit; wherein the signal output amplification module is electrically connected to the reset pulse signal generating module, and includes: a first end of the charge-sensitive amplification unit is electrically connected to the drain of the silicon carbide-based junction field effect transistor, and a second end of the charge-sensitive amplification unit is electrically connected to the high-pass filtering unit, for amplifying the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the high-pass filtering unit and the voltage comparison unit; the high-pass filtering unit is electrically connected to the charge-sensitive amplification unit, for performing high-pass filtering on the second amplified signal, and amplifying the signal after the high-pass filtering to obtain and output the target signal.

[0009] According to an embodiment of the present invention, the high-pass filtering unit includes a high-pass filtering sub-unit and a first operational amplifier; the high-pass filtering unit is electrically connected to the charge-sensitive amplifier unit, including: the first end of the high-pass filtering sub-unit is electrically connected to the charge-sensitive amplifier unit, the second end of the high-pass filtering sub-unit is electrically connected to the input end of the first operational amplifier, and is used to perform high-pass filtering on the second amplified signal to obtain a filtered signal; the input end of the first operational amplifier is electrically connected to the second end of the high-pass filtering sub-unit, and the output end of the first operational amplifier outputs a target signal, which is used to amplify the filtered signal to obtain and output the target signal to an external circuit.

[0010] According to an embodiment of the present invention, the voltage comparison unit includes a first bias subunit, a second bias subunit and a voltage comparator; wherein the first end of the voltage comparison unit is electrically connected to the signal output amplification module, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: the first end of the first bias subunit is electrically connected to the second end of the charge sensitive amplification unit, the second end of the first bias subunit is grounded, and the third end of the first bias subunit is electrically connected to the same-direction input end of the voltage comparator, which is used to divide the second amplified signal output by the charge sensitive amplification unit and provide the voltage comparator with an input voltage to be compared; the first end of the second bias subunit is electrically connected to the second end of the charge sensitive amplification unit, and ... second bias subunit is electrically connected to the second end of the reset pulse width modulation unit. One end is electrically connected to the second power supply, the second end of the second bias subunit is grounded, and the third end of the second bias subunit is electrically connected to the reverse input end of the voltage comparator, so as to provide a reference voltage to the reverse input end of the voltage comparator; the same-direction input end of the voltage comparator is electrically connected to the third end of the first bias subunit, the reverse input end of the voltage comparator is electrically connected to the third end of the second bias subunit, and the output end of the voltage comparator outputs a first control signal, which is used to output a high-level first control signal to the reset pulse width modulation unit when the voltage at the same-direction input end is greater than the voltage at the reverse input end, and output a low-level first control signal to the reset pulse width modulation unit when the voltage at the same-direction input end is less than the voltage at the reverse input end.

[0011] According to an embodiment of the present invention, the reset pulse width modulation unit includes a rising edge D-type trigger, a timing resistor and a timing capacitor; wherein the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: the clock port of the rising edge D-type trigger is electrically connected to the output end of the voltage comparator, the data input port of the rising edge D-type trigger and the set port of the rising edge D-type trigger are electrically connected to the second power supply, used to maintain the high level input state of the data input port and the set port of the rising edge D-type trigger, the reset port of the rising edge D-type trigger is electrically connected to the first end of the timing capacitor, the positive output end of the rising edge D-type trigger is electrically connected to the reset pulse amplification unit, and the reverse input end of the rising edge D-type trigger is electrically connected to the reset pulse amplification unit. The output end is electrically connected to the first end of the timing resistor, and is used for the clock port to respond to receiving a high-level first control signal, the forward output end outputs a high-level reset pulse signal, and the reverse output end outputs a low-level reverse pulse signal; the first end of the timing resistor is electrically connected to the reverse output end of the rising edge D-type trigger, and the second end of the timing resistor is electrically connected to the first end of the timing capacitor, and is used to discharge the timing capacitor to the timing resistor when the reverse output end outputs a low-level reverse pulse signal; the first end of the timing capacitor is electrically connected to the second end of the timing resistor, and the second end of the timing capacitor is grounded, and is used to discharge to the timing resistor when the reverse output end outputs a low-level reverse pulse signal to obtain a first voltage, and reset the rising edge D-type trigger when the first voltage of the timing capacitor is less than the reset input voltage of the rising edge D-type trigger.

[0012] According to an embodiment of the present invention, the reset pulse amplification unit includes a second operational amplifier and a third bias subunit; wherein the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: the first end of the second operational amplifier is electrically connected to the first end of the third bias subunit, and the second end of the second operational amplifier is electrically connected to the second end of the diode, which is used to amplify the reset pulse signal to obtain a target reset pulse signal, and send the target reset pulse signal to the diode to turn on the diode, so as to reset the gate voltage of the silicon carbide-based junction field effect transistor.

[0013] The second aspect of the present invention provides a method for amplifying and resetting a data signal, comprising: a semiconductor radiation detector sends a first output signal to a signal input buffer module; the signal input buffer module amplifies the first output signal to obtain a first amplified signal; the signal input buffer module sends the first amplified signal to a signal output amplification module; the signal output amplification module amplifies and high-pass filters the first amplified signal to output a target signal.

[0014] According to an embodiment of the present invention, the signal output amplification module includes a charge-sensitive amplification unit and a high-pass filtering unit; the method also includes: the charge-sensitive amplification unit amplifies the first amplified signal to obtain a second amplified signal; the charge-sensitive amplification unit sends the second amplified signal to the reset pulse signal generating module; the reset pulse signal generating module compares the second amplified signal, and when the amplitude of the second amplified signal is greater than a predetermined threshold, sends a target reset pulse signal to the signal input buffer module; the signal input buffer module resets the signal output amplification module according to the target reset pulse signal.

[0015] According to the reset type charge sensitive amplifier circuit and the data signal amplification and reset method of the present invention, by using a signal input buffer module, a signal output amplifier module and a reset pulse signal generating module, based on the first output signal detected by the semiconductor radiation detector and the power supply, the signal input buffer unit in the signal input buffer module amplifies the first output signal to obtain a first amplified signal, and then transmits the first amplified signal to the signal output amplifier module, the signal output amplifier module performs another amplification process and high-pass filtering process on the received first amplified signal, so as to obtain a target signal that meets the output requirements, and outputs the target signal to an external circuit, and at the same time, based on the first amplified signal, the voltage comparison unit in the reset pulse signal generating module determines the voltage amplitude of the first amplified signal, and when the voltage comparison unit determines that the amplitude of the first amplified signal exceeds a predetermined threshold, the voltage comparison unit outputs a high-level first control signal to the reset pulse width modulation unit, so that the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplifier unit according to the high-level first control signal. The reset pulse amplifying unit amplifies the received reset pulse signal to obtain a target reset pulse signal, and outputs the target reset pulse signal to the signal input buffer unit, thereby resetting the reset charge-sensitive amplifier circuit, so that the reset charge-sensitive amplifier circuit can work normally in a high-temperature and high-irradiation environment, avoiding failures of the amplifier circuit and the radiation detector system, and can adapt to working requirements in extreme working environments. In addition, a reset pulse width modulation unit is provided in the reset pulse signal generating module, so that the reset pulse width modulation unit can output a reset pulse signal of a pulse voltage of a predetermined width according to a high-level first control signal, thereby resetting the amplifier circuit. Moreover, the gate leakage current required by the reset charge-sensitive amplifier circuit is small, further reducing the noise caused by excessive gate leakage current, improving the signal-to-noise ratio of the reset charge-sensitive amplifier circuit, and being able to output more target signals per unit time, thereby improving the operating speed of the reset charge-sensitive amplifier circuit, so that it can respond to more intensive and higher-frequency input signals in a high-temperature and high-irradiation environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of the structure of a reset type charge sensitive amplifier circuit according to an embodiment of the present invention is shown;

[0018] Figure 2 A circuit diagram of a signal input buffer module according to an embodiment of the present invention is shown;

[0019] Figure 3 A circuit diagram of a signal input buffer unit according to an embodiment of the present invention is shown;

[0020] Figure 4 A circuit diagram of a signal output amplification module according to an embodiment of the present invention is shown;

[0021] Figure 5 A circuit diagram of a reset pulse signal generating module according to an embodiment of the present invention is shown;

[0022] Figure 6 A circuit diagram of a voltage comparison unit according to an embodiment of the present invention is shown;

[0023] Figure 7 A circuit diagram of a reset pulse width modulation unit according to an embodiment of the present invention is shown;

[0024] Figure 8 A circuit diagram of a reset type charge sensitive amplifier circuit according to an embodiment of the present invention is shown;

[0025] Fig. 9 A flow chart of a method for amplifying and resetting a data signal according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0026] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0027] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0028] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0029] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0030] In the technical solution of the present invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0031] Radiation detector technology has extremely important applications in frontier disciplines such as nuclear medicine, radio astronomy, particle physics, and industrial applications such as nuclear power plant monitoring, environmental quality testing, and chemical element analysis. In the entire radiation detector system, the design of the amplifier circuit is a relatively important part of the overall circuit. In the amplifier circuit of the radiation detector system, the commonly used amplifiers are mainly divided into three types: charge sensitive, voltage sensitive, and current sensitive amplifiers. Among them, charge sensitive amplifiers are widely used in high energy resolution measurement systems due to their stable output gain, low noise, and good performance.

[0032] However, the field effect transistors in the existing reset charge sensitive amplifier circuit are made of silicon materials, and the junction field effect transistors made of silicon materials are used in the reset charge sensitive amplifier circuit, so that the amplifier circuit has lower thermal noise and higher time resolution. In the process of studying the reset charge sensitive amplifier circuit, the researchers found that in the related technology, the junction field effect transistors made of existing silicon materials cannot meet the requirements of normal operation in a high temperature and high radiation environment, which leads to technical problems such as failure of the amplifier circuit and radiation detector system where the silicon-based junction field effect transistor is located.

[0033] In view of this, an embodiment of the present invention provides a reset-type charge-sensitive amplifier circuit, comprising: a signal input buffer module, a signal output amplifier module and a reset pulse signal generating module; wherein the signal input buffer module is electrically connected to the signal output amplifier module, the signal input buffer module comprises a signal input buffer unit and a voltage bias unit, the first end of the signal input buffer unit is used to be electrically connected to the semiconductor radiation detector, the second end of the signal input buffer unit is electrically connected to the voltage bias unit, and is used to read a first output signal output by the semiconductor radiation detector, amplify the first output signal and output a first amplified signal to the signal output amplifier module, the first amplified signal represents a signal obtained after amplifying the first output signal; the signal output amplifier module is electrically connected to the reset pulse signal generating module The generating module is electrically connected and used to amplify and high-pass filter the first amplified signal to obtain and output the target signal; the reset pulse signal generating module includes a voltage comparison unit, a reset pulse width modulation unit and a reset pulse amplifying unit, the first end of the voltage comparison unit is electrically connected to the signal output amplification module, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplifying unit, and the voltage comparison unit outputs a first control signal of a high level to the reset pulse width modulation unit based on the first amplified signal, and the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplifying unit based on the high-level first control signal, so as to reset the reset charge sensitive amplifier circuit.

[0034] Figure 1 A schematic structural diagram of a reset-type charge-sensitive amplifier circuit according to an embodiment of the present invention is shown.

[0035] like Figure 1 As shown, the reset type charge sensitive amplifier circuit includes a signal input buffer module 102 , a signal output amplifier module 103 and a reset pulse signal generating module 104 .

[0036] According to an embodiment of the present invention, the signal input buffer module 102 is electrically connected to the signal output amplification module 103, and the signal input buffer module 102 includes a signal input buffer unit and a voltage bias unit. The first end of the signal input buffer unit is used to be electrically connected to the semiconductor radiation detector 101, and the second end of the signal input buffer unit is electrically connected to the voltage bias unit, and is used to read the first output signal output by the semiconductor radiation detector 101, amplify the first output signal and output the first amplified signal to the signal output amplification module 103, and the first amplified signal represents the signal obtained after amplifying the first output signal.

[0037] According to an embodiment of the present invention, the semiconductor radiation detector 101 can be characterized as a device for detecting and measuring ionizing radiation. The semiconductor radiation detector 101 contains a photodiode P1. When the photodiode P1 receives radiation from a radiation source, it generates a first output signal and sends it to a signal input buffer unit in the signal input buffer module 102.

[0038] According to an embodiment of the present invention, the semiconductor radiation detector 101 includes a first resistor r1, a second resistor r2, a third resistor r3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a photodiode P1 and a third resistor r3.

[0039] According to an embodiment of the present invention, a first end of the first resistor r1 is connected to a first node q1, a second end of the first resistor r1 is grounded, a first end of the first capacitor C1 is connected to the first node q1, a second end of the first capacitor C1 is connected to a second node q2, a first end of the photodiode P1 is connected to the second node q2, a second end of the photodiode P1 is grounded, a first end of the second resistor r2 is connected to a third power supply HV Bias, a second end of the second resistor r2 is connected to a third node q3, a first end of the third resistor r3 is connected to the second node q2, a second end of the third resistor r3 is connected to the third node q3, a first end of the second capacitor C2 is connected to the third node q3, a second end of the second capacitor C2 is grounded, a first end of the third capacitor C3 is connected to the second node q2, and a second end of the third capacitor C3 is connected to a fourth node q4.

[0040] According to the embodiment of the present invention, the first node q1 is connected to the test terminal TEST, and the reset-type charge-sensitive amplifier circuit can be tested through the test terminal TEST.

[0041] According to an embodiment of the present invention, the third power supply HV Bias supplies power to the semiconductor radiation detector 101. When the photodiode P1 of the semiconductor radiation detector 101 receives radiation from the radiation source, it generates a first output signal. The first output signal in the second node q2 is sent to the signal input cache module 102 through the third capacitor C3.

[0042] According to an embodiment of the present invention, the first end of the signal input buffer module 102 is connected to the fourth node q4 , and the first output signal in the fourth node q4 can be output to the signal input buffer module 102 .

[0043] According to the embodiment of the present invention, the signal output amplification module 103 is electrically connected to the reset pulse signal generation module 104 and is used to amplify and high-pass filter the first amplified signal to obtain and output a target signal.

[0044] According to an embodiment of the present invention, the first end of the signal output amplification module 103 is connected to the fourth node q4, and the second end of the signal output amplification module 103 is connected to the fifth node, and the signal in the fifth node can be output to the reset pulse signal generating module 104.

[0045] According to an embodiment of the present invention, the signal output amplification module 103 can output the target signal to an external circuit, so that the external circuit can perform subsequent circuit operations according to the target signal.

[0046] According to an embodiment of the present invention, the reset pulse signal generating module 104 includes a voltage comparison unit, a reset pulse width modulation unit and a reset pulse amplifying unit, the first end of the voltage comparison unit is electrically connected to the signal output amplifying module 103, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplifying unit, and is used for the voltage comparison unit to output a first control signal of a high level to the reset pulse width modulation unit based on the first amplified signal, and the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplifying unit based on the high-level first control signal, so as to reset the reset charge sensitive amplifier circuit.

[0047] According to an embodiment of the present invention, the first end of the reset pulse signal generating module 104 is connected to the fifth node, and the second end of the reset pulse signal generating module 104 is connected to the sixth node. The target reset pulse signal in the sixth node can be sent to the signal input cache module 102 to facilitate resetting the amplifier circuit.

[0048] According to an embodiment of the present invention, by using a signal input buffer module 102, a signal output amplification module 103 and a reset pulse signal generation module 104, based on the first output signal detected by the semiconductor radiation detector 101 and the power supply, the signal input buffer unit in the signal input buffer module 102 amplifies the first output signal to obtain a first amplified signal, and then transmits the first amplified signal to the signal output amplification module 103. The signal output amplification module 103 performs another amplification process and a high-pass filtering process on the received first amplified signal so as to obtain a target signal that meets the output requirements, and outputs the target signal to an external circuit. At the same time, based on the first amplified signal, the voltage comparison unit in the reset pulse signal generation module 104 determines the voltage amplitude of the first amplified signal. When the voltage comparison unit determines that the amplitude of the first amplified signal exceeds a predetermined threshold value, the voltage comparison unit outputs a high-level first control signal to the reset pulse width modulation unit, so that the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplification unit according to the high-level first control signal. The reset pulse amplifying unit amplifies the received reset pulse signal to obtain a target reset pulse signal, and outputs the target reset pulse signal to the signal input buffer unit, thereby resetting the reset charge-sensitive amplifier circuit, so that the reset charge-sensitive amplifier circuit can work normally in a high-temperature and high-irradiation environment, avoiding failures of the amplifier circuit and the radiation detector system, and can adapt to working requirements in extreme working environments. In addition, a reset pulse width modulation unit is provided in the reset pulse signal generating module 104, so that the reset pulse width modulation unit can output a reset pulse signal of a pulse voltage of a predetermined width according to a high-level first control signal, thereby resetting the amplifier circuit. Moreover, the gate leakage current required by the reset charge-sensitive amplifier circuit is small, further reducing the noise caused by excessive gate leakage current, improving the signal-to-noise ratio of the reset charge-sensitive amplifier circuit, and being able to output more target signals per unit time, thereby improving the operating speed of the reset charge-sensitive amplifier circuit, so that it can respond to more intensive and higher-frequency input signals in a high-temperature and high-irradiation environment.

[0049] Figure 2 A circuit diagram of a signal input buffer module according to an embodiment of the present invention is shown.

[0050] like Figure 2 As shown, the signal input buffer module includes a signal input buffer unit 202 and a voltage bias unit 201 .

[0051] According to an embodiment of the present invention, the first end of the signal input buffer unit 202 is connected to the first end of the voltage bias unit 201, the second end of the signal input buffer unit 202 is connected to the reset pulse amplification unit, and the second end of the voltage bias unit 201 is connected to the first power supply VCC, which is a constant voltage source.

[0052] Figure 3 A circuit diagram of a signal input buffer unit according to an embodiment of the present invention is shown.

[0053] like Figure 3 As shown, the signal input buffer unit includes a silicon carbide-based junction field effect transistor SiC-JFET and a diode D1.

[0054] According to an embodiment of the present invention, a first end of the signal input buffer unit is electrically connected to the semiconductor radiation detector, and a second end of the signal input buffer unit is electrically connected to the voltage bias unit, comprising:

[0055] According to an embodiment of the present invention, the gate of the silicon carbide based junction field effect transistor SiC-JFET is electrically connected to the first end of the diode D1 and the semiconductor radiation detector, the drain of the silicon carbide based junction field effect transistor SiC-JFET is electrically connected to the voltage bias unit, and the source of the silicon carbide based junction field effect transistor SiC-JFET is grounded, so as to amplify the first output signal to obtain a first amplified signal, and output the first amplified signal to the signal output amplification module.

[0056] According to an embodiment of the present invention, the diode D1 may be a fast recovery diode.

[0057] According to an embodiment of the present invention, the fourth node q4 is located on a circuit where the gate of the silicon carbide-based junction field effect transistor SiC-JFET is electrically connected to the first end of the diode D1, that is, the second end of the third capacitor C3 is connected to the fourth node q4, the first end of the diode D1 is connected to the fourth node q4, the gate of the silicon carbide-based junction field effect transistor SiC-JFET is connected to the fourth node q4, and the first output signal in the fourth node q4 is transmitted to the gate of the silicon carbide-based junction field effect transistor SiC-JFET, so that the silicon carbide-based junction field effect transistor SiC-JFET is turned on, and the first output signal is amplified to obtain a first amplified signal, and the amplification factor is between 10 and 100 times, for example, 10 times, 20 times, 30 times, 40 times, 50 times, 60 times, 70 times, 80 times, 90 times, and 100 times.

[0058] According to an embodiment of the present invention, the first end of the diode D1 is electrically connected to the gate of the silicon carbide-based junction field effect transistor SiC-JFET and the semiconductor radiation detector, and the second end of the diode D1 is electrically connected to the second end of the reset pulse amplification unit, so that when the reset pulse signal at the second end of the diode D1 is a high pulse signal, the first end of the diode D1 is a high-level first output signal.

[0059] According to an embodiment of the present invention, the second end of the diode D1 is connected to the sixth node q6, and the output end of the reset pulse amplifying unit is connected to the sixth node q6. When the second end of the reset pulse amplifying unit outputs a high-pulse target reset pulse signal to the diode D1, the voltage at the second end of the diode D1 is greater than the voltage at the first end of the diode D1, and the diode D1 is turned on, so that the first end of the diode D1 outputs a high-level first output signal, and sends the high-level first output signal to the gate of the silicon carbide-based junction field effect transistor SiC-JFET, so as to facilitate the reset of the signal output amplification module.

[0060] According to an embodiment of the present invention, this embodiment adopts a silicon carbide-based junction field effect transistor SiC-JFET and a diode D1, and the gate of the silicon carbide-based junction field effect transistor SiC-JFET is connected to the first end of the diode D1. When the first output signal is sent to the gate of the silicon carbide-based junction field effect transistor SiC-JFET, the first output signal is amplified for the first time by the silicon carbide-based junction field effect transistor SiC-JFET to obtain the first amplified signal, and when the second end of the diode D1 receives a high-pulse target reset pulse signal, the voltage across the diode D1 changes, the voltage value at the second end of the diode D1 is greater than the voltage value at the first end, and the diode D1 is turned on, so that the voltage value of the first output signal received by the gate of the silicon carbide-based junction field effect transistor SiC-JFET changes, thereby resetting the signal output amplification module.

[0061] According to an embodiment of the present invention, this embodiment adopts a silicon carbide-based junction field effect transistor SiC-JFET, and according to the wide bandgap characteristics of the silicon carbide-based junction field effect transistor, the reset-type charge-sensitive amplifier circuit can be operated in a high-temperature environment of 150°C, and the reset-type charge-sensitive amplifier circuit can also be operated in a high-irradiation environment. At the same time, the gate leakage current of the silicon carbide-based junction field effect transistor SiC-JFET in the reset-type charge-sensitive amplifier circuit only requires a current of pA level, thereby reducing the noise introduced by the gate leakage current and reducing the noise caused by the silicon carbide-based The noise of the first amplified signal output by the junction field effect transistor SiC-JFET further improves the quality and accuracy of the output amplified signal, improves the reliability and sensitivity of the reset charge-sensitive amplifier circuit, and, because the gate leakage current of the present invention is small, the reset charge-sensitive amplifier circuit can respond to more intensive and higher frequency input signals per unit time, and then output more target signals, thereby enhancing the signal processing capability of the reset charge-sensitive amplifier circuit, and enabling the reset charge-sensitive amplifier circuit to adapt to the processing and application requirements of complex signals in high temperature and high radiation environments.

[0062] According to an embodiment of the present invention, the voltage bias unit includes a first power source VCC and a first bias resistor R1 , and the first power source VCC is a power source with a constant voltage.

[0063] According to an embodiment of the present invention, the first power source VCC is used to provide a constant voltage to the first bias resistor R1.

[0064] According to an embodiment of the present invention, the first power source VCC may also be used to supply power to the silicon carbide based junction field effect transistor SiC-JFET and the fast recovery diode.

[0065] According to an embodiment of the present invention, the first power source VCC may be connected to the seventh node q7.

[0066] According to an embodiment of the present invention, a first end of the first bias resistor R1 is electrically connected to a first power supply VCC, and a second end of the first bias resistor R1 is electrically connected to a drain of a silicon carbide-based junction field effect transistor SiC-JFET, for adjusting a bias current of the drain of the silicon carbide-based junction field effect transistor SiC-JFET, and providing a stable static operating point to the silicon carbide-based junction field effect transistor SiC-JFET.

[0067] According to an embodiment of the present invention, the first end of the first bias resistor R1 may be connected to the seventh node q7, and the first power source VCC is used to supply power to the first bias resistor R1 and the signal input buffer unit.

[0068] According to an embodiment of the present invention, the first bias resistor R1 and the silicon carbide-based junction field effect transistor SiC-JFET together form a common-source amplifier circuit.

[0069] According to an embodiment of the present invention, the first bias resistor R1 is characterized as a variable resistor with adjustable resistance. By adjusting the resistance of the first bias resistor R1, the bias current of the drain of the silicon carbide-based junction field effect transistor SiC-JFET is adjusted, so that when the semiconductor radiation detector is not working, the voltages at the in-phase input terminal and the reverse input terminal of the amplifier in the signal output amplification module are made the same.

[0070] According to an embodiment of the present invention, this embodiment uses a first power supply VCC to provide constant voltage power to electronic devices such as a first bias resistor R1, so that the reset-type charge-sensitive amplifier circuit can work normally. Based on the first bias resistor R1 connected to the drain of the silicon carbide-based junction field effect transistor SiC-JFET, a stable static operating point is provided for the silicon carbide-based junction field effect transistor SiC-JFET, so that when the semiconductor radiation detector is not working, the amplifier in the signal output amplification module can work normally.

[0071] Figure 4A circuit diagram of a signal output amplification module according to an embodiment of the present invention is shown.

[0072] like Figure 4 As shown, the signal output amplification module includes a charge sensitive amplification unit 401 and a high pass filtering unit 402 .

[0073] According to an embodiment of the present invention, the signal output amplification module is electrically connected to the reset pulse signal generation module, and includes:

[0074] According to an embodiment of the present invention, the first end of the charge-sensitive amplifier unit 401 is electrically connected to the drain of the silicon carbide-based junction field effect transistor SiC-JFET, and the second end of the charge-sensitive amplifier unit 401 is electrically connected to the high-pass filter unit 402, for amplifying the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the high-pass filter unit 402 and the voltage comparison unit.

[0075] According to an embodiment of the present invention, the charge-sensitive amplifier unit 401 includes a third operational amplifier U3, a feedback capacitor CF and a fourth bias subunit, wherein the fourth bias subunit includes a second bias resistor R2 and a third bias resistor R3.

[0076] According to an embodiment of the present invention, there is an eighth node q8 in the circuit where the first bias resistor R1 is connected to the seventh node q7, the first end of the second bias resistor R2 is connected to the eighth node q8, the second end of the second bias resistor R2 is connected to the first end of the third bias resistor R3, the second end of the third bias resistor R3 is grounded, the inverting input end of the third operational amplifier U3 is connected to the ninth node q9, the ninth node q9 is located in the circuit where the second end of the second bias resistor R2 is connected to the first end of the third bias resistor R3, the non-inverting input end of the third operational amplifier U3 is connected to the tenth node q10, the tenth node q10 is located in the circuit where the second end of the first bias resistor R1 is electrically connected to the drain of the silicon carbide-based junction field effect transistor SiC-JFET, the third end of the third operational amplifier U3 is connected to the first power supply VCC, the fourth end of the third operational amplifier U3 is grounded, the output end of the third operational amplifier U3 is connected to the fifth node q5, the first end of the feedback capacitor CF is connected to the fifth node q5, and the second end of the feedback capacitor CF is connected to the fourth node q4.

[0077] According to an embodiment of the present invention, the feedback capacitor CF, the silicon carbide-based junction field effect transistor SiC-JFET and the charge-sensitive amplifier unit together form a negative feedback amplifier circuit.

[0078] According to an embodiment of the present invention, the third operational amplifier U3 can be used to amplify the first amplified signal to obtain a second amplified signal. The feedback capacitor CF can be used to determine the amplification factor of the first amplified signal by the third operational amplifier U3. The amplification factor of the first amplified signal by the third operational amplifier U3 can be calculated according to formula (1).

[0079]

[0080] Av may be represented as the amplification factor of the first amplified signal by the third operational amplifier U3, CF may be represented as the capacitance value of the feedback capacitor CF, and Q may be represented as the charge number output by the semiconductor radiation detector.

[0081] According to an embodiment of the present invention, the high-pass filtering unit 402 is electrically connected to the charge-sensitive amplifying unit 401, and is used to perform high-pass filtering on the second amplified signal, and amplify the signal after the high-pass filtering to obtain and output the target signal.

[0082] According to the embodiment of the present invention, a first terminal of the high-pass filter unit 402 is connected to the fifth node q5, and an output terminal of the high-pass filter unit 402 outputs a target signal.

[0083] According to an embodiment of the present invention, this embodiment adopts a charge-sensitive amplifier unit 401 and a high-pass filter unit 402, and uses the third operational amplifier U3 in the charge-sensitive unit to amplify the first amplified signal for a second time, thereby obtaining a second amplified signal, and then sends the second amplified signal to the high-pass filter unit 402, and the high-pass filter unit 402 performs high-pass filtering and amplification processing on the second amplified signal again to obtain and output the target signal.

[0084] According to an embodiment of the present invention, the high-pass filtering unit 402 includes a high-pass filtering sub-unit and a first operational amplifier U1 .

[0085] According to an embodiment of the present invention, the high-pass filtering unit 402 is electrically connected to the charge-sensitive amplification unit, and includes:

[0086] According to an embodiment of the present invention, the first end of the high-pass filter subunit is electrically connected to the charge-sensitive amplifier unit, and the second end of the high-pass filter subunit is electrically connected to the input end of the first operational amplifier U1, for performing high-pass filtering on the second amplified signal to obtain a filtered signal.

[0087] According to an embodiment of the present invention, the high-pass filter subunit includes a filter capacitor CFIL, a filter resistor RFIL, a fourth bias resistor R4 and a fifth bias resistor R5.

[0088] According to an embodiment of the present invention, a first end of the filter capacitor CFIL is connected to a fifth node q5, a second end of the filter capacitor CFIL is connected to an eleventh node q11, a first end of the filter resistor RFIL is connected to the eleventh node q11, a second end of the filter resistor RFIL is grounded, a first end of the fourth bias resistor R4 is connected to a twelfth node q12, a second end of the fourth bias resistor R4 is connected to a thirteenth node q13, a first end of the fifth bias resistor R5 is connected to the twelfth node q12, and a second end of the fifth bias resistor R5 is grounded.

[0089] According to an embodiment of the present invention, the input end of the first operational amplifier U1 is electrically connected to the second end of the high-pass filter subunit, and the output end of the first operational amplifier U1 outputs a target signal for amplifying the filtered signal to obtain and output the target signal to an external circuit.

[0090] According to an embodiment of the present invention, the non-inverting input terminal of the first operational amplifier U1 is connected to the eleventh node q11, the inverting input terminal of the first operational amplifier U1 is connected to the twelfth node q12, the third terminal of the first operational amplifier U1 is connected to the second power supply V2, the second power supply V2 is a +5V voltage source, the fourth terminal of the first operational amplifier U1 is grounded, and the output terminal of the first operational amplifier U1 outputs the target signal.

[0091] According to an embodiment of the present invention, the fourth bias resistor R4 and the fifth bias resistor R5 can be used to provide a stable static operating point for the reverse input terminal of the first operational amplifier U1. The filter capacitor CFIL and the filter resistor RFIL form a high-pass filter circuit, which can filter the second amplified signal in the frequency domain to obtain the filtered second amplified signal, thereby avoiding the influence of the output impedance change on the filtering characteristics. The cutoff frequency of the high-pass filter unit 402 can be calculated according to formula (2).

[0092]

[0093] Wherein, f may be represented as the cut-off frequency of the high-pass filter unit 402 , CFIL may be represented as the capacitance value of the filter capacitor CFIL, and RFIL may be represented as the resistance value of the filter resistor RFIL.

[0094] According to an embodiment of the present invention, the high-pass filter unit 402 further includes an output resistor ROUT.

[0095] According to the embodiment of the present invention, a first end of the output resistor ROUT is connected to the thirteenth node q13, and a second end of the output resistor ROUT is grounded.

[0096] According to an embodiment of the present invention, when the second power supply V2 is supplied, the second amplified signal is filtered through a high-pass filtering circuit composed of a filtering capacitor CFIL and a filtering resistor RFIL, and a portion of the second amplified signal that is lower than the cutoff frequency of the high-pass filtering unit 402 is filtered out to obtain a portion of the second amplified signal that is higher than the cutoff frequency of the high-pass filtering unit 402, and amplification processing is performed for the third time on the portion of the second amplified signal that is higher than the cutoff frequency of the high-pass filtering unit 402 to obtain a target signal that meets the output requirements, and the target signal is output to an external circuit, thereby realizing high-pass filtering and amplification processing of the second amplified signal, thereby obtaining the target signal, and outputting the target signal to the external circuit.

[0097] Figure 5 A circuit diagram of a reset pulse signal generating module according to an embodiment of the present invention is shown.

[0098] like Figure 5 As shown, the reset pulse signal generating module includes a voltage comparing unit 501 , a reset pulse width modulation unit 502 and a reset pulse amplifying unit 503 .

[0099] According to an embodiment of the present invention, the first end of the voltage comparison unit 501 is electrically connected to the signal output amplification module, the second end of the voltage comparison unit 501 is electrically connected to the first end of the reset pulse width modulation unit 502, the second end of the reset pulse width modulation unit 502 is electrically connected to the reset pulse amplification unit 503, and the second power supply V2 is a constant voltage source of +5V.

[0100] Figure 6 A circuit diagram of a voltage comparison unit according to an embodiment of the present invention is shown.

[0101] like Figure 6 As shown, the voltage comparison unit includes a first bias subunit, a second bias subunit and a voltage comparator U4.

[0102] According to an embodiment of the present invention, a first end of a voltage comparison unit is electrically connected to a signal output amplification module, a second end of the voltage comparison unit is electrically connected to a first end of a reset pulse width modulation unit, and a second end of the reset pulse width modulation unit is electrically connected to a reset pulse amplification unit, including:

[0103] According to an embodiment of the present invention, the first end of the first bias subunit is electrically connected to the second end of the charge-sensitive amplifier unit, the second end of the first bias subunit is grounded, and the third end of the first bias subunit is electrically connected to the same-direction input end of the voltage comparator U4, so as to divide the second amplified signal output by the charge-sensitive amplifier unit and provide the input voltage to be compared to the voltage comparator U4.

[0104] According to an embodiment of the present invention, the first bias subunit includes a sixth bias resistor R6 and a seventh bias resistor R7.

[0105] According to an embodiment of the present invention, a first end of the sixth bias resistor R6 is connected to the fifth node q5, a second end of the sixth bias resistor R6 is electrically connected to a first end of the seventh bias resistor R7, and a second end of the seventh bias resistor R7 is grounded.

[0106] According to the embodiment of the present invention, the sixth bias resistor R6 and the seventh bias resistor R7 can divide the second amplified signal output by the charge-sensitive amplifier unit to provide an input voltage to be compared to the voltage comparator U4.

[0107] According to an embodiment of the present invention, a first end of the second bias subunit is electrically connected to the second power supply V2, a second end of the second bias subunit is grounded, and a third end of the second bias subunit is electrically connected to the reverse input end of the voltage comparator U4, for providing a reference voltage to the reverse input end of the voltage comparator U4.

[0108] According to an embodiment of the present invention, the second biasing subunit includes an eighth biasing resistor R8 and a ninth biasing resistor R9.

[0109] According to an embodiment of the present invention, a first end of the eighth bias resistor R8 is connected to the second power supply V2, a second end of the eighth bias resistor R8 is electrically connected to a first end of the ninth bias resistor R9, and a second end of the ninth bias resistor R9 is grounded.

[0110] According to the embodiment of the present invention, the eighth bias resistor R8 and the ninth bias resistor R9 can provide a reference voltage to the inverting input terminal of the voltage comparator U4.

[0111] According to an embodiment of the present invention, the same-direction input terminal of the voltage comparator U4 is electrically connected to the third terminal of the first bias subunit, the reverse input terminal of the voltage comparator U4 is electrically connected to the third terminal of the second bias subunit, and the output terminal of the voltage comparator U4 outputs a first control signal, which is used to output a high-level first control signal to the reset pulse width modulation unit when the voltage of the same-direction input terminal is greater than the voltage of the reverse input terminal, and output a low-level first control signal to the reset pulse width modulation unit when the voltage of the same-direction input terminal is less than the voltage of the reverse input terminal.

[0112] According to an embodiment of the present invention, the non-inverting input terminal of the voltage comparator U4 is connected to the fourteenth node q14, and the fourteenth node q14 is located in a circuit where the second end of the sixth bias resistor R6 is electrically connected to the first end of the seventh bias resistor R7. The inverting input terminal of the voltage comparator U4 is connected to the fifteenth node q15, and the fifteenth node q15 is located in a circuit where the second end of the eighth bias resistor R8 is electrically connected to the first end of the ninth bias resistor R9. The third terminal of the voltage comparator U4 is connected to the second power supply V2, the fourth terminal of the voltage comparator U4 is grounded, and the output terminal of the voltage comparator outputs a first control signal.

[0113] According to an embodiment of the present invention, the voltage comparator U4 can judge the voltage value of the second amplified signal. When the voltage value of the second amplified signal is greater than a predetermined voltage threshold, the voltage at the same-direction input terminal of the voltage comparator U4 is greater than the voltage at the reverse input terminal, and the voltage comparator U4 outputs a high-level first control signal. The predetermined voltage threshold is calculated according to formula (3).

[0114]

[0115] Among them, V can be represented as a predetermined voltage threshold, VCC can be represented as a voltage value of the first power supply, R6 can be represented as the resistance value of the sixth bias resistor R6, R7 can be represented as the resistance value of the seventh bias resistor R7, R8 can be represented as the resistance value of the eighth bias resistor R8, and R9 can be represented as the resistance value of the ninth bias resistor R9.

[0116] According to an embodiment of the present invention, when the voltage value of the second amplified signal is less than the predetermined voltage threshold, the voltage at the non-inverting input terminal of the voltage comparator U4 is less than the voltage at the inverting input terminal, and the voltage comparator U4 outputs a low-level first control signal.

[0117] According to an embodiment of the present invention, when the second power supply V2 is supplied, the second amplified signal is sent to the positive input terminal of the voltage comparator U4 through the third operational amplifier U3 of the present embodiment, and the voltage value of the second amplified signal is continuously compared and judged by the voltage comparator U4. When the voltage value of the second amplified signal is greater than a predetermined voltage threshold, the voltage comparator U4 outputs a high-level first control signal. When the voltage value of the second amplified signal is less than the predetermined voltage threshold, the voltage comparator U4 outputs a low-level first control signal, thereby realizing the voltage value of the second amplified signal being judged by the voltage comparator U4, and outputting the first control signal for controlling the reset pulse width modulation unit according to the specific voltage value of the second amplified signal, thereby controlling the working state of the entire reset charge sensitive amplifier circuit.

[0118] According to an embodiment of the present invention, the present invention continuously monitors the voltage value of the second amplified signal by using a voltage comparator U4, thereby achieving a first control signal for controlling circuit reset according to the second amplified signal at the current moment, thereby enabling the reset-type charge-sensitive amplifier circuit to be flexibly reset without setting a fixed period for resetting the circuit. While the reset-type charge-sensitive amplifier circuit can respond to a more intensive and higher-frequency first input signal, damage to the reset-type charge-sensitive amplifier circuit is avoided, thereby further improving the reliability of the reset-type charge-sensitive amplifier circuit.

[0119] Figure 7 A circuit diagram of a reset pulse width modulation unit according to an embodiment of the present invention is shown.

[0120] like Figure 7 As shown, the reset pulse width modulation unit includes a rising edge D-type trigger, a timing resistor RTM and a timing capacitor CTM.

[0121] According to an embodiment of the present invention, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including:

[0122] According to an embodiment of the present invention, the clock port of the rising edge D-type flip-flop is electrically connected to the output end of the voltage comparator U4, the data input port and the set port of the rising edge D-type flip-flop are electrically connected to the second power supply V2, and are used to maintain the high-level input state of the data input port and the set port of the rising edge D-type flip-flop, the reset port of the rising edge D-type flip-flop is electrically connected to the first end of the timing capacitor CTM, the forward output end of the rising edge D-type flip-flop is electrically connected to the reset pulse amplification unit, and the reverse output end of the rising edge D-type flip-flop is electrically connected to the first end of the timing resistor RTM, and the clock port responds to receiving a high-level first control signal, the forward output end outputs a high-level reset pulse signal, and the reverse output end outputs a low-level reverse pulse signal.

[0123] According to an embodiment of the present invention, when the clock port of the rising edge D-type flip-flop receives a first control signal of a high level, the reverse output end of the rising edge D-type flip-flop outputs a low-level reverse pulse signal, and the forward output end outputs a high-level reset pulse signal, thereby controlling the reset-type charge-sensitive amplifier circuit to reset. When the clock port of the rising edge D-type flip-flop receives a first control signal of a low level, the reverse output end of the rising edge D-type flip-flop outputs a high-level reverse pulse signal, and the forward output end outputs a low-level reset pulse signal, and the reset-type charge-sensitive amplifier circuit maintains a normal working state.

[0124] According to an embodiment of the present invention, the first end of the timing resistor RTM is electrically connected to the reverse output end of the rising edge D-type flip-flop, and the second end of the timing resistor RTM is connected to the sixteenth node q16. The sixteenth node q16 is located in a circuit where the reset port of the rising edge D-type flip-flop is electrically connected to the first end of the timing capacitor CTM, and is used to facilitate the timing capacitor CTM to discharge to the timing resistor RTM when the reverse output end outputs a low-level reverse pulse signal.

[0125] According to an embodiment of the present invention, a first end of the timing capacitor CTM is electrically connected to a second end of the timing resistor RTM, and the second end of the timing capacitor CTM is grounded, so as to discharge to the timing resistor RTM when a low-level reverse pulse signal is output at the reverse output end, thereby obtaining a first voltage. When the first voltage of the timing capacitor CTM is less than a reset input voltage of the rising-edge D-type trigger, the rising-edge D-type trigger is reset.

[0126] According to an embodiment of the present invention, when the clock port of the rising edge D-type flip-flop receives a high-level first control signal, the reverse output terminal of the rising edge D-type flip-flop outputs a low-level reverse pulse signal, and the forward output terminal outputs a high-level reset pulse signal. The timing capacitor CTM discharges the charge through the timing resistor RTM. When the voltage on the timing capacitor CTM is lower than the reset input voltage of the rising edge D-type flip-flop, the output of the rising edge D-type flip-flop flips over and outputs a high-level reset pulse signal with a predetermined pulse width to the reset pulse amplification unit. The predetermined pulse width can be calculated according to formula (4).

[0127]

[0128] Wherein, T may be characterized as a predetermined pulse width, RTM may be characterized as a resistance value of a timing resistor RTM, and CTM may be characterized as a capacitance value of a timing capacitor CTM.

[0129] According to an embodiment of the present invention, when the second power supply V2 is used for power supply, this embodiment is based on a rising edge D-type trigger. When the rising edge D-type trigger receives a first control signal of a high level, the reverse output end of the rising edge D-type trigger outputs a low level reverse pulse signal, so that the timing capacitor CTM is discharged through the timing resistor RTM. When the voltage on the timing capacitor CTM is lower than the reset input voltage of the rising edge D-type trigger, the output of the rising edge D-type trigger is flipped, and a high level reset pulse signal with a predetermined pulse width is output, thereby resetting the reset charge sensitive amplifier circuit, thereby outputting a new target signal.

[0130] According to an embodiment of the present invention, the reset pulse amplifying unit includes a second operational amplifier U2 and a third biasing subunit.

[0131] According to an embodiment of the present invention, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including:

[0132] According to an embodiment of the present invention, the first end of the second operational amplifier U2 is electrically connected to the first end of the third bias subunit, and the second end of the second operational amplifier U2 is electrically connected to the second end of the diode D1, so as to amplify the reset pulse signal to obtain a target reset pulse signal, and send the target reset pulse signal to the diode D1 to turn on the diode D1, so as to reset the gate voltage of the silicon carbide-based junction field effect transistor SiC-JFET.

[0133] According to an embodiment of the present invention, the third bias subunit includes a tenth bias resistor R10 and an eleventh bias resistor R11, the tenth bias resistor R10 is a sliding variable resistor with variable resistance, the first end of the tenth bias resistor R10 is electrically connected to the positive output end of the rising edge D-type trigger, the second end of the tenth bias resistor R10 is connected to the seventeenth node q17, the first end of the eleventh bias resistor R11 is connected to the seventeenth node q17, the second end of the eleventh bias resistor R11 is grounded, the in-phase input end of the second operational amplifier U2 is connected to the seventeenth node q17, the reverse input end of the second operational amplifier U2 is connected to the sixth node q6, the output end of the second operational amplifier U2 is electrically connected to the second end of the diode D1, and the sixth node q6 is located on the circuit where the output end of the second operational amplifier U2 is electrically connected to the second end of the diode D1.

[0134] According to an embodiment of the present invention, when the positive output terminal of the rising edge D-type flip-flop outputs a high-level reset pulse signal to the second operational amplifier U2, the high-level reset pulse signal is amplified by the second operational amplifier U2, so that the positive electrode voltage of the diode D1 is greater than the negative electrode voltage of the diode D1, the diode D1 is turned on to increase the gate voltage of the silicon carbide-based junction field effect transistor SiC-JFET, the voltage of the positive input terminal of the third operational amplifier U3 is reduced, and the voltage of the second amplified signal is reduced, thereby realizing the reset of the reset-type charge-sensitive amplifier circuit. When the positive output terminal of the rising edge D-type flip-flop outputs a low-level reset pulse signal to the second operational amplifier U2, the reset-type charge-sensitive amplifier circuit is not reset and remains in the original state to work normally.

[0135] According to an embodiment of the present invention, this embodiment amplifies the high-level reset pulse signal based on the tenth bias resistor R10, the eleventh bias resistor R11 and the second operational amplifier U2, thereby realizing the conduction of the diode D1, so as to reset the reset-type charge-sensitive amplifier circuit.

[0136] Figure 8 A circuit diagram of a reset-type charge-sensitive amplifier circuit according to an embodiment of the present invention is shown.

[0137] like Figure 8 As shown, Figure 8 The schematic diagram of the full circuit of the reset type charge sensitive amplifier circuit is shown, and the reset type charge sensitive amplifier circuit includes a signal input buffer module 801, a signal output amplifier module 802 and a reset pulse signal generating module 803. After receiving the irradiation, the photodiode P1 of the semiconductor radiation detector 804 generates a first output signal, and then transmits the first output signal to the silicon carbide based junction field effect transistor SiC-JFET. The first output signal of the gate of the silicon carbide based junction field effect transistor SiC-JFET is amplified by the field effect transistor to obtain a first amplified signal. The first amplified signal is amplified twice by the third operational amplifier U3 to obtain a second amplified signal. The second amplified signal is sent to the high-pass filter unit and the voltage comparison unit at the fifth node q5 at the same time. The second amplified signal below the cut-off frequency is filtered out by the filter capacitor CFIL and the filter resistor RFIL, and the second amplified signal above the cut-off frequency is transmitted to the first operational amplifier U1 for amplification processing to obtain and output the target signal. At the same time, the voltage comparator U4 compares and detects the voltage value of the second amplified signal.

[0138] According to an embodiment of the present invention, when the voltage value of the second amplified signal is greater than a predetermined voltage threshold, a high-level first control signal is output to the rising edge D-type flip-flop, a low-level reverse pulse signal is output from the reverse output terminal of the rising edge D-type flip-flop, the timing capacitor CTM is controlled to discharge to the timing resistor RTM, and the positive output terminal of the rising edge D-type flip-flop outputs a high-level reset pulse signal with a fixed pulse width, the high-level reset pulse signal is transmitted to the positive input terminal of the second operational amplifier U2, the second operational amplifier U2 amplifies the high-level reset pulse signal to obtain a target reset pulse signal, and the target reset pulse signal is transmitted to the positive electrode of the fast recovery diode D1. At this time, the positive electrode voltage of the fast recovery diode D1 is greater than the negative electrode voltage, the fast recovery diode D1 is turned on, the voltage of the gate of the silicon carbide-based junction field effect transistor SiC-JFET rises, and the voltage of the positive input terminal of the third operational amplifier U3 decreases, so that the voltage value of the second amplified signal decreases, thereby realizing the reset of the amplifier circuit.

[0139] According to an embodiment of the present invention, when the voltage value of the second amplified signal is less than a predetermined voltage threshold, a low-level first control signal is output to the rising edge D-type flip-flop, a high-level reverse pulse signal is output from the reverse output end of the rising edge D-type flip-flop, and a low-level reset pulse signal is output from the forward output end of the rising edge D-type flip-flop. The second operational amplifier U2 amplifies the first-level reset pulse signal to obtain a target reset pulse signal, and the target reset pulse signal is transmitted to the anode of the fast recovery diode D1. At this time, the anode voltage of the fast recovery diode D1 is less than the cathode voltage, the fast recovery diode D1 is turned off, the amplifying circuit is not reset, and normal operation is maintained.

[0140] Fig. 9 A flow chart of a method for amplifying and resetting a data signal according to an embodiment of the present invention is shown.

[0141] like Fig. 9 As shown, the data signal amplification and resetting method of this embodiment includes operations S910 to S940.

[0142] In operation S910 , the semiconductor radiation detector sends a first output signal to a signal input buffer module.

[0143] In operation S920, the signal input buffer module amplifies the first output signal to obtain a first amplified signal.

[0144] According to an embodiment of the present invention, the silicon carbide-based junction field effect transistor in the signal input buffer module amplifies the first output signal to obtain a first amplified signal.

[0145] In operation S930, the signal input buffer module sends the first amplified signal to the signal output amplification module.

[0146] In operation S940 , the signal output amplification module amplifies and performs high-pass filtering on the first amplified signal to output a target signal.

[0147] According to an embodiment of the present invention, the third operational amplifier in the signal output amplification module amplifies the first amplified signal to obtain a second amplified signal, and then outputs the second amplified signal to the high-pass filtering unit in the signal output amplification module for high-pass filtering and amplification processing, filters out the second amplified signal whose frequency is lower than the cutoff frequency of the high-pass filtering unit, amplifies the second amplified signal whose frequency is higher than the cutoff frequency of the high-pass filtering unit, and obtains and outputs the target signal.

[0148] According to an embodiment of the present invention, since the semiconductor radiation detector sends a first output signal to the signal input buffer module, the silicon carbide-based junction field effect transistor in the signal input buffer module amplifies the first output signal to obtain a first amplified signal, the signal input buffer module sends the first amplified signal to the signal output amplification module, the third operational amplifier in the signal output amplification module amplifies the first amplified signal to obtain a second amplified signal, and then outputs the second amplified signal to the high-pass filtering unit in the signal output amplification module for high-pass filtering and amplification processing to obtain and output the target signal, thereby realizing the reset-type charge-sensitive amplifier circuit. The first output signal obtained by the semiconductor radiation detector is amplified and processed to obtain and output a target signal. Due to the use of silicon carbide-based junction field effect transistors, the reset-type charge-sensitive amplifier circuit can amplify data signals in a high-temperature, high-irradiation environment, and the gate leakage current required by the reset-type charge-sensitive amplifier circuit is small, which reduces the noise caused by excessive gate leakage current, improves the signal-to-noise ratio of the reset-type charge-sensitive amplifier circuit, and can output more target signals per unit time, thereby improving the operating speed of the reset-type charge-sensitive amplifier circuit, so that it can respond to more intensive and higher-frequency input signals in a high-temperature, high-irradiation environment.

[0149] According to an embodiment of the present invention, the signal output amplification module includes a charge-sensitive amplification unit and a high-pass filtering unit, and the data signal amplification and reset method further includes:

[0150] According to an embodiment of the present invention, the charge-sensitive amplifier unit amplifies the first amplified signal to obtain a second amplified signal.

[0151] According to an embodiment of the present invention, the charge-sensitive amplifier unit sends a second amplified signal to the reset pulse signal generating module.

[0152] According to an embodiment of the present invention, the reset pulse signal generating module compares the second amplified signal, and sends a target reset pulse signal to the signal input buffer module when the amplitude of the second amplified signal is greater than a predetermined voltage threshold.

[0153] According to an embodiment of the present invention, when the amplitude of the second amplified signal is greater than a predetermined voltage threshold, a high-level reset pulse signal is output to the reset pulse amplifying unit in the reset pulse signal generating module, and the reset pulse amplifying unit amplifies the high-level reset pulse signal to obtain a target reset pulse signal, so that the diode in the signal input buffer module is turned on, thereby resetting the amplifier circuit.

[0154] According to an embodiment of the present invention, when the amplitude of the second amplified signal is less than a predetermined voltage threshold, a low-level reset pulse signal is output to the reset pulse amplifying unit in the reset pulse signal generating module, and the diode in the signal input buffer module is not turned on, so that the amplifying circuit is not reset.

[0155] According to an embodiment of the present invention, the signal input buffer module resets the signal output amplification module according to the target reset pulse signal.

[0156] According to an embodiment of the present invention, since the charge-sensitive amplifying unit amplifies the first amplified signal to obtain the second amplified signal, the charge-sensitive amplifying unit sends the second amplified signal to the reset pulse signal generating module, the reset pulse signal generating module compares the second amplified signal, and when the amplitude of the second amplified signal is greater than a predetermined voltage threshold, a high-level reset pulse signal is output to the reset pulse amplifying unit in the reset pulse signal generating module, the reset pulse amplifying unit amplifies the high-level reset pulse signal to obtain a target reset pulse signal, the signal input buffer module resets the signal output amplifying module according to the target reset pulse signal, and when the amplitude of the second amplified signal is less than a predetermined voltage threshold, a low-level reset pulse signal is output to the reset pulse amplifying unit in the reset pulse signal generating module, the diode in the signal input buffer module is not turned on, and thus the amplifying circuit is not reset, thereby realizing the resetting of the data signal based on the reset-type charge-sensitive amplifying circuit.

[0157] According to an embodiment of the present invention, the present invention continuously monitors the voltage value of the second amplified signal through a reset pulse signal generating module, thereby realizing that a target reset pulse signal for controlling circuit reset can be flexibly output according to the second amplified signal at the current moment, thereby enabling the reset-type charge-sensitive amplifier circuit to be flexibly reset without setting a fixed period for resetting the circuit. While the reset-type charge-sensitive amplifier circuit can respond to a more intensive and higher-frequency first input signal, damage to the reset-type charge-sensitive amplifier circuit can be avoided, thereby further improving the reliability of the reset-type charge-sensitive amplifier circuit.

[0158] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0159] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A reset type charge sensitive amplifier circuit, characterized in that: include: Signal input buffer module, signal output amplification module and reset pulse signal generation module; wherein, The signal input buffer module is electrically connected to the signal output amplification module, and the signal input buffer module includes a signal input buffer unit and a voltage bias unit, wherein the first end of the signal input buffer unit is electrically connected to the semiconductor radiation detector, and the second end of the signal input buffer unit is electrically connected to the voltage bias unit, and is used to read a first output signal output by the semiconductor radiation detector, amplify the first output signal and output a first amplified signal to the signal output amplification module, wherein the first amplified signal represents a signal obtained after amplifying the first output signal; The signal output amplification module is electrically connected to the reset pulse signal generation module, and is used to amplify and high-pass filter the first amplified signal to obtain and output a target signal; The reset pulse signal generating module comprises a voltage comparing unit, a reset pulse width modulation unit and a reset pulse amplifying unit, wherein the first end of the voltage comparing unit is electrically connected to the signal output amplifying module, the second end of the voltage comparing unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplifying unit, and the voltage comparing unit outputs a first control signal of a high level to the reset pulse width modulation unit based on the first amplified signal, and the reset pulse width modulation unit outputs a reset pulse signal to the reset pulse amplifying unit based on the first control signal of the high level, so as to reset the reset type charge sensitive amplifier circuit; The signal input buffer unit includes a silicon carbide-based junction field effect transistor and a diode; a first end of the signal input buffer unit is electrically connected to the semiconductor radiation detector, and a second end of the signal input buffer unit is electrically connected to the voltage bias unit, including: a gate of the silicon carbide-based junction field effect transistor is electrically connected to the first end of the diode and the semiconductor radiation detector, a drain of the silicon carbide-based junction field effect transistor is electrically connected to the voltage bias unit, and a source of the silicon carbide-based junction field effect transistor is grounded, for amplifying the first output signal to obtain the first amplified signal, and outputting the first amplified signal to the signal output amplification module; a first end of the diode is electrically connected to the gate of the silicon carbide-based junction field effect transistor and the semiconductor radiation detector, and a second end of the diode is electrically connected to the second end of the reset pulse amplification unit, for making the first end of the diode a high-level first output signal when the reset pulse signal at the second end of the diode is a high pulse signal.

2. The circuit according to claim 1, characterized in that The voltage bias unit includes a first power supply and a first bias resistor, wherein the first power supply is a power supply with a constant voltage; wherein, The first power supply is used to provide a constant voltage to the first bias resistor; The first end of the first bias resistor is electrically connected to the first power supply, and the second end of the first bias resistor is electrically connected to the drain of the silicon carbide-based junction field effect transistor, and is used to adjust the bias current of the drain of the silicon carbide-based junction field effect transistor to provide a stable static operating point for the silicon carbide-based junction field effect transistor.

3. The circuit according to claim 1, characterized in that The signal output amplification module includes a charge sensitive amplification unit and a high pass filter unit; wherein, The signal output amplification module is electrically connected to the reset pulse signal generation module and includes: The first end of the charge-sensitive amplifier unit is electrically connected to the drain of the silicon carbide-based junction field effect transistor, and the second end of the charge-sensitive amplifier unit is electrically connected to the high-pass filter unit, for amplifying the first amplified signal to obtain a second amplified signal, and outputting the second amplified signal to the high-pass filter unit and the voltage comparison unit; The high-pass filtering unit is electrically connected to the charge-sensitive amplifying unit, and is used to perform high-pass filtering on the second amplified signal, and to amplify the signal after the high-pass filtering, so as to obtain and output the target signal.

4. The circuit according to claim 3, characterized in that The high-pass filter unit includes a high-pass filter sub-unit and a first operational amplifier; The high-pass filtering unit is electrically connected to the charge-sensitive amplifying unit, and includes: The first end of the high-pass filter subunit is electrically connected to the charge-sensitive amplifier unit, and the second end of the high-pass filter subunit is electrically connected to the input end of the first operational amplifier, for performing high-pass filtering on the second amplified signal to obtain a filtered signal; The input end of the first operational amplifier is electrically connected to the second end of the high-pass filter subunit, and the output end of the first operational amplifier outputs the target signal, which is used to amplify the filtered signal to obtain and output the target signal to an external circuit.

5. The circuit according to claim 1, characterized in that The voltage comparison unit includes a first bias subunit, a second bias subunit and a voltage comparator; wherein, The first end of the voltage comparison unit is electrically connected to the signal output amplification module, the second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: The first end of the first bias subunit is electrically connected to the second end of the charge-sensitive amplifier unit, the second end of the first bias subunit is grounded, and the third end of the first bias subunit is electrically connected to the same-direction input end of the voltage comparator, and is used to divide the second amplified signal output by the charge-sensitive amplifier unit to provide the voltage comparator with an input voltage to be compared; The first end of the second bias subunit is electrically connected to the second power supply, the second end of the second bias subunit is grounded, and the third end of the second bias subunit is electrically connected to the inverting input end of the voltage comparator, for providing a reference voltage to the inverting input end of the voltage comparator; The same-direction input terminal of the voltage comparator is electrically connected to the third terminal of the first bias subunit, the reverse input terminal of the voltage comparator is electrically connected to the third terminal of the second bias subunit, and the output terminal of the voltage comparator outputs a first control signal, which is used to output a first control signal of a high level to the reset pulse width modulation unit when the voltage of the same-direction input terminal is greater than the voltage of the reverse input terminal, and output a first control signal of a low level to the reset pulse width modulation unit when the voltage of the same-direction input terminal is less than the voltage of the reverse input terminal.

6. The circuit according to claim 1, characterized in that The reset pulse width modulation unit includes a rising edge D-type trigger, a timing resistor and a timing capacitor; wherein, The second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: The clock port of the rising edge D-type flip-flop is electrically connected to the output end of the voltage comparator, the data input port of the rising edge D-type flip-flop and the set port of the rising edge D-type flip-flop are electrically connected to the second power supply, and are used to maintain the high level input state of the data input port of the rising edge D-type flip-flop and the set port of the rising edge D-type flip-flop, the reset port of the rising edge D-type flip-flop is electrically connected to the first end of the timing capacitor, the forward output end of the rising edge D-type flip-flop is electrically connected to the reset pulse amplification unit, and the reverse output end of the rising edge D-type flip-flop is electrically connected to the first end of the timing resistor, and the clock port responds to receiving the high level first control signal, the forward output end outputs a high level reset pulse signal, and the reverse output end outputs a low level reverse pulse signal; The first end of the timing resistor is electrically connected to the reverse output end of the rising edge D-type flip-flop, and the second end of the timing resistor is electrically connected to the first end of the timing capacitor, so as to facilitate the timing capacitor to discharge to the timing resistor when the reverse output end outputs a low-level reverse pulse signal; The first end of the timing capacitor is electrically connected to the second end of the timing resistor, and the second end of the timing capacitor is grounded, and is used to discharge to the timing resistor when the reverse output end outputs a low-level reverse pulse signal to obtain a first voltage, and reset the rising-edge D-type trigger when the first voltage of the timing capacitor is less than the reset input voltage of the rising-edge D-type trigger.

7. The circuit according to claim 1, characterized in that The reset pulse amplifying unit includes a second operational amplifier and a third bias subunit; wherein, The second end of the voltage comparison unit is electrically connected to the first end of the reset pulse width modulation unit, and the second end of the reset pulse width modulation unit is electrically connected to the reset pulse amplification unit, including: The first end of the second operational amplifier is electrically connected to the first end of the third bias subunit, and the second end of the second operational amplifier is electrically connected to the second end of the diode, and is used to amplify the reset pulse signal to obtain a target reset pulse signal, and send the target reset pulse signal to the diode to turn on the diode, so as to reset the gate voltage of the silicon carbide-based junction field effect transistor.

8. A method for amplifying and resetting a data signal using the circuit according to any one of claims 1 to 7, characterized in that: include: The semiconductor radiation detector sends a first output signal to the signal input buffer module; The signal input buffer module amplifies the first output signal to obtain a first amplified signal; The signal input buffer module sends the first amplified signal to the signal output amplification module; The signal output amplification module amplifies and performs high-pass filtering on the first amplified signal to output a target signal.

9. The method according to claim 8, characterized in that The signal output amplification module includes a charge sensitive amplification unit and a high pass filtering unit; the method further includes: The charge-sensitive amplifier unit amplifies the first amplified signal to obtain a second amplified signal; The charge sensitive amplifier unit sends the second amplified signal to the reset pulse signal generating module; The reset pulse signal generating module compares the second amplified signal, and sends a target reset pulse signal to the signal input buffer module when the amplitude of the second amplified signal is greater than a predetermined threshold; The signal input buffer module resets the signal output amplification module according to the target reset pulse signal.

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