On-chip self-test system and method based on full digital domain

Abstract

The present application provides an on-chip self-test system and method based on a full digital domain. The on-chip self-test system based on the full digital domain is configured in a system-on-chip chip including at least one analog-to-digital converter and at least one digital-to-analog converter. The on-chip self-test system based on the full digital domain includes: a controller, a digital vector generator, a strobe adder and a code memory; the controller is electrically connected to the digital vector generator, the strobe adder and the code memory respectively; by integrating a built-in self-test system of the full digital domain, the system-on-chip chip can generate a test signal internally, and analyze the response signal through the built-in digital logic, thereby realizing accurate testing of the dynamic characteristics of ADC and DAC, with high test accuracy, without interrupting system operation or connecting external devices, significantly reducing the test cost, and can perform performance monitoring throughout the chip life cycle, avoiding complex analog test circuit design, and reducing the chip area occupied by the self-test system.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to an on-chip self-test system and method based on a full digital domain. Background Art

[0002] With the rapid development of semiconductor technology, mixed signal chips (chips that integrate analog and digital signal processing functions) are increasingly used in various fields, especially in key areas such as high-precision measurement, high-speed communication, and industrial automation. Among them, the performance of analog-to-digital converters (ADC-Analog-to-Digital Converter) and digital-to-analog converters (DAC-Digital-to-Analog Converter) as the core components of mixed signal chips directly determines the accuracy and efficiency of the entire system. At present, the world's most advanced high-precision ADC has a resolution of up to 32Bits and a sampling rate of 38KSPS; while the sampling rate of high-speed ADC can reach 10.4GSPS and a resolution of 12Bits. The resolution of high-precision DAC can reach 24Bits and a sampling rate of 256KSPS; while the resolution of high-speed DAC can reach 14Bits and a sampling rate of 12GSPS.

[0003] As the performance of mixed-signal chips improves, mass production testing faces the dual challenges of rising test costs and increasingly high test quality requirements. If these two challenges are not resolved, they will in turn seriously restrict the performance upgrade and market application of the chip itself. Therefore, research on mass production testing of mixed-signal chips is a necessary and significant industrial value field.

[0004] Traditionally, the testing of mixed-signal chips relies on automated test equipment (ATE-Automated Test Equipment), which has the following technical problems:

[0005] (1) Although this equipment is powerful, the testing cost is expensive. The cost of mass production testing of chips depends on two aspects: the testing time of a single chip and the fixed asset investment of the testing equipment. The circuit area ratio of the digital part to the analog part of a mixed-signal chip is generally more than seven to three, but the test time ratio is lower than three to seven because the dynamic and static characteristic testing of the analog part takes a long time. In addition, the cost of the mixed-signal ATE itself is more than twice that of the digital signal ATE, which puts pressure on the fixed asset investment of the testing plant. Its cost is also passed on to the chip testing cost, resulting in an increase in the overall chip cost. In addition, as chip performance improves, the frequency of test equipment updates and upgrades accelerates, further exacerbating the increase in testing costs.

[0006] (2) Limited test accuracy. As the performance of mixed-signal chips continues to break through, existing test equipment often has difficulty keeping up with their update speed. Even the latest and most advanced test equipment may have lags behind the chip under test in terms of ADC / DAC chip performance, so the sampling rate or effective number of bits is lower than that of the ADC / DAC chip under test, resulting in limited test accuracy. This performance mismatch problem is particularly prominent when testing high-speed, high-precision ADC / DAC chips, which seriously restricts the true evaluation of chip performance.

[0007] (3) It is impossible to ensure the performance of the chip throughout its life cycle. Existing testing methods mainly focus on functional and performance testing of hybrid chips before they leave the factory. Once the chip is integrated into a module or system board, it is difficult to conduct effective performance testing or self-testing, and there are limitations on the performance monitoring and self-testing of the chip during subsequent use. This is particularly critical in areas with high reliability requirements (such as industrial control, automotive electronics, aerospace, etc.). How to ensure the performance of mixed-signal chips is a challenge, because any performance degradation may lead to system failure or safety accidents.

[0008] In response to the above challenges, the industry has proposed a test solution based on BIST (built-in self-test). This solution integrates test modules (such as ramp signal generator, comparator, trigger cycle counter, etc.) inside the chip, realizing testing without external ATE equipment, thereby reducing test costs. However, this solution also has obvious limitations:

[0009] (1) Design complexity and area occupation: The design of the BIST module is complex, including analog circuits and digital circuits, and requires a large chip area, which increases the cost. This is a considerable challenge for application scenarios that pursue high integration and low cost.

[0010] (2) Limited test scope: Current BIST solutions mainly focus on static characteristic testing of ADC / DAC, but are unable to test dynamic characteristics. Summary of the invention

[0011] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide an on-chip self-test system and method based on the full digital domain, which is used to solve the technical problems in the prior art such as high cost of testing analog-to-digital converters and digital-to-analog converters, limited test accuracy, complex circuit design, large chip area and limited test range.

[0012] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an on-chip self-test system based on a full digital domain, which is configured in an on-chip system chip including at least one analog-to-digital converter and at least one digital-to-analog converter, and the on-chip self-test system based on the full digital domain includes: a controller, a digital vector generator, a gate adder and a code memory; the controller is electrically connected to the digital vector generator, the gate adder and the code memory respectively; when performing a dynamic characteristic test on the analog-to-digital converter and the digital-to-analog converter, the controller controls the digital vector generator to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received first digital code stream into a corresponding first analog signal and outputs it; the gate adder controls the first analog signal output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received first analog signal into a corresponding first digital signal and outputs it, The controller controls the code memory to be stored; the controller controls the digital vector generator to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received second digital code stream into a corresponding second analog signal and outputs it; the selection adder controls the second analog signal output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received second analog signal into a corresponding second digital signal and outputs it, and controls the code memory to be stored; the controller calculates and analyzes the first digital signal output by each of the analog-to-digital converters and the second digital signal output by each of the analog-to-digital converters stored in the code memory respectively, to obtain the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter, and compares the dynamic characteristic index value with the preset specification value to output the test result.

[0013] In some embodiments of the first aspect of the present application, the controller performs calculation and analysis on the first digital signals output by each of the analog-to-digital converters and the second digital signals output by each of the analog-to-digital converters stored in the code memory, respectively, to obtain the dynamic characteristic index values ​​corresponding to each analog-to-digital converter and the dynamic characteristic index values ​​corresponding to each digital-to-analog converter, including: the controller performs spectrum analysis on the first digital signals output by each of the analog-to-digital converters and the second digital signals output by each of the analog-to-digital converters stored in the code memory, respectively, to obtain the fundamental and harmonic components in the spectrum of the first waveform signal, the noise components in the spectrum of the first waveform signal, the fundamental and harmonic components in the spectrum of the second waveform signal, and the noise components in the spectrum of the second waveform signal; according to the fundamental and harmonic components in the spectrum of the first waveform signal , the noise component in the first waveform signal spectrum, the fundamental and harmonic components in the second waveform signal spectrum, and the noise component in the second waveform signal spectrum, calculate the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter; according to the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter, calculate the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter.

[0014] In some embodiments of the first aspect of the present application, the on-chip self-test system based on the all-digital domain also includes: a first multiplexing network and a second multiplexing network; the first multiplexing network is electrically connected to the input end of each of the digital-to-analog converters and the input end of each of the analog-to-digital converters, respectively; the second multiplexing network is electrically connected to the output end of each of the digital-to-analog converters and the output end of each of the analog-to-digital converters, respectively.

[0015] In some embodiments of the first aspect of the present application, the first multiplexer network includes multiple first multiplexers and multiple second multiplexers; each of the first multiplexers is electrically connected to the digital vector generator, each of the first multiplexers is electrically connected to the input end of the digital-to-analog converter, and controls whether to enable the first digital code stream and the second digital code stream to enter the correspondingly connected digital-to-analog converter; each of the second multiplexers is electrically connected to the enable adder, each of the second multiplexers is electrically connected to the input end of the analog-to-digital converter, and controls whether to enable the first analog signal and the second analog signal to enter the correspondingly connected analog-to-digital converter.

[0016] In some embodiments of the first aspect of the present application, the second multiplexing network includes multiple third multiplexers and multiple fourth multiplexers; each of the third multiplexers is electrically connected to the code memory, each of the third multiplexers is electrically connected to an output end of the analog-to-digital converter, and controls whether the output signal of the corresponding analog-to-digital converter is enabled to enter the code memory; each of the fourth multiplexers is electrically connected to the enable adder, each of the fourth multiplexers is electrically connected to an output end of the digital-to-analog converter, and controls whether the output signal of the corresponding digital-to-analog converter is enabled to enter the enable adder.

[0017] In some embodiments of the first aspect of the present application, when the dynamic characteristics test is performed on the analog-to-digital converter and the digital-to-analog converter, the controller controls the first multiplexing network and the second multiplexing network to switch to a self-test state; the first multiplexer controls the first digital code stream to enter the correspondingly connected digital-to-analog converter, the fourth multiplexer controls the first analog signal output by the correspondingly connected digital-to-analog converter to enter the selection adder, the selection adder controls the first analog signal to enter the second multiplexer, and the second multiplexer controls the first analog signal to enter the correspondingly connected analog-to-digital converter; the third multiplexer controls the first digital code stream to enter the correspondingly connected digital-to-analog converter; The multiplexer controls the first digital signal output by the corresponding analog-to-digital converter to enter the code memory for storage; the first multiplexer controls the second digital code stream to enter the corresponding digital-to-analog converter, the fourth multiplexer controls the second analog signal output by the corresponding digital-to-analog converter to enter the selection adder, the selection adder controls the second analog signal to enter the second multiplexer, and the second multiplexer controls the second analog signal to enter the corresponding analog-to-digital converter; the third multiplexer controls the second digital signal output by the corresponding analog-to-digital converter to enter the code memory for storage.

[0018] In some embodiments of the first aspect of the present application, the method of calculating the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter and the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter includes:

[0019] ;

[0020] ;

[0021] in, Represents the fundamental wave and harmonic components in the spectrum of the first waveform signal; Represents the fundamental wave and harmonic components in the spectrum of the second waveform signal; Represents the fundamental and harmonic components in the waveform spectrum of the digital-to-analog converter; Represents the fundamental and harmonic components in the waveform spectrum of the analog-to-digital converter; Indicates the order of harmonics.

[0022] In some embodiments of the first aspect of the present application, the dynamic characteristic index value includes a signal-to-noise ratio value; and the calculation method of the signal-to-noise ratio value includes:

[0023] ;

[0024] in, represents the signal-to-noise ratio value; Indicates the amplitude value of the fundamental component; Represents the amplitude value of the spectrum component at the i-th frequency point; Indicates the order of harmonics; M represents the fundamental spectrum component; N represents the number of waveform sampling points; Indicates the number of frequency points in the complete spectrum.

[0025] In some embodiments of the first aspect of the present application, the dynamic characteristic index value includes a total harmonic distortion value; and the calculation method of the total harmonic distortion value includes:

[0026] ;

[0027] in, Indicates the total harmonic distortion value; Indicates the amplitude value of the fundamental component; Indicates The amplitude value of the harmonic component of the order; R represents the harmonic order that needs to be paid attention to when calculating THD.

[0028] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an on-chip self-test method based on the full digital domain, which is applied to a system-on-chip chip including at least one analog-to-digital converter and at least one digital-to-analog converter, and the system-on-chip chip is configured with the on-chip self-test system based on the full digital domain as described above; the on-chip self-test method includes: when performing dynamic characteristic testing on the analog-to-digital converter and the digital-to-analog converter, the controller controls the digital vector generator to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received first digital code stream into a corresponding first analog signal and outputs it; the selection adder controls the first analog signal output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received first analog signal into a corresponding first digital signal and outputs it, and the controller controls the entry into the code memory The controller controls the digital vector generator to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received second digital code stream into a corresponding second analog signal and outputs it; the selection adder controls the second analog signal output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received second analog signal into a corresponding second digital signal and outputs it, and is controlled by the controller to enter the code memory for storage; the controller calculates and analyzes the first digital signal output by each of the analog-to-digital converters and the second digital signal output by each of the analog-to-digital converters stored in the code memory respectively, to obtain the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter, and compares the dynamic characteristic index value with the preset specification value to output the test result.

[0029] As described above, the on-chip self-test system and method based on the full digital domain in the present application has the following beneficial effects:

[0030] (1) By integrating a fully digital domain built-in self-test system, the SoC chip can generate digital test vectors internally and analyze the response signals through built-in digital logic, thereby achieving accurate testing of the dynamic characteristics of the analog-to-digital converter and the digital-to-analog converter. The test has high accuracy and completely eliminates the reliance on external ATE, significantly reducing the test cost. In addition, the fully digital domain-based SoC self-test system allows the test to be started at any stage of the operation of the SoC chip without interrupting the system operation or connecting external devices, so that the performance of the analog-to-digital converter and the digital-to-analog converter can be monitored at any time during the entire life cycle of the chip. Accurate measurement of dynamic characteristics can be achieved simply through software instructions, greatly improving the flexibility and convenience of testing.

[0031] (2) The on-chip self-test system based on the full digital domain in this application can perform dynamic performance testing on multiple groups of analog-to-digital converters and digital-to-analog converters integrated on the system-on-chip chip, achieving efficient test coverage and solving the problem of low efficiency in traditional testing methods that require testing each module separately.

[0032] (3) The on-chip self-test system based on the full digital domain in this application avoids complex analog circuit design, involves fewer electronic devices, reduces the occupied chip area, and reduces the noise, drift and other unstable factors introduced by the analog circuit. At the same time, the digital circuit has higher stability and reliability and can maintain consistent performance over a wider operating temperature range. In addition, the design, simulation and verification of digital circuits are also more mature and efficient, which helps to simplify the design process of the on-chip self-test system based on the full digital domain and improve the reliability and maintainability of the test system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It shows the principle structure diagram of the mixed signal chip ADC / DAC test in the prior art.

[0034] Figure 2 The schematic block diagram of the on-chip self-test system of the ADC / DAC combination in the prior art is shown.

[0035] Figure 3 Shown is a principle structural block diagram of an on-chip self-test system based on a full digital domain in one embodiment of the present application.

[0036] Figure 4 Shown is a principle structure diagram of an on-chip self-test system based on a full digital domain when performing a test in an embodiment of the present application.

[0037] Figure 5 It shows a principle structure diagram of an on-chip self-test system based on a full digital domain in an embodiment of the present application when it is working normally.

[0038] Figure 6 Shown is a flowchart of an on-chip self-test method based on the full digital domain in an embodiment of the present application.

[0039] Attachment number description

[0040] 100 On-Chip Self-Test System 101 Controller 102 Digital vector generator 103 Strobe Adder 104 Code Memory 105 First multiplex network 1051 First multiplexer 1052 Second multiplexer 106 Second multiplex network 1061 The third multiplexer 1062 Fourth Multiplexer 200 Digital to Analog Converter 300 Analog-to-digital converter DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0042] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0043] <1> ATE (Automatic Test Equipment): An electronic device used for automated testing of electronic components, circuit boards, integrated circuits, or entire electronic systems.

[0044] <2> BIST (Built-In Self-Test) is a technology for self-testing at the integrated circuit or system level. It embeds test logic and test programs inside the chip to achieve comprehensive testing of the chip's own functions, thereby improving the efficiency and reliability of the test.

[0045] <3> Digital bit stream: It is a series of discrete digital signals that represent the sampling and quantization results of the original analog signal (such as sound, image, etc.).

[0046] <4> FFT (Fast Fourier Transform): Fast Fourier transform is an efficient algorithm for calculating discrete Fourier transform and its inverse transform.

[0047] The testing of traditional mixed-signal chips relies on automated test equipment (ATE-Automated Test Equipment), such as Figure 1 As shown in Figure 1, there are problems such as high testing cost, limited testing accuracy, and inability to ensure chip performance throughout its life cycle. Although the industry has proposed a test solution based on BIST (built-in self-test), such as Figure 2 As shown. This solution integrates test modules (such as ramp signal generator, comparator, trigger cycle counter, etc.) inside the chip, realizing testing without external ATE equipment, thereby reducing test costs. However, this solution also has obvious limitations:

[0048] (1) Design complexity and area occupation: The design of the BIST module is complex, including analog circuits and digital circuits, and requires a large chip area, which increases the cost. This is a considerable challenge for application scenarios that pursue high integration and low cost.

[0049] (2) Limited test scope: Current BIST solutions mainly focus on static characteristic testing of ADC / DAC, but are unable to test dynamic characteristics.

[0050] In order to solve the problems in the above-mentioned background technology, the present invention provides an on-chip self-test system and method based on the full digital domain, which is used to solve the technical problems in the prior art such as high cost of testing analog-to-digital converters and digital-to-analog converters, limited test accuracy, complex circuit design, large chip area and limited test range.

[0051] To facilitate understanding of the embodiments of the present application, first Figure 3 Detailed description. Figure 3 The principle structural block diagram of the on-chip self-test system based on the full digital domain in the embodiment of the present invention is shown. The on-chip self-test system 100 based on the full digital domain is configured in a system-on-chip chip including at least one analog-to-digital converter 300 and at least one digital-to-analog converter 200. The on-chip self-test system 100 based on the full digital domain includes: a controller 101, a digital vector generator 102, a strobe adder 103 and a code memory 104; the controller 101 is electrically connected to the digital vector generator 102, the strobe adder 103 and the code memory 104 respectively. Among them, Figure 3-5 The mixed signal chip under test is a system-on-chip chip having multiple groups of analog-to-digital converters and digital-to-analog converters.

[0052] In this embodiment, when performing dynamic characteristic testing on the analog-to-digital converter and the digital-to-analog converter, the controller 101 controls the digital vector generator 102 to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters 200 respectively, and each of the digital-to-analog converters 200 converts the received first digital code stream into a corresponding first analog signal and outputs it.

[0053] In this embodiment, the selection adder 103 controls the first analog signal output by each of the digital-to-analog converters 200 to enter each of the analog-to-digital converters 300 respectively, and each of the analog-to-digital converters 300 converts the received first analog signal into a corresponding first digital signal and outputs it, which is controlled by the controller 101 to enter the code memory 104 for storage.

[0054] In this embodiment, the controller 101 controls the digital vector generator 102 to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters 200 respectively. Each of the digital-to-analog converters 200 converts the received second digital code stream into a corresponding second analog signal and outputs it.

[0055] In this embodiment, the selection adder controls the second analog signals output by each of the digital-to-analog converters 200 to enter each of the analog-to-digital converters 300 respectively, and each of the analog-to-digital converters 300 converts the received second analog signals into corresponding second digital signals and outputs them, which are controlled by the controller 101 to enter the code memory 104 for storage.

[0056] In this embodiment, the controller 101 calculates and analyzes the first digital signal output by each of the analog-to-digital converters 300 and the second digital signal output by each of the analog-to-digital converters 300 stored in the code memory 104, respectively, to obtain the dynamic characteristic index value corresponding to each analog-to-digital converter 300 and the dynamic characteristic index value corresponding to each digital-to-analog converter 200, and compares the dynamic characteristic index value with the preset specification value to output the test result.

[0057] In this embodiment, the controller 101 is electrically connected to the digital vector generator 102, the selection adder 103, and the code memory 104, respectively, and is used to control the digital vector generator 102 to output a digital signal, control the selection adder 103 to transmit the analog signal output by the digital-to-analog converter 200 to a designated output channel, and read the signal from the code memory 104 for dynamic test analysis.

[0058] In this embodiment, the first digital signal and the second digital signal output by the analog-to-digital converter 300 are selected and stored in the code memory 104. Since the first digital signal and the second digital signal output by the analog-to-digital converter 300 are generated based on the first analog signal and the second analog signal output by the digital-to-analog converter 200, by calculating and analyzing the first digital signal and the second digital signal stored in the code memory 104, the frequency spectrum characteristics of the waveform signal in each analog-to-digital converter 300 and the frequency spectrum characteristics of the waveform signal in each digital-to-analog converter 200 can be obtained, and then the dynamic characteristics of each analog-to-digital converter 300 and each digital-to-analog converter 200 can be analyzed.

[0059] In this embodiment, the on-chip self-test system 100 based on the full digital domain in this application is configured in a system-on-chip chip including at least one analog-to-digital converter 300 and at least one digital-to-analog converter 200. By integrating the built-in self-test system of the full digital domain, the system-on-chip chip can generate digital test vectors internally, and analyze the response signal through the built-in digital logic, thereby realizing accurate testing of the dynamic characteristics of the analog-to-digital converter and the digital-to-analog converter, with high test accuracy, completely eliminating the reliance on external ATE, and significantly reducing the test cost. In addition, the on-chip self-test system 100 based on the full digital domain allows the test to be started at any stage of the operation of the system-on-chip chip without interrupting the system operation or connecting external devices, so that the performance of the analog-to-digital converter and the digital-to-analog converter can be monitored at any time during the entire life cycle of the chip, and the accurate measurement of the dynamic characteristics can be realized only through software instructions, which greatly improves the flexibility and convenience of the test.

[0060] Furthermore, the on-chip self-test system 100 based on the all-digital domain in the present application can perform dynamic performance testing on multiple groups of analog-to-digital converters and digital-to-analog converters integrated on the system-on-chip chip, achieving efficient test coverage and solving the problem of low efficiency in traditional testing methods that require testing each module separately.

[0061] Furthermore, the on-chip self-test system 100 based on the full digital domain in the present application avoids complex analog circuit design, involves fewer electronic devices, reduces the chip area occupied, and reduces the unstable factors such as noise and drift introduced by the analog circuit. At the same time, the digital circuit has higher stability and reliability, and can maintain consistent performance within a wider operating temperature range. In addition, the design, simulation and verification of the digital circuit are also more mature and efficient, which helps to simplify the design process of the on-chip self-test system 100 based on the full digital domain and improve the reliability and maintainability of the test system.

[0062] In this embodiment, the on-chip self-test system 100 based on the all-digital domain also includes: a first multiplexing network 105 and a second multiplexing network 106; the first multiplexing network 105 is electrically connected to the input end of each of the digital-to-analog converters 200 and the input end of each of the analog-to-digital converters 300; the second multiplexing network 106 is electrically connected to the output end of each of the digital-to-analog converters 200 and the output end of each of the analog-to-digital converters 300.

[0063] In this embodiment, the first multiplexing network 105 includes a plurality of first multiplexers 1051 and a plurality of second multiplexers 1052. Each of the first multiplexers 1051 is electrically connected to the digital vector generator 102, and each of the first multiplexers 1051 is electrically connected to an input end of the digital-to-analog converter 200 to control whether to enable the first digital code stream and the second digital code stream to enter the corresponding digital-to-analog converter 200. Each of the second multiplexers 1052 is electrically connected to the selection adder 103, and each of the second multiplexers 1052 is electrically connected to an input end of the analog-to-digital converter 300 to control whether to enable the first analog signal and the second analog signal to enter the corresponding analog-to-digital converter 300. The number of the first multiplexers 1051 and the number of the fourth multiplexers 1062 are the same as the number of the digital-to-analog converters 200, and each digital-to-analog converter 200 is connected to a first multiplexer 1051 and a fourth multiplexer 1062. The number of the second multiplexers 1052 and the number of the third multiplexers 1061 are the same as the number of the analog-to-digital converters 300, and each analog-to-digital converter 300 is connected to a second multiplexer 1052 and a third multiplexer 1061.

[0064] In this embodiment, one input terminal of the first multiplexer 1051 is connected to an input terminal of the DAC outside the chip when the DAC is working normally, one input terminal is connected to an output terminal of the digital vector generator 102, and the output terminal of the first multiplexer 1051 is connected to the digital-to-analog converter 200. One input terminal of the second multiplexer 1052 is connected to an input terminal of the ADC outside the chip when the ADC is working normally, one input terminal is connected to an output terminal of the selection adder 103, and the output terminal of the second multiplexer 1052 is connected to the analog-to-digital converter 300.

[0065] In this embodiment, when the analog-to-digital converter 300 and the digital-to-analog converter 200 are not tested, the input end of the first multiplexer 1051 is selected to be connected to the input end outside the chip when the DAC is working normally, that is, the first multiplexer 1051 is controlled to select the digital-to-analog signal (DAC) outside the chip to be input to the corresponding digital-to-analog converter 200; the input end of the second multiplexer 1052 is selected to be connected to the input end outside the chip when the ADC is working normally, that is, the second multiplexer 1052 is controlled to select the analog-to-digital signal (ADC) outside the chip to be input to the corresponding analog-to-digital converter 300.

[0066] In this embodiment, when testing the analog-to-digital converter 300 and the digital-to-analog converter 200, the controller 101 controls the first multiplexing network 105 and the second multiplexing network 106 to switch to a self-test state, and the input end of the first multiplexer 1051 is selected to be connected with the digital vector generator 102, that is, the first multiplexer 1051 is controlled to select the first digital code stream and the second digital code stream output by the digital vector generator 102 to enter the correspondingly connected digital-to-analog converter 200; the input end of the second multiplexer 1052 is selected to be connected with the selection adder 103, that is, the second multiplexer 1052 is controlled to select the first analog signal and the second analog signal to enter the correspondingly connected analog-to-digital converter 300.

[0067] In this embodiment, the second multiplexing network 106 includes multiple third multiplexers 1061 and multiple fourth multiplexers 1062; each of the third multiplexers 1061 is electrically connected to the code memory 104, and each of the third multiplexers 1061 is electrically connected to an output end of the analog-to-digital converter 300 to control whether the output signal of the corresponding analog-to-digital converter 300 is enabled to enter the code memory 104; each of the fourth multiplexers 1062 is electrically connected to the selection adder 103, and each of the fourth multiplexers 1062 is electrically connected to an output end of the digital-to-analog converter 200 to control whether the output signal of the corresponding digital-to-analog converter is enabled to enter the selection adder 103.

[0068] In this embodiment, the input end of the third multiplexer 1061 is connected to the output end of the analog-to-digital converter 300, one output end of the third multiplexer 1061 is connected to the code memory 104, and one output end is connected to the output end of the ADC when the ADC is working normally. The input end of the fourth multiplexer 1062 is connected to the output end of the digital-to-analog converter 200, one output end of the fourth multiplexer 1062 is connected to the selection adder 103, and one output end is connected to the output end of the DAC when the DAC is working normally.

[0069] In this embodiment, when the analog-to-digital converter 300 and the digital-to-analog converter 200 are not tested, the output end of the third multiplexer 1061 is selected to be connected to the output end outside the chip when the ADC is working normally, that is, the third multiplexer 1061 is controlled to select the output signal of the corresponding analog-to-digital converter 300 to be output to the outside of the chip; the output end of the fourth multiplexer 1062 is selected to be connected to the output end outside the chip when the DAC is working normally, that is, the fourth multiplexer 1062 is controlled to select the output signal of the corresponding digital-to-analog converter 200 to be output to the outside of the chip.

[0070] In this embodiment, when testing the analog-to-digital converter 300 and the digital-to-analog converter 200, the controller 101 controls the first multiplexing network 105 and the second multiplexing network 106 to switch to a self-test state, and the output end of the third multiplexer 1061 is selected to be connected to the code memory 104, that is, the third multiplexer 1061 is controlled to select the first digital signal and the second digital signal output by the corresponding analog-to-digital converter 300 to enter the code memory 104 for storage; the output end of the fourth multiplexer 1062 is selected to be connected to the selection adder 103, that is, the fourth multiplexer 1062 is controlled to select the first analog signal and the second analog signal output by the corresponding digital-to-analog converter 200 to enter the selection adder 103, and the selection adder 103 transmits the first analog signal and the second analog signal output by the digital-to-analog converter 200 to the designated output channel.

[0071] In this embodiment, if Figure 4 As shown, it is a principle structure diagram of the on-chip self-test system based on the full digital domain when testing in an embodiment of the present invention. When the dynamic characteristics test is performed on the analog-to-digital converter and the digital-to-analog converter, the controller 101 controls the first multiplexing network 105 and the second multiplexing network 106 to switch to the self-test state; the first multiplexer 1051 controls the first digital code stream to enter the correspondingly connected digital-to-analog converter 200, the fourth multiplexer 1062 controls the first analog signal output by the correspondingly connected digital-to-analog converter 200 to enter the selection adder 103, the selection adder 103 controls the first analog signal to enter the second multiplexer 1052, and the second multiplexer 1052 controls the first analog signal to enter the correspondingly connected analog-to-digital converter 300; the third multiplexer 1061 controls the correspondingly connected The first digital signal output by the analog-to-digital converter 300 enters the code memory 104 for storage; the first multiplexer 1051 controls the second digital code stream to enter the correspondingly connected digital-to-analog converter 200, the fourth multiplexer 1062 controls the second analog signal output by the correspondingly connected digital-to-analog converter 200 to enter the selection adder 103, the selection adder 103 controls the second analog signal to enter the second multiplexer 1052, and the second multiplexer 1052 controls the second analog signal to enter the correspondingly connected analog-to-digital converter 300; the third multiplexer 1061 controls the second digital signal output by the correspondingly connected analog-to-digital converter to enter the code memory 104 for storage.

[0072] In this embodiment, the controller 101 calculates and analyzes the first digital signal output by each analog-to-digital converter and the second digital signal output by each analog-to-digital converter stored in the code memory 104, and obtains the dynamic characteristic index value corresponding to each analog-to-digital converter 300 and the dynamic characteristic index value corresponding to each digital-to-analog converter 200 in a manner including:

[0073] (1) The controller 101 performs spectrum analysis on the first digital signals output by each of the analog-to-digital converters and the second digital signals output by each of the analog-to-digital converters stored in the code memory 104, respectively, to obtain the fundamental and harmonic components in the spectrum of the first waveform signal, the noise component in the spectrum of the first waveform signal, the fundamental and harmonic components in the spectrum of the second waveform signal, and the noise component in the spectrum of the second waveform signal.

[0074] In this embodiment, the controller 101 performs spectrum analysis on the first digital signal and the second digital signal stored in the code memory 104, and obtains the complete spectrum of the first waveform signal and the complete spectrum of the second waveform signal through fast Fourier transform (FFT), and the complete spectrum includes fundamental wave and harmonic components, noise components, etc. Among them, the fundamental wave and harmonic components in the spectrum of the first waveform signal are set as , the noise component in the first waveform signal spectrum is set to ; The fundamental and harmonic components in the second waveform signal spectrum are set to , the noise component in the second waveform signal spectrum is set to . Indicates the order of harmonics, which is a preset value. The preset value is determined according to the specific specifications of the chip. For example, it can be set to k=5~10. When k=1, it is the fundamental component, and when k>1, it is the harmonic component. The noise component of the measured digital-to-analog converter and analog-to-digital converter can be set to the arithmetic mean of the noise component in the first waveform signal spectrum and the noise component in the second waveform signal spectrum because the amplitude is very small compared to the fundamental wave and harmonics:

[0075] ; Formula (I)

[0076] in, Represents the noise component of the ith frequency point of the analog-to-digital converter; Represents the noise component of the digit-to-analog converter at the i-th frequency point; represents the noise component in the spectrum of the first waveform signal; represents the noise component in the spectrum of the second waveform signal; N represents the number of waveform sampling points; represents the order of harmonics, and M represents the fundamental spectral component.

[0077] (2) Calculate the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter based on the fundamental and harmonic components in the spectrum of the first waveform signal, the noise component in the spectrum of the first waveform signal, the fundamental and harmonic components in the spectrum of the second waveform signal, and the noise component in the spectrum of the second waveform signal.

[0078] In this embodiment, the method of calculating the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter and the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter includes:

[0079] ; Formula (II)

[0080] ; Formula (III)

[0081] in, Represents the fundamental wave and harmonic components in the spectrum of the first waveform signal; Represents the fundamental wave and harmonic components in the spectrum of the second waveform signal; Represents the fundamental and harmonic components in the waveform spectrum of the digital-to-analog converter; Represents the fundamental and harmonic components in the waveform spectrum of the analog-to-digital converter; Indicates the order of harmonics.

[0082] In this embodiment, the fundamental wave and harmonic components in the spectrum of the first waveform signal are set to , the fundamental and harmonic components in the second waveform signal spectrum are set to are all known quantities. By solving the equations of formula (II) and formula (III), we can calculate , , in order to obtain the spectral characteristics of the analog-to-digital converter and the digital-to-analog converter respectively.

[0083] (3) Based on the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter, calculate the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter.

[0084] In this embodiment, the dynamic characteristic index value includes a signal-to-noise ratio value; and the calculation method of the signal-to-noise ratio value includes:

[0085] ; Formula (IV)

[0086] in, represents the signal-to-noise ratio value; Indicates the amplitude value of the fundamental component; Represents the amplitude value of the spectrum component at the i-th frequency point; Indicates the order of harmonics; M represents the fundamental spectrum component; N represents the number of waveform sampling points; Indicates the number of frequency points in the complete spectrum.

[0087] In this embodiment, the signal-to-noise ratio (SNR) is the power ratio of the baseband signal to the noise. The signal and the noise must be sampled at the same or equivalent point and must be in the same system bandwidth. If the signal and the noise are measured through the same impedance, the signal-to-noise ratio can be obtained by calculating the square of the signal amplitude ratio, which is usually expressed in logarithmic decibels, as shown in formula (IV).

[0088] In this embodiment, the fundamental wave and harmonic components in the waveform spectrum of the analog-to-digital converter and the fundamental wave and harmonic components in the waveform spectrum of the digital-to-analog converter are calculated according to formula (II) and formula (III). If the number of waveform sampling points N=1024, it means that 1024 points are sampled, and then the spectrum is obtained through fast Fourier transform (FFT). The spectrum has 512 bins, bin=0~511, where bin=0 is the DC component, which is eliminated in the calculation. represents the amplitude value of the spectrum component at the i-th frequency point, including the amplitude value of the spectrum component at the harmonic frequency point and the amplitude value of the spectrum component at the non-harmonic frequency point. hour, Indicates the amplitude value of the spectrum component of the harmonic frequency point, k=1, 2, 3..., k=1 is the fundamental component, k=2 is the second-order harmonic component, k=3 is the third-order harmonic component, and so on. hour, The amplitude value of the spectrum component representing the non-harmonic frequency point (also called the noise component), that is, in the complete spectrum, except for the fundamental component, harmonic component, and DC component bin=0, all other components belong to the non-harmonic component, also called the noise component. Therefore, according to the above formula (IV), the signal-to-noise ratio value can be calculated.

[0089] In this embodiment, the dynamic characteristic index value includes a total harmonic distortion value; the calculation method of the total harmonic distortion value includes:

[0090] ; Formula (V)

[0091] in, Indicates the total harmonic distortion value; Indicates the amplitude value of the fundamental component; Indicates The amplitude value of the harmonic component of the order; R represents the harmonic order that needs to be paid attention to when calculating THD.

[0092] In this embodiment, the total harmonic distortion value (THD) is the ratio of the sum of all harmonic powers to the fundamental signal power. The total harmonic distortion value is often used to describe the linearity of analog systems and the power quality of power supply systems. In actual test environments, it is impossible to measure an infinite number of harmonic components, so R is usually set as the number of harmonic components included in the total harmonic distortion value THD calculation. Similar to the signal-to-noise ratio value, the total harmonic distortion value THD is usually expressed in logarithmic decibels, as shown in formula (V).

[0093] In this embodiment, the calculated signal-to-noise ratio value and total harmonic distortion value are compared with the preset specification value. If the dynamic characteristic index value is within the preset specification value range, the controller 101 outputs a test pass (PASS). If the dynamic characteristic index value is not within the preset specification value range, the controller 101 outputs a test fail (FAIL).

[0094] In this embodiment, the overall process of performing dynamic characteristic test on the analog-to-digital converter and the digital-to-analog converter is described:

[0095] (1) The controller 101 controls the first multiplexing network 105 and the second multiplexing network 106 to switch to a self-test state.

[0096] (2) The controller 101 controls the digital vector generator 102 to generate a first digital code stream. The first digital code stream .

[0097] (3) The first multiplexer 1051 controls the first digital code stream to enter the correspondingly connected digital-to-analog converter 200, and the digital-to-analog converter 200 converts the received first digital code stream into a corresponding first analog signal and outputs it. The fourth multiplexer 1062 controls the first analog signal output by the correspondingly connected digital-to-analog converter 200 to enter the input end of the gate adder 103. The gate adder 103 is used to connect the input signal to the specified output channel.

[0098] (4) The selection adder 103 controls the first analog signal to enter the second multiplexer 1052, and the second multiplexer 1052 controls the first analog signal to enter the corresponding analog-to-digital converter 300. The analog-to-digital converter 300 converts the received first analog signal into a corresponding first digital signal and outputs it. The third multiplexer 1061 controls the first digital signal output by the corresponding analog-to-digital converter 300 to enter the code memory 104 for storage.

[0099] (5) The controller 101 controls the digital vector generator 102 to generate a second digital code stream. The second digital code stream ;in, represents the independent variable, the discretized time; A is the signal amplitude; It is pi.

[0100] (6) The first multiplexer 1051 controls the second digital code stream to enter the correspondingly connected digital-to-analog converter 200, and the digital-to-analog converter 200 converts the received second digital code stream into a corresponding second analog signal and outputs it. The fourth multiplexer 1062 controls the correspondingly connected second analog signal output by the digital-to-analog converter 200 to enter the input end of the selection adder 103.

[0101] (7) The selection adder 103 controls the second analog signal to enter the second multiplexer 1052, and the second multiplexer 1052 controls the second analog signal to enter the correspondingly connected analog-to-digital converter 300. The analog-to-digital converter 300 converts the received second analog signal into a corresponding second digital signal and outputs it. The third multiplexer 1061 controls the second digital signal output by the correspondingly connected analog-to-digital converter to enter the code memory 104 for storage.

[0102] (8) The controller performs spectrum analysis on the first digital signals output by each analog-to-digital converter and the second digital signals output by each analog-to-digital converter stored in the code memory, respectively, to obtain the fundamental wave and harmonic components in the spectrum of the first waveform signal, the noise component in the spectrum of the first waveform signal, the fundamental wave and harmonic components in the spectrum of the second waveform signal, and the noise component in the spectrum of the second waveform signal. The fundamental wave and harmonic components in the spectrum of the first waveform signal and the fundamental wave and harmonic components in the spectrum of the second waveform signal both include: signal amplitude, frequency and initial phase.

[0103] (9) Calculate the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter based on the fundamental and harmonic components in the first waveform signal spectrum, the noise component in the first waveform signal spectrum, the fundamental and harmonic components in the second waveform signal spectrum, and the noise component in the second waveform signal spectrum.

[0104] (10) Based on the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter, the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter are calculated.

[0105] (11) Compare the dynamic characteristic index value with the preset specification value to output the test result.

[0106] In this embodiment, if the dynamic characteristic index value is within the preset specification value range, the controller 101 outputs a test pass (PASS). If the dynamic characteristic index value is not within the preset specification value range, the controller 101 outputs a test fail (FAIL).

[0107] In this embodiment, if Figure 5 As shown, it is a principle structure diagram of the on-chip self-test system based on the full digital domain in the embodiment of the present invention when it is working normally. When working normally, the controller 101 controls the first multiplexing network 105 and the second multiplexing network 106 to switch to a normal working state, the input end of the first multiplexer 1051 is selected to be connected to the input end outside the chip when the DAC is working normally, that is, the first multiplexer 1051 is controlled to select the digital-to-analog signal (DAC) outside the chip to be input into the corresponding digital-to-analog converter 200, and the output end of the fourth multiplexer 1062 is selected to be connected to the output end outside the chip when the DAC is working normally, that is, the output signal of the corresponding digital-to-analog converter 200 is controlled to be output to the outside of the chip. The input end of the second multiplexer 1052 is selected to be connected to the input end outside the chip when the ADC is working normally, that is, the second multiplexer 1052 is controlled to select the analog-to-digital signal (ADC) outside the chip to be input into the correspondingly connected analog-to-digital converter 300, and the output end of the third multiplexer 1061 is selected to be connected to the output end outside the chip when the ADC is working normally, that is, the third multiplexer 1061 is controlled to select the output signal of the correspondingly connected analog-to-digital converter 300 to be output outside the chip.

[0108] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first multiplexer and the second multiplexer are only used to distinguish different multiplexers, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0109] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0110] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0111] Figure 6 FIG. 1 is a flow chart of an on-chip self-test method based on a full digital domain provided by an embodiment of the present application. Figure 6 As shown, the on-chip self-test method based on the full digital domain is applied to a system-on-chip chip including at least one analog-to-digital converter and at least one digital-to-analog converter, and the system-on-chip chip is configured with the on-chip self-test system based on the full digital domain as described above; the on-chip self-test method comprises:

[0112] S601: When performing dynamic characteristic test on the analog-to-digital converter and the digital-to-analog converter, the controller controls the digital vector generator to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received first digital code stream into a corresponding first analog signal and outputs it.

[0113] S602: The selection adder controls the first analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively. Each of the analog-to-digital converters converts the received first analog signal into a corresponding first digital signal and outputs it. The controller controls the first analog signal to enter the code memory for storage.

[0114] S603: The controller controls the digital vector generator to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters respectively. Each of the digital-to-analog converters converts the received second digital code stream into a corresponding second analog signal and outputs it.

[0115] S604: The selection adder controls the second analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received second analog signals into corresponding second digital signals and outputs them, which are controlled by the controller to enter the code memory for storage.

[0116] S605: The controller calculates and analyzes the first digital signal output by each of the analog-to-digital converters and the second digital signal output by each of the analog-to-digital converters stored in the code memory, respectively, to obtain the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter, and compares the dynamic characteristic index value with the preset specification value to output the test result.

[0117] Since the implementation principle of the on-chip self-test method based on the full digital domain in this embodiment is substantially the same as the principle of the on-chip self-test system based on the full digital domain, the common technical contents between the principles will not be repeated.

[0118] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0119] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0121] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0124] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0125] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0126] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0127] In summary, the present application provides an on-chip self-test system and method based on a full digital domain. By integrating a built-in self-test system of a full digital domain, dynamic performance tests can be performed on multiple groups of analog-to-digital converters and digital-to-analog converters integrated on a system-on-chip chip, achieving efficient test coverage. The system-on-chip chip can generate digital test vectors internally, and analyze the response signal through built-in digital logic, thereby realizing accurate testing of the dynamic characteristics of the analog-to-digital converter and the digital-to-analog converter, with high test accuracy, completely eliminating the reliance on external ATE, and significantly reducing the test cost. And the on-chip self-test system based on the full digital domain allows the test to be started at any stage of the operation of the system-on-chip chip without interrupting the system operation or connecting external devices, so that the performance of the analog-to-digital converter and the digital-to-analog converter can be monitored at any time during the entire life cycle of the chip. The on-chip self-test system based on the full digital domain in the present application is a full digital circuit, which avoids complex analog circuit design, involves fewer electronic devices, reduces the occupied chip area, and reduces the noise, drift and other unstable factors introduced by the analog circuit. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0128] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An on-chip self-test system based on a full digital domain, characterized in that: The on-chip self-test system based on the full digital domain is configured in a system-on-chip chip including at least one analog-to-digital converter and at least one digital-to-analog converter, and comprises: a controller, a digital vector generator, a strobe adder, and a code memory; the controller is electrically connected to the digital vector generator, the strobe adder, and the code memory respectively; When the dynamic characteristics test is performed on the analog-to-digital converter and the digital-to-analog converter, the controller controls the digital vector generator to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received first digital code stream into a corresponding first analog signal and outputs it; The gate adder controls the first analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received first analog signals into corresponding first digital signals and outputs them, which are controlled by the controller to enter the code memory for storage; The controller controls the digital vector generator to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received second digital code stream into a corresponding second analog signal and outputs the second analog signal; The gate adder controls the second analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received second analog signals into corresponding second digital signals and outputs them, which are controlled by the controller to enter the code memory for storage; The controller calculates and analyzes the first digital signal output by each analog-to-digital converter and the second digital signal output by each analog-to-digital converter stored in the code memory, respectively, to obtain the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter, and compares the dynamic characteristic index value with the preset specification value to output the test result; wherein the method of obtaining the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter includes: The controller performs spectrum analysis on the first digital signals output by each of the analog-to-digital converters and the second digital signals output by each of the analog-to-digital converters stored in the code memory, respectively, to obtain the fundamental wave and harmonic components in the spectrum of the first waveform signal, the noise component in the spectrum of the first waveform signal, the fundamental wave and harmonic components in the spectrum of the second waveform signal, and the noise component in the spectrum of the second waveform signal; Calculate the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter based on the fundamental and harmonic components in the first waveform signal spectrum, the noise component in the first waveform signal spectrum, the fundamental and harmonic components in the second waveform signal spectrum, and the noise component in the second waveform signal spectrum; According to the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter, the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter are calculated; Methods for calculating the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter and the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter include: in, Represents the fundamental wave and harmonic components in the spectrum of the first waveform signal; Represents the fundamental wave and harmonic components in the spectrum of the second waveform signal; Represents the fundamental and harmonic components in the waveform spectrum of the digital-to-analog converter; Represents the fundamental wave and harmonic components in the waveform spectrum of the analog-to-digital converter; k represents the order of the harmonic; The dynamic characteristic index value includes a signal-to-noise ratio value; the calculation method of the signal-to-noise ratio value includes: Among them, SNR dB represents the signal-to-noise ratio value; Indicates the amplitude value of the fundamental component; represents the amplitude value of the spectrum component at the i-th frequency point; k represents the order of the harmonic; M represents the fundamental spectrum component; N represents the number of waveform sampling points; bin represents the number of frequency points in the complete spectrum; The dynamic characteristic index value includes a total harmonic distortion value; the calculation method of the total harmonic distortion value includes: Among them, THD dB Indicates the total harmonic distortion value; Indicates the amplitude value of the fundamental component; Represents the amplitude value of the r-th order harmonic component; R represents the harmonic order that needs to be paid attention to when calculating THD.

2. The on-chip self-test system based on the full digital domain according to claim 1, characterized in that: The on-chip self-test system based on the all-digital domain also includes: a first multiplexing network and a second multiplexing network; the first multiplexing network is electrically connected to the input end of each of the digital-to-analog converters and the input end of each of the analog-to-digital converters respectively; the second multiplexing network is electrically connected to the output end of each of the digital-to-analog converters and the output end of each of the analog-to-digital converters respectively.

3. The on-chip self-test system based on the all-digital domain according to claim 2, characterized in that: The first multiplexing network includes a plurality of first multiplexers and a plurality of second multiplexers; Each of the first multiplexers is electrically connected to the digital vector generator, and each of the first multiplexers is electrically connected to an input end of the digital-to-analog converter to control whether to select the first digital code stream and the second digital code stream to enter the correspondingly connected digital-to-analog converter; Each of the second multiplexers is electrically connected to the selection adder, and each of the second multiplexers is electrically connected to an input end of the analog-to-digital converter to control whether to select the first analog signal and the second analog signal to enter the correspondingly connected analog-to-digital converter.

4. The on-chip self-test system based on the full digital domain according to claim 3, characterized in that: The second multiplexing network includes a plurality of third multiplexers and a plurality of fourth multiplexers; Each of the third multiplexers is electrically connected to the code memory, and each of the third multiplexers is electrically connected to an output end of the analog-to-digital converter to control whether to enable the output signal of the corresponding analog-to-digital converter to enter the code memory; Each of the fourth multiplexers is electrically connected to the selection adder, and each of the fourth multiplexers is electrically connected to an output end of the digital-to-analog converter to control whether to select the output signal of the correspondingly connected digital-to-analog converter to enter the selection adder.

5. The on-chip self-test system based on the full digital domain according to claim 4, characterized in that: When the analog-to-digital converter and the digital-to-analog converter are subjected to a dynamic characteristic test, the controller controls the first multiplexing network and the second multiplexing network to switch to a self-test state; The first multiplexer controls the first digital code stream to enter the correspondingly connected digital-to-analog converter, the fourth multiplexer controls the first analog signal output by the correspondingly connected digital-to-analog converter to enter the gate adder, the gate adder controls the first analog signal to enter the second multiplexer, and the second multiplexer controls the first analog signal to enter the correspondingly connected analog-to-digital converter; The third multiplexer controls the first digital signal output by the corresponding analog-to-digital converter to enter the code memory for storage; The first multiplexer controls the second digital code stream to enter the correspondingly connected digital-to-analog converter, the fourth multiplexer controls the second analog signal output by the correspondingly connected digital-to-analog converter to enter the gate adder, the gate adder controls the second analog signal to enter the second multiplexer, and the second multiplexer controls the second analog signal to enter the correspondingly connected analog-to-digital converter; The third multiplexer controls the second digital signal output by the corresponding analog-to-digital converter to enter the code memory for storage.

6. An on-chip self-test method based on the full digital domain, characterized in that: Applicable to a system-on-chip chip comprising at least one analog-to-digital converter and at least one digital-to-analog converter, wherein the system-on-chip chip is configured with an on-chip self-test system based on a full digital domain as claimed in any one of claims 1 to 5; The on-chip self-test method comprises: When the dynamic characteristics test is performed on the analog-to-digital converter and the digital-to-analog converter, the controller controls the digital vector generator to generate a first digital code stream, and controls the first digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received first digital code stream into a corresponding first analog signal and outputs it; The gate adder controls the first analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received first analog signals into corresponding first digital signals and outputs them, which are controlled by the controller to enter the code memory for storage; The controller controls the digital vector generator to generate a second digital code stream, and controls the second digital code stream to enter each of the digital-to-analog converters respectively, and each of the digital-to-analog converters converts the received second digital code stream into a corresponding second analog signal and outputs the second analog signal; The gate adder controls the second analog signals output by each of the digital-to-analog converters to enter each of the analog-to-digital converters respectively, and each of the analog-to-digital converters converts the received second analog signals into corresponding second digital signals and outputs them, which are controlled by the controller to enter the code memory for storage; The controller calculates and analyzes the first digital signals output by each analog-to-digital converter and the second digital signals output by each analog-to-digital converter stored in the code memory, respectively, to obtain the dynamic characteristic index values ​​corresponding to each analog-to-digital converter and the dynamic characteristic index values ​​corresponding to each digital-to-analog converter, and compares the dynamic characteristic index values ​​with preset specification values ​​to output test results; The method of obtaining the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter includes: The controller performs spectrum analysis on the first digital signals output by each of the analog-to-digital converters and the second digital signals output by each of the analog-to-digital converters stored in the code memory, respectively, to obtain the fundamental wave and harmonic components in the spectrum of the first waveform signal, the noise component in the spectrum of the first waveform signal, the fundamental wave and harmonic components in the spectrum of the second waveform signal, and the noise component in the spectrum of the second waveform signal; Calculate the fundamental and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter based on the fundamental and harmonic components in the first waveform signal spectrum, the noise component in the first waveform signal spectrum, the fundamental and harmonic components in the second waveform signal spectrum, and the noise component in the second waveform signal spectrum; According to the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter, the noise component in the waveform spectrum corresponding to each analog-to-digital converter, the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter, and the noise component in the waveform spectrum corresponding to each digital-to-analog converter, the dynamic characteristic index value corresponding to each analog-to-digital converter and the dynamic characteristic index value corresponding to each digital-to-analog converter are calculated; Methods for calculating the fundamental wave and harmonic components in the waveform spectrum corresponding to each analog-to-digital converter and the fundamental wave and harmonic components in the waveform spectrum corresponding to each digital-to-analog converter include: in, Represents the fundamental wave and harmonic components in the spectrum of the first waveform signal; Represents the fundamental wave and harmonic components in the spectrum of the second waveform signal; Represents the fundamental and harmonic components in the waveform spectrum of the digital-to-analog converter; Represents the fundamental wave and harmonic components in the waveform spectrum of the analog-to-digital converter; k represents the order of the harmonic; The dynamic characteristic index value includes a signal-to-noise ratio value; the calculation method of the signal-to-noise ratio value includes: Among them, SNR dB represents the signal-to-noise ratio value; Indicates the amplitude value of the fundamental component; represents the amplitude value of the spectrum component at the i-th frequency point; k represents the order of the harmonic; M represents the fundamental spectrum component; N represents the number of waveform sampling points; bin represents the number of frequency points in the complete spectrum; The dynamic characteristic index value includes a total harmonic distortion value; the calculation method of the total harmonic distortion value includes: Among them, THD dB Indicates the total harmonic distortion value; Indicates the amplitude value of the fundamental component; Represents the amplitude of the r-th order harmonic component; R represents the harmonic order that needs to be paid attention to when calculating THD.

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