Data transmission method, device, chip and electronic device for multi-core system-level chip

Abstract

The present application relates to the field of chips, and provides a data transmission method, device, chip and electronic device for a multi-core system-level chip, which is mainly used to solve the following technical problems: the usage relationship between each DMA channel and the CPU is relatively chaotic, the data transmission efficiency is low, and the number of configuration registers used by the DMA channel is large, which limits the overall size of the chip. The chip of the present application includes multiple CPUs and DMA controllers; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of multiple DMA channels is stored together in a configuration information storage unit; a DMA channel is allocated to a CPU for use. The present application allocates a corresponding DMA channel to each CPU, the usage relationship is clear, and the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reducing the storage area occupancy rate on the DMA controller and reducing the size of the DMA controller.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a data transmission method, device, chip and electronic device for a multi-core system-level chip. Background Art

[0002] DMA (Direct Memory Access) is a chip design technology used to achieve high-speed data transfer between devices. It allows peripheral devices (such as hard disks, network cards, etc.) to directly access main memory without the intervention of the CPU (Central Processing Unit).

[0003] The chip integrates a DMA controller, which is the core of DMA transmission. The DMA controller is responsible for managing all stages of DMA transmission, including initialization, data transmission, interrupt processing, etc. It usually contains multiple channels, each of which can independently perform data transmission.

[0004] However, when the DMA controller of the existing chip manages the DMA channels, there are a large number of DMA channels, the usage relationship between each DMA channel and the CPU is relatively chaotic, the data transmission efficiency is low, and each DMA channel is correspondingly provided with a configuration register. The number of configuration registers is large, which occupies a large area of ​​the DMA controller, thereby affecting the overall size of the chip, limiting the overall size of the chip, and affecting the overall performance of the chip. Summary of the invention

[0005] In view of this, the embodiments of the present application propose a data transmission method, device, chip and electronic device for a multi-core system-level chip to solve the following problems in the prior art: the usage relationship between each DMA channel and the CPU is relatively chaotic, the data transmission efficiency is low, and each DMA channel is correspondingly provided with a configuration register. The number of configuration registers is large, which occupies a large area of ​​the DMA controller, thereby affecting the overall size of the chip, limiting the overall size of the chip, and affecting the overall performance of the chip.

[0006] On the one hand, an embodiment of the present application proposes a data transmission method for a multi-core system-level chip, wherein the multi-core system-level chip includes: multiple central processing units (CPUs) and direct memory access (DMA) controllers; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored together in a configuration information storage unit; a DMA channel is allocated to a CPU for use, and a CPU is configured with one or more DMA channels, and the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; the data transmission method includes: receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of the multiple hard-isolated DMA channels in the DMA controller; in response to the data transmission request of the first DMA channel, reading the configuration information of the first DMA channel in the configuration information storage unit; transmitting the data pointed to by the first DMA channel according to the configuration information to write the data to a bus; after the data transmission is completed, writing the current configuration information of the first DMA channel into the configuration information storage unit; when the writing operation of the current configuration information is completed, notifying the first DMA channel of a data transmission completion message.

[0007] In some embodiments, the method further includes: receiving a data transmission request from a second DMA channel of a second CPU; and switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission.

[0008] In some embodiments, the bus burst access transmission-based switching of the data transmitted in the first DMA channel and the second DMA channel includes: after transmitting the first data corresponding to the first burst access transmission of the first DMA channel, transmitting the second data corresponding to the second burst access transmission of the second DMA channel; after the second data of the second DMA channel is transmitted, transmitting the third data corresponding to the first burst access transmission of the first DMA channel again.

[0009] In some embodiments, switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission includes: detecting whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number; in the case that the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number, preferentially transmitting the data in the DMA channel with a data number less than the predetermined number.

[0010] In some embodiments, the configuration information storage unit is a static random access memory.

[0011] In some embodiments, the method further includes: configuring different firewall information for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates a memory address range that the DMA channel is allowed to access.

[0012] In some embodiments, transmitting the data pointed to by the first DMA channel according to the configuration information includes: detecting whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel; and transmitting the data pointed to by the first DMA channel when the memory address to be accessed matches the firewall information.

[0013] On the other hand, an embodiment of the present application proposes a data transmission device for a multi-core system-level chip, wherein the multi-core system-level chip includes: multiple central processing units (CPUs) and direct memory access (DMA) controllers; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored together in a configuration information storage unit; a DMA channel is allocated to a CPU for use, a CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; the data transmission device includes: a channel request processing unit, for receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel A DMA channel is an enabled DMA channel, the first DMA channel is one of the multiple hard-isolated DMA channels in the DMA controller; a configuration information read-write unit is used to respond to a data transmission request of the first DMA channel and read the configuration information of the first DMA channel in the configuration information storage unit; a DMA engine is used to transmit the data pointed to by the first DMA channel according to the configuration information to write the data into a bus; the configuration information read-write unit is also used to write the current configuration information of the first DMA channel into the configuration information storage unit after the data transmission is completed; when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel.

[0014] On the other hand, an embodiment of the present application provides a chip storing a computer program, wherein the computer program implements the steps of the above method when executed by a processor.

[0015] On the other hand, an embodiment of the present application proposes a computer device, which includes at least a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the above method when executing the computer program in the memory.

[0016] In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in usage; in addition, each DMA channel has the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, thereby ensuring the system's authority control; the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 A flowchart of a data transmission method for a multi-core system-on-chip provided in the first embodiment of the present application;

[0019] Figure 2 A transmission schematic diagram of different DMA channels being determined based on burst transmission provided in the first embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of a data transmission device for a multi-core system-on-chip provided in a second embodiment of the present application;

[0021] Figure 4 A schematic diagram of the architecture of a data transmission device provided in a second embodiment of the present application, which is arranged in a DMA controller and interacts with a CPU and a bus;

[0022] Figure 5 A schematic diagram of the structure of a computer device provided in the fourth embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiment of the present application clearer, the technical solution of the embodiment of the present application will be clearly and completely described in conjunction with the drawings of the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, not all of the embodiments. Based on the described embodiment of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0025] In order to keep the following description of the embodiments of the present application clear and concise, the present application omits detailed descriptions of known functions and known components.

[0026] The first embodiment of the present application provides a data transmission method for a multi-core system-level chip, the multi-core system-level chip includes: multiple CPUs and a DMA controller; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored in a configuration information storage unit; a DMA channel is allocated to a CPU for use, a CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; the process of the data transmission method is as follows Figure 1 As shown, steps S101 to S105 are included:

[0027] S101, receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of a plurality of hard-isolated DMA channels in a DMA controller.

[0028] The first DMA channel is any one of the multiple DMA channels, and the first CPU is any one of the multiple CPUs of the multi-core system-level chip. In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in use; and in the embodiment of the present application, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and each DMA channel can have the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, which ensures the system's authority control.

[0029] During implementation, the embodiment of the present application can configure a firewall for each DMA channel. Specifically, taking the only two channels of a CPU as an example, it is necessary to configure different firewall information for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates the memory address range that the DMA channel is allowed to access. When transmitting the data pointed to by the first DMA channel according to the configuration information, it is possible to first detect whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel; when the memory address to be accessed matches the firewall information, the data pointed to by the first DMA channel is transmitted. By setting firewall information for the DMA channel, the embodiment of the present application avoids access to memory that is not allowed to be accessed, and also prevents data from being accessed between different DMA channels, thereby ensuring the robustness and security of the operation of multiple CPU systems.

[0030] S102 , in response to a data transmission request of a first DMA channel, reading configuration information of the first DMA channel from a configuration information storage unit.

[0031] In the embodiment of the present application, the configuration information of multiple hard-isolated DMA channels is stored together in one configuration information storage unit, instead of using multiple registers to store the configuration information of DMA channels separately in the prior art. One configuration information storage unit can realize the function of storing the configuration information of DMA channels separately in multiple registers. Compared with the method of setting multiple registers, the method of using one configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip. In specific implementation, the above-mentioned configuration information storage unit is preferably a static random access memory (SRAM).

[0032] S103, transmitting the data pointed to by the first DMA channel according to the configuration information, so as to write the data into the bus.

[0033] When writing data to the bus, the ID of the first DMA channel will be brought to the bus. Since the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, the first DMA channel has the same address access rights as the first CPU to which it belongs, and can implement the same operations as the first CPU on the bus.

[0034] S104, after the data transmission is completed, write the current configuration information of the first DMA channel into the configuration information storage unit.

[0035] Before data transmission, the channel configuration information is read from the SRAM. After data transmission is completed, the configuration information can be written back to the SRAM. The whole process adopts pipeline operation, and there is no extra overhead in time delay. The above configuration information can be a state context, which can include source data and target data addresses, data transmission length, transmission data CRC calculation value, etc., which will not be repeated here.

[0036] S105 , when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel.

[0037] After the transfer completion message is notified to the first DMA channel, the data pointed to by the entire first DMA channel is transferred.

[0038] When receiving a data transmission request from the first DMA channel of the first CPU, data transmission requests from DMA channels corresponding to other CPUs may also be received. If at this time, the amount of data pointed to by the first DMA channel is large, it will take a long time to transmit all the data, which will hinder the data transmission of other DMA channels. In this case, after receiving a data transmission request from the second DMA channel of the second CPU, the embodiment of the present application will switch the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission (burst).

[0039] In specific implementation, after the first burst access transmission corresponding to the first data of the first DMA channel is transmitted, the second burst access transmission corresponding to the second data of the second DMA channel is transmitted; after the second data of the second DMA channel is transmitted, the third data corresponding to the first burst access transmission of the first DMA channel is transmitted again. The burst switching DMA channel is used to alternately transmit the data in the two DMA channels, thereby avoiding the problem of excessive delay caused by the long transmission time of a certain DMA channel and ensuring the response speed.

[0040] Of course, if the amount of data to be transmitted by the first DMA channel or the second DMA channel is not large, then transmitting the data pointed to by the DMA channel first and then transmitting more data of another DMA channel will not cause the problem of excessive delay. Therefore, the embodiment of the present application can also detect whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number; if the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number, the data in the DMA channel with the number of data less than the predetermined number is preferentially transmitted.

[0041] like Figure 2 The figure shows a schematic diagram of the transmission of different DMA channels when performing data transmission based on burst. Figure 2 In the figure, DMA channel x corresponding to CPU0 transmits first, with a total of m bursts, and DMA channel y corresponding to CPU1 has n bursts to transmit. In the transmission order, the bursts of DMA channel x and DMA channel y are transmitted alternately, as shown in the figure. After burst0 of DMA channel x is transmitted, burst0 of DMA channel y is transmitted. After burst0 of DMA channel y is transmitted, burst1 of DMA channel x is transmitted. After burst1 of DMA channel x is transmitted, burst1 of DMA channel y is transmitted. The transmission is transmitted alternately in this order. However, since DMA channel x has the slowest data or the largest transmission volume, the burst of DMA channel x may end last in the transmission order, and other CPUs do not need to wait for the transmission of DMA channel x to complete before starting the transmission, which has little impact on applications based on different CPUs.

[0042] In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in usage; in addition, each DMA channel has the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, thereby ensuring the system's authority control; the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip.

[0043] The second embodiment of the present application provides a data transmission device for a multi-core system-level chip, the multi-core system-level chip includes: multiple CPUs and a DMA controller; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored in a configuration information storage unit; a DMA channel is allocated to a CPU for use, a CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; the structure of the data transmission device is shown in the figure Figure 3 As shown, including:

[0044] A channel request processing unit 10 is used to receive a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel and is one of a plurality of hard-isolated DMA channels in a DMA controller; a configuration information read-write unit 20 is coupled to the channel request processing unit 10 and is used to respond to the data transmission request of the first DMA channel and read the configuration information of the first DMA channel in a configuration information storage unit; a DMA engine 30 is coupled to the configuration information read-write unit 20 and is used to transmit the data pointed to by the first DMA channel according to the configuration information so as to write the data into a bus; the configuration information read-write unit 20 is also used to write the current configuration information of the first DMA channel into the configuration information storage unit after the data transmission is completed; and when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel.

[0045] In order to more clearly illustrate the relationship between the above data transmission device, the CPU and the bus, Figure 4 The schematic diagram of the architecture of the data transmission device arranged in the DMA controller to interact with the CPU and the bus is shown, wherein M is the number of CPUs, N is the number of DMA channels, M is less than N, and both M and N are positive integers. As can be seen from the figure, there are multiple DMA channels, the CPU enables its corresponding DMA channel, and there is one DMA engine, which is responsible for the read and write operations on the bus. The embodiment of the present application takes into account the occupied area of ​​the DMA controller, so only one DMA engine is set. In the specific implementation, if the occupied area of ​​the DMA controller is not considered, multiple DMA engines can also be set, which is also within the protection scope of the embodiment of the present application.

[0046] The first DMA channel is any one of the multiple DMA channels, and the first CPU is any one of the multiple CPUs of the multi-core system-level chip. In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in use; and in the embodiment of the present application, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and each DMA channel can have the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, which ensures the system's authority control.

[0047] When implemented, the embodiment of the present application can configure a firewall for each DMA channel. Specifically, taking the only two channels of a CPU as an example, the DMA engine 30 is also used to configure different firewall information for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates the memory address range that the DMA channel is allowed to access. When transmitting the data pointed to by the first DMA channel according to the configuration information, the DMA engine 30 is also specifically used to detect whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel, and when the memory address to be accessed matches the firewall information, the data pointed to by the first DMA channel is transmitted. The embodiment of the present application avoids access to memory that is not allowed to be accessed by setting firewall information for the DMA channel, and also prevents data from being accessed between different DMA channels, thereby ensuring the robustness and security of the operation of multiple CPU systems.

[0048] In the embodiment of the present application, the configuration information of multiple hard-isolated DMA channels is stored together in one configuration information storage unit, instead of using multiple registers to store the configuration information of DMA channels separately in the prior art. One configuration information storage unit can realize the function of storing the configuration information of DMA channels separately in multiple registers. Compared with the method of setting multiple registers, the method of using one configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip. In specific implementation, the above-mentioned configuration information storage unit is preferably SRAM.

[0049] Before data transmission, the channel configuration information is read from the SRAM. When writing data to the bus, the ID of the first DMA channel will be brought to the bus. Since the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, the first DMA channel has the same address access rights as the first CPU to which it belongs, and the same operations as the first CPU can be performed on the bus. After the data transmission is completed, the configuration information can be written back to the SRAM. The entire process adopts a pipeline operation, and there is no extra overhead in time delay. When the transmission completion message is notified to the first DMA channel, the data pointed to by the entire first DMA channel is transmitted. The above configuration information can be a state context, which can include, for example, the source data and target data addresses, the data transmission length, the transmission data CRC calculation value, etc., which will not be repeated here.

[0050] When receiving a data transmission request from the first DMA channel of the first CPU, data transmission requests from DMA channels corresponding to other CPUs may also be received. If at this time, the amount of data pointed to by the first DMA channel is large, it will take a long time to transfer all the data, which will hinder the data transmission of other DMA channels. For this situation, the channel request processing unit 10 of the embodiment of the present application is also used to receive a data transmission request from the second DMA channel of the second CPU; the DMA engine 30 is also used to switch the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission (burst).

[0051] When switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission, the DMA engine 30 is further used to: after transmitting the first data corresponding to the first burst access transmission of the first DMA channel, transmit the second data corresponding to the second burst access transmission of the second DMA channel; after the second data of the second DMA channel is transmitted, transmit the third data corresponding to the first burst access transmission of the first DMA channel again. By using burst switching DMA channels to alternately transmit data in the two DMA channels, the problem of excessive delay caused by too long transmission time of a certain DMA channel is avoided, and the response speed is guaranteed.

[0052] Of course, if the amount of data to be transmitted by the first DMA channel or the second DMA channel is not large, then transmitting the data pointed to by the DMA channel first and then transmitting more data of another DMA channel will not cause the problem of excessive delay. Therefore, the DMA engine 30 of the embodiment of the present application can also be used to: detect whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number; when the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number, preferentially transmit the data in the DMA channel with the number of data less than the predetermined number.

[0053] In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in usage; in addition, each DMA channel has the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, thereby ensuring the system's authority control; the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip.

[0054] The third embodiment of the present application provides a chip storing a computer program, which, when executed by a processor, implements the data transmission method of the multi-core system-level chip provided by any embodiment of the present application; the multi-core system-level chip includes: multiple central processing units (CPUs) and direct memory access (DMA) controllers; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored together in a configuration information storage unit; one DMA channel is allocated to one CPU for use, one CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; the data transmission method includes the following steps S11 to S15:

[0055] S11, receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of a plurality of hard-isolated DMA channels in a DMA controller;

[0056] S12, in response to a data transmission request of the first DMA channel, reading configuration information of the first DMA channel from a configuration information storage unit;

[0057] S13, transmitting the data pointed to by the first DMA channel according to the configuration information to write the data into the bus;

[0058] S14, after the data transmission is completed, writing the current configuration information of the first DMA channel into the configuration information storage unit;

[0059] S15, when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel.

[0060] The configuration information storage unit may be a static random access memory.

[0061] The computer program is specifically further executed by the processor to perform the following steps: receiving a data transmission request of a second DMA channel of the second CPU; and switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission.

[0062] When the computer program is executed by the processor to switch the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission, the processor specifically executes the following steps: after transmitting the first data corresponding to the first burst access transmission of the first DMA channel, the second data corresponding to the second burst access transmission of the second DMA channel is transmitted; after the second data of the second DMA channel is transmitted, the third data corresponding to the first burst access transmission of the first DMA channel is transmitted again.

[0063] When the computer program is executed by the processor to switch the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission, the processor specifically executes the following steps: detecting whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number; when the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number, preferentially transmitting the data in the DMA channel with the number of data less than the predetermined number.

[0064] The computer program is specifically further executed by the processor to perform the following steps: configuring different firewall information for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates the memory address range that the DMA channel is allowed to access.

[0065] When the computer program is executed by the processor to transmit the data pointed to by the first DMA channel according to the configuration information, the processor specifically executes the following steps: detecting whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel; and transmitting the data pointed to by the first DMA channel when the memory address to be accessed matches the firewall information.

[0066] In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in usage; in addition, each DMA channel has the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, thereby ensuring the system's authority control; the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip.

[0067] Optionally, the specific examples in this embodiment can refer to the examples described in the above embodiments and the optional implementation modes, and this embodiment will not be repeated here. Obviously, it should be understood by those skilled in the art that the above-mentioned modules or steps of the present application can be implemented with a general computing device, which can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented with executable program codes of computing devices, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in an order different from that here, or they can be made into each integrated circuit module respectively, or multiple modules or steps therein can be made into a single integrated circuit module to implement. In this way, the present application is not limited to any specific hardware and software combination.

[0068] A fourth embodiment of the present application provides a computer device. The structural diagram of the computer device can be as follows: Figure 5 As shown, at least a memory 901 and a processor 902 are included, the memory 901 stores a computer program, and the processor 902 implements the data transmission method of the multi-core system-level chip provided by any embodiment of the present application when executing the computer program on the memory 901; the multi-core system-level chip includes: multiple central processing units CPU and direct memory access DMA controller; the DMA controller includes multiple hard-isolated DMA channels, and the configuration information of the multiple hard-isolated DMA channels is stored together in a configuration information storage unit; a DMA channel is allocated to a CPU for use, a CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access rights; illustratively, the computer device computer program steps are as follows S21 to S25:

[0069] S21, receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of a plurality of hard-isolated DMA channels in a DMA controller;

[0070] S22, in response to a data transmission request of the first DMA channel, reading configuration information of the first DMA channel from a configuration information storage unit;

[0071] S23, transmitting the data pointed to by the first DMA channel according to the configuration information to write the data into the bus;

[0072] S24, after the data transmission is completed, writing the current configuration information of the first DMA channel into the configuration information storage unit;

[0073] S25, when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel.

[0074] The configuration information storage unit may be a static random access memory.

[0075] The processor also specifically executes the following computer program: receiving a data transmission request of a second DMA channel of a second CPU; and switching data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission.

[0076] When the processor executes a computer program stored in the memory for switching data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission, the processor specifically executes the following computer program: after transmitting the first data corresponding to the first burst access transmission of the first DMA channel, the second data corresponding to the second burst access transmission of the second DMA channel is transmitted; after the second data of the second DMA channel is transmitted, the third data corresponding to the first burst access transmission of the first DMA channel is transmitted again.

[0077] When the processor executes a computer program stored in the memory and switching data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission, the processor specifically executes the following computer program: detecting whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number; when the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than the predetermined number, preferentially transmitting the data in the DMA channel whose number of data is less than the predetermined number.

[0078] The processor also specifically executes the following computer program: configuring different firewall information for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates a memory address range that the DMA channel is allowed to access.

[0079] When the processor executes a computer program stored in the memory and transmitting the data pointed to by the first DMA channel according to the configuration information, the processor specifically executes the following computer program: detecting whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel; and transmitting the data pointed to by the first DMA channel when the memory address to be accessed matches the firewall information.

[0080] In the embodiment of the present application, a corresponding DMA channel is allocated to each CPU, and each DMA channel is dedicated to one CPU. During data transmission, the hard-isolated DMA channels are independent of each other, and each DMA channel is configured to use all DMA functions. Each DMA channel only serves its corresponding CPU, and there will be no confusion in usage; in addition, each DMA channel has the same memory address access rights as the CPU to which it belongs, and multiple CPUs have different memory address access rights, thereby ensuring the system's authority control; the use of a configuration information storage unit reduces the area overhead by at least 10 times, greatly reduces the occupancy rate of the storage area on the DMA controller, further reduces the size of the DMA controller, and thus provides more space for chip design, provides great operability for reducing chip size or adding more chip functions, and improves the overall performance of the chip.

[0081] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0082] In addition, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present application with equivalent elements, modifications, omissions, combinations (e.g., various embodiments intersecting schemes), adaptations or changes. The elements in the claims are to be interpreted broadly based on the language adopted in the claims, and are not limited to the examples described in this specification or during the practice of this application, and the examples are to be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered as examples only, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.

[0083] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more schemes thereof) may be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features may be grouped together to simplify the present application. This should not be interpreted as an intention that a disclosed feature that is not required to be protected is necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of a particular disclosed embodiment. Thus, the following claims are incorporated herein as examples or embodiments in the specific embodiments, wherein each claim is independently a separate embodiment, and it is considered that these embodiments may be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the attached claims and the full scope of equivalent forms granted by these claims.

[0084] Multiple embodiments of the present application are described in detail above, but the present application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present application, and these variations and modifications should all fall within the scope of protection required by the present application.

Claims

1. A data transmission method for a multi-core system-on-chip, It is characterized in that The multi-core system-level chip includes: multiple central processing units (CPUs) and direct memory access (DMA) controllers; the DMA controller includes multiple hard-isolated DMA channels, and configuration information of the multiple hard-isolated DMA channels is stored in a configuration information storage unit; one DMA channel is allocated to one CPU for use, one CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access permissions; The data transmission method comprises: Receiving a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of the multiple hard-isolated DMA channels in the DMA controller; In response to a data transmission request of the first DMA channel, reading configuration information of the first DMA channel in the configuration information storage unit; transmitting the data pointed to by the first DMA channel according to the configuration information to write the data into a bus; After the data transmission is completed, writing the current configuration information of the first DMA channel into the configuration information storage unit; When the writing operation of the current configuration information is completed, notifying the first DMA channel of a data transfer completion message; The method further comprises: receiving a data transfer request from a second DMA channel of a second CPU; Switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission; The switching of the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission includes: After transmitting the first data corresponding to the first burst access transmission of the first DMA channel, transmitting the second data corresponding to the second burst access transmission of the second DMA channel; After the second data of the second DMA channel is transmitted, the third data corresponding to the first burst access transmission of the first DMA channel is transmitted again.

2. The data transmission method of a multi-core system-on-chip according to claim 1, It is characterized in that Switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission includes: Detecting whether the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number; When the number of data corresponding to the burst access transmission in the first DMA channel or the second DMA channel is less than a predetermined number, the data in the DMA channel whose number of data is less than the predetermined number is preferentially transmitted.

3. The data transmission method of a multi-core system-on-chip according to claim 1, It is characterized in that The configuration information storage unit is a static random access memory.

4. The data transmission method of a multi-core system-on-chip according to any one of claims 1 to 3, It is characterized in that The method further comprises: Different firewall information is configured for the first DMA channel and the third DMA channel of the first CPU, wherein the firewall information indicates a memory address range that the DMA channel is allowed to access.

5. The data transmission method of a multi-core system-on-chip as claimed in claim 4, It is characterized in that The transmitting the data pointed to by the first DMA channel according to the configuration information includes: Detecting whether the memory address to be accessed by the first DMA channel matches the firewall information of the first DMA channel; When the memory address to be accessed matches the firewall information, the data pointed to by the first DMA channel is transmitted.

6. A data transmission device for a multi-core system-on-chip, It is characterized in that The multi-core system-level chip includes: multiple central processing units (CPUs) and direct memory access (DMA) controllers; the DMA controller includes multiple hard-isolated DMA channels, and configuration information of the multiple hard-isolated DMA channels is stored in a configuration information storage unit; one DMA channel is allocated to one CPU for use, one CPU is configured with one or more DMA channels, the ID of the DMA channel is configured to match the ID of the CPU to which it belongs, and multiple CPUs have different memory address access permissions; The data transmission device comprises: a channel request processing unit, configured to receive a data transmission request of a first DMA channel of a first CPU, wherein the first DMA channel is an enabled DMA channel, and the first DMA channel is one of the multiple hard-isolated DMA channels in the DMA controller; a configuration information reading and writing unit, configured to read the configuration information of the first DMA channel from the configuration information storage unit in response to a data transmission request of the first DMA channel; a DMA engine, configured to transmit the data pointed to by the first DMA channel according to the configuration information, so as to write the data into a bus; The configuration information reading and writing unit is further used to write the current configuration information of the first DMA channel into the configuration information storage unit after the data transmission is completed; when the writing operation of the current configuration information is completed, a data transmission completion message is notified to the first DMA channel; The channel request processing unit is further used to receive a data transmission request of a second DMA channel of the second CPU; The DMA engine is further used for switching the data transmitted in the first DMA channel and the second DMA channel based on bus burst access transmission; The DMA engine is also used for: After transmitting the first data corresponding to the first burst access transmission of the first DMA channel, transmitting the second data corresponding to the second burst access transmission of the second DMA channel; After the second data of the second DMA channel is transmitted, the third data corresponding to the first burst access transmission of the first DMA channel is transmitted again.

7. A chip storing a computer program. It is characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

8. An electronic device comprising at least a memory and a processor, wherein the memory stores a computer program. It is characterized in that The processor implements the steps of the method of any one of claims 1 to 5 when executing the computer program on the memory.

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