Testing method of bottom circuit layout, testing method and device of circuit layout

Abstract

The present application relates to a testing method for a bottom-layer circuit layout, a testing method and device for a circuit layout, including: obtaining a current bottom-layer circuit layout for a pre-post-simulation test; obtaining a circuit structure associated with the current bottom-layer circuit layout; combining the current bottom-layer circuit layout with the circuit structure and filling virtual metal to form a post-simulation test structure associated with the current bottom-layer circuit layout; based on the post-simulation test structure, performing a post-simulation test on the current bottom-layer circuit layout to obtain a post-simulation test result of the current bottom-layer circuit layout. The present disclosure helps to improve the consistency between the post-simulation test results of the bottom-layer circuit layout and the post-simulation test results of the top-layer circuit layout, helps to prevent the problem that the bottom-layer circuit layout meets the design requirements while the top-layer circuit layout cannot meet the design requirements, and helps to improve the development efficiency of the integrated circuit design stage.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a method for testing an underlying circuit layout, a method for testing a circuit layout, and a device for testing a circuit layout. Background Art

[0002] In the manufacturing process of integrated circuits, dummy metal is a metal support structure unrelated to the circuit pattern added to the wafer to meet the minimum metal density requirements, prevent grooves from appearing in the metal layer during chemical mechanical polishing (CMP), and support the metal layer.

[0003] Although virtual metal has nothing to do with circuit graphics, its existence will lead to the existence of parasitic RC (capacitance resistance) in the circuit, causing an increase in RC parameters, which will lead to a decrease in the frequency of high-speed circuits and even affect signal transmission.

[0004] Therefore, during the integrated circuit design phase, it is necessary to introduce virtual metal and perform corresponding tests to avoid the problem of signal transmission being affected by the presence of virtual metal. Summary of the invention

[0005] In view of this, the present application provides a testing method for a bottom-level circuit layout, a testing method and a device for a circuit layout, so as to help reduce the difference between the post-simulation test results of the bottom-level circuit layout and the post-simulation test results of the top-level circuit layout caused by the RC parameters brought about by the unreal virtual metal introduced in the post-simulation process of the bottom-level circuit layout, and help improve the consistency between the post-simulation test results of the bottom-level circuit layout and the post-simulation test results of the top-level circuit layout.

[0006] According to one aspect of an embodiment of the present disclosure, a method for testing a bottom layer circuit layout is provided, comprising:

[0007] Obtain the current bottom-layer circuit layout for pre-simulation testing;

[0008] Acquire a circuit structure associated with the current bottom layer circuit layout;

[0009] Combining the current bottom layer circuit layout with the circuit structure and filling virtual metal to form a post-simulation test structure associated with the current bottom layer circuit layout;

[0010] Based on the post-simulation test structure, a post-simulation test result of the current bottom-layer circuit layout is obtained by performing a post-simulation test on the current bottom-layer circuit layout.

[0011] In a possible implementation, the circuit structure includes at least one of other underlying circuit layouts associated with the current underlying circuit layout and a metal interconnection structure between the current underlying circuit layout and the other underlying circuit layouts.

[0012] In a possible implementation manner, combining the current bottom layer circuit layout with the circuit structure includes:

[0013] In the case where the other bottom-layer circuit layouts include devices and connecting wiring between devices, connecting the current bottom-layer circuit layout with the other bottom-layer circuit layouts through a planned metal interconnect structure;

[0014] When the other bottom-level circuit layout only includes devices, or when the other bottom-level circuit layout does not include devices, the current bottom-level circuit layout is connected to the other bottom-level circuit layout through a pre-planned metal interconnection structure.

[0015] In a possible implementation manner, the dummy metal is filled in the space of the metal interconnect structure not occupied by the circuit structure, and is removed after the post-simulation test of the current bottom layer circuit layout is completed.

[0016] In a possible implementation manner, the bottom layer circuit layout testing method further includes:

[0017] In the case that the circuit structure does not exist, the virtual metal is directly filled around the current bottom layer circuit layout to form the post-simulation test structure.

[0018] According to another aspect of an embodiment of the present disclosure, a method for testing a circuit layout is provided, comprising:

[0019] Performing the bottom layer circuit layout testing method as described in any one of the above items on at least one of all the bottom layer circuit layouts constituting the top layer circuit layout;

[0020] Connecting all the bottom-layer circuit layouts that have passed the post-simulation test through the planned metal interconnection structure and filling virtual metal to form the top-layer circuit layout that has been pre-tested;

[0021] By performing a post-simulation test on the top-level circuit layout, a post-simulation test result of the top-level circuit layout is obtained.

[0022] According to another aspect of an embodiment of the present disclosure, a testing device for a bottom layer circuit layout is provided, comprising:

[0023] A layout acquisition module is configured to execute acquisition of the current bottom layer circuit layout for pre-simulation test;

[0024] A circuit structure acquisition module, configured to execute acquisition of a circuit structure associated with the current bottom layer circuit layout;

[0025] A test structure assembly module is configured to perform combining the current bottom layer circuit layout with the circuit structure and filling virtual metal to form a post-simulation test structure associated with the current bottom layer circuit layout;

[0026] The bottom layer layout post-simulation test module is configured to execute a post-simulation test on the current bottom layer circuit layout based on the post-simulation test structure to obtain a post-simulation test result of the current bottom layer circuit layout.

[0027] According to another aspect of an embodiment of the present disclosure, a circuit layout testing device is provided, comprising:

[0028] The testing device for the bottom layer circuit layout as described above is used to perform a post-simulation test of the bottom layer circuit layout on at least one of all the bottom layer circuit layouts constituting the top layer circuit layout;

[0029] A top-level circuit layout assembly module is configured to connect all the bottom-level circuit layouts that have passed the post-simulation test through the planned metal interconnection structure and fill the virtual metal to form the top-level circuit layout that has been pre-tested for the post-simulation test;

[0030] The top-level layout post-simulation test module is configured to perform a post-simulation test on the top-level circuit layout to obtain a post-simulation test result of the top-level circuit layout.

[0031] According to another aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0032] processor;

[0033] a memory for storing executable instructions for the processor;

[0034] Wherein, the processor is configured to execute the executable instructions to implement the testing method of the underlying circuit layout as described in any of the above items and / or the testing method of the circuit layout as described above.

[0035] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the testing method of the underlying circuit layout as described in any of the above items and / or the testing method of the circuit layout as described above.

[0036] It can be seen from the above scheme that in the testing method of the bottom-layer circuit layout, the testing method and device of the circuit layout disclosed in the present invention, after the current bottom-layer circuit layout is combined with the associated circuit structure, the circuit structure will occupy a part of the space that should be filled with unreal virtual metal, and because the circuit structure is associated with the current bottom-layer circuit layout, the circuit structure around the current bottom-layer circuit layout is closer to the circuit structure in the final top-layer circuit layout, which means that the RC parameters extracted by the current bottom-layer circuit layout will be closer to the actual contribution of the current bottom-layer circuit layout to the RC parameters of the top-layer circuit layout, and thus the disclosed scheme helps to reduce the difference between the post-simulation test results of the current bottom-layer circuit layout and the post-simulation test results of the top-layer circuit layout, thereby helping to improve the consistency between the post-simulation test results of the bottom-layer circuit layout and the post-simulation test results of the top-layer circuit layout, helping to prevent the problem that the bottom-layer circuit layout meets the design requirements but the top-layer circuit layout cannot meet the design requirements, and helping to improve the development efficiency of the integrated circuit design stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the design process of an analog circuit in the related art;

[0038] Figure 2 It is a flowchart of post-simulation and other related processes for circuit layout in the related technology;

[0039] Figure 3 is a flow chart of a method for testing a bottom-layer circuit layout according to an exemplary embodiment;

[0040] Figure 4 It is a flowchart of an application scenario of a method for testing a bottom-layer circuit layout according to an exemplary embodiment;

[0041] Figure 5 is a schematic diagram of a post-simulation test layout including associated circuit structures according to an exemplary embodiment;

[0042] Figure 6 is a flow chart of a circuit layout testing method according to an exemplary embodiment;

[0043] Figure 7 is a structural schematic diagram of a testing device for a bottom-layer circuit layout according to an exemplary embodiment;

[0044] Figure 8 is a schematic structural diagram of a circuit layout testing device according to an exemplary embodiment;

[0045] Fig. 9 It is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0048] Analog circuits are circuits used to transmit, transform, process, amplify, measure, and display analog signals. They are an important interface between the real world and the digital world. Compared with digital circuits, analog circuits may have higher requirements for voltage and current stability, because even small changes may affect the quality of the signal, and analog circuits may be more sensitive to noise and interference. For this reason, analog circuits usually adopt fully customized designs, which require the design of circuit schematics and layouts, as well as pre-simulation and post-simulation.

[0049] Figure 1 It is a schematic diagram of the design process of analog circuits in related technologies. Figure 1 As shown in the figure, the design process of analog circuits usually includes: determining the demand stage, including determining the design standards of the circuit; then, designing the circuit schematic; after the circuit schematic design is completed, pre-circuit simulation is performed, and the circuit schematic is modified according to the results of the pre-simulation; after the pre-simulation is completed, the circuit layout is designed according to the circuit schematic; then, the circuit layout is subjected to DRC (Design Rule Check, design rule check) and LVS (Layout Versus Schematic, layout and principle) verification. Figure 1 The circuit layout is then modified based on the post-simulation results, DRC and LVS are performed, parasitic parameters are extracted, and post-simulation is performed again, until the performance of the analog circuit corresponding to the circuit layout meets the requirements and the design of the analog circuit is completed.

[0050] In chip design, hierarchical design is a common design method, which refers to breaking down complex chip designs into smaller, more manageable modules or subsystems. This design method allows large integrated circuits (ICs) to be divided into multiple levels, each level is responsible for different functions or circuit parts. In a hierarchical design, there is usually a top-level design and multiple sub-modules or partitions. Among them, the top-level design corresponds to the top-circuit, which is the circuit structure of the integrated circuit as a whole. The top-circuit layout is the entire layout containing the circuit structure of the integrated circuit as a whole. The top-level design is the overall framework of the integrated circuit. A sub-module or partition can be a functional block with specific functions, such as a processor core, a memory controller, an input / output interface, etc. A sub-module can be further subdivided into smaller modules to form a hierarchical structure. A sub-module or partition corresponds to a sub-circuit. A sub-circuit is a part of the circuit structure in an integrated circuit, such as the circuit structure of a functional module. The sub-circuit layout is the circuit structure of the functional modules that make up the integrated circuit.

[0051] Under normal circumstances, the top-level circuit will be composed of several bottom-level circuits. After the pre-simulation is completed, the bottom-level circuit layout will be designed first, and DRC, LSV, parasitic parameter extraction and post-simulation verification will be performed on the bottom-level circuit layout. After the post-simulation results of the bottom-level circuit layout meet the relevant specifications (spec), the top-level circuit layout containing the bottom-level circuit layout will be designed. At the same time, in order to meet the metal density requirements in the DRC rules, it is also necessary to sprinkle dummy metal in the blank positions in the circuit layout, and then perform RC parameter extraction on the circuit layout, that is, extract the resistance (R) parasitic parameters and capacitance (C) parasitic parameters on the metal (metal) lines in the circuit layout. Finally, post-simulation verification is performed. After the post-simulation performance of the circuit layout meets the corresponding specification requirements, the post-simulation work is completed.

[0052] Figure 2 It is a flowchart of the related process of post-simulation and the like for the circuit layout in the related technology, such as Figure 2As shown, after completing the pre-simulation, the bottom circuit layout is obtained through design; then, DRC and LVS are performed on the bottom circuit layout; then, RC parameters are extracted from the bottom circuit layout; then, post-simulation is performed on the bottom circuit layout, and the bottom circuit layout is modified, DRC and LVS are performed, RC parameters are extracted, and post-simulation is performed again according to the post-simulation results; after the performance of the analog circuit corresponding to the bottom circuit layout meets the requirements, the bottom circuit layout is assembled to obtain the top circuit layout, and virtual metal is sprinkled on the blank positions of the top circuit layout; then, DRC and LVS are performed on the top circuit layout; then, RC parameters are extracted from the top circuit layout; then, post-simulation is performed on the top circuit layout, and the top circuit layout is modified, DRC and LVS are performed, RC parameters are extracted, and post-simulation is performed again according to the post-simulation results, and the post-simulation work is completed after the post-simulation performance of the top circuit layout meets the corresponding specification requirements.

[0053] In the related art, whether it is the post-simulation of the bottom circuit layout or the post-simulation of the top circuit layout, in the process of extracting RC parameters (or before extracting RC parameters), the related program will automatically fill the gaps in the layout with high-density virtual metal, which will result in a lot of unreal virtual metal being added when the bottom circuit layout is extracted. These unreal virtual metals will be removed when forming the top circuit layout. Because the existence of virtual metal will affect the extracted RC parameters, these unreal virtual metals will affect the post-simulation results of the bottom circuit layout, which may cause deviations between the post-simulation results of the bottom circuit layout and the post-simulation results of the top circuit layout, such as differences between the frequency results of the post-simulation of the bottom circuit layout and the frequency results of the post-simulation of the top circuit layout. This difference may cause the post-simulation test results of the bottom circuit layout to meet the design requirements, but the post-simulation test results of the top circuit layout composed of all the bottom circuit layouts that meet the design requirements cannot meet the design requirements, resulting in rework of the integrated circuit design and development, thereby affecting the development efficiency. How to reduce this error has become a problem that needs to be solved urgently.

[0054] In view of this, the embodiments of the present disclosure provide a testing method for a bottom-level circuit layout, a testing method and a device for a circuit layout, so as to help reduce the difference between the post-simulation test results of the bottom-level circuit layout and the post-simulation test results of the top-level circuit layout caused by the RC parameters brought about by the unreal virtual metal introduced in the post-simulation process of the bottom-level circuit layout, and help improve the consistency between the post-simulation test results of the bottom-level circuit layout and the post-simulation test results of the top-level circuit layout.

[0055] Figure 3 is a flow chart of a method for testing a bottom-layer circuit layout according to an exemplary embodiment. Figure 3As shown, the testing method of the bottom layer circuit layout mainly includes the following steps 301 to 304.

[0056] Step 301, obtaining the current bottom layer circuit layout for the pre-simulation test;

[0057] Step 302: Obtain a circuit structure associated with the current bottom layer circuit layout;

[0058] Step 303: Combine the current bottom layer circuit layout with the circuit structure and fill virtual metal to form a post-simulation test structure associated with the current bottom layer circuit layout;

[0059] Step 304 : Based on the post-simulation test structure, a post-simulation test is performed on the current bottom-layer circuit layout to obtain a post-simulation test result of the current bottom-layer circuit layout.

[0060] In the testing method of the bottom-layer circuit layout of the embodiment of the present disclosure, in step 303, after the current bottom-layer circuit layout is combined with the associated circuit structure, the circuit structure will occupy a part of the space that should be filled with unreal virtual metal, and because the circuit structure is associated with the current bottom-layer circuit layout, the circuit structure around the current bottom-layer circuit layout is closer to the circuit structure in the final top-layer circuit layout, which means that the RC parameters extracted by the current bottom-layer circuit layout will be closer to the actual contribution of the current bottom-layer circuit layout to the RC parameters of the top-layer circuit layout, so it helps to reduce the difference between the post-simulation test results of the current bottom-layer circuit layout and the post-simulation test results of the top-layer circuit layout, and helps to improve the consistency between the post-simulation test results of the current bottom-layer circuit layout and the post-simulation test results of the top-layer circuit layout.

[0061] In an exemplary embodiment, the circuit structure associated with the current bottom circuit layout may include a structure that is the same as or similar to the real circuit structure, wherein the real circuit structure refers to the circuit structure arranged around the current bottom circuit layout when it is in the top circuit layout of the final completed design. The more similar the circuit structure associated with the current bottom circuit layout is to the real circuit structure and the larger the space occupied (which means that more unreal virtual metal can be replaced), the closer the RC parameters extracted for the current bottom circuit layout are to the real contribution of the current bottom circuit layout to the RC parameters of the top circuit layout. From the perspective of post-simulation test results, the difference between the post-simulation test results of the current bottom circuit layout and the post-simulation test results of the top circuit layout is. In an exemplary embodiment, the circuit structure includes at least one of other bottom circuit layouts associated with the current bottom circuit layout and metal interconnect structures between the current bottom circuit layout and other bottom circuit layouts.

[0062] In the exemplary embodiment, due to the complexity of the integrated circuit, during the design process of the circuit layout, part of the underlying circuit layout may have been designed, part of the underlying circuit layout is in a state of waiting to be designed, and part of the underlying circuit layout is in a state of being designed. For the current underlying circuit layout that currently needs to execute the test method of the underlying circuit layout of the embodiment of the present disclosure, other underlying circuit layouts around it may be in a state of being designed, waiting to be designed, or in a state of being designed. For the current bottom-level circuit layout to be subjected to post-simulation test, no matter what design status the other surrounding bottom-level circuit layouts are in, as long as the circuit structure associated with it is set in the area around the current bottom-level circuit layout, even if the circuit structure is not yet perfect, it is still closer to the circuit structure of the top-level circuit layout than when only unreal virtual metal is set in the area around the current bottom-level circuit layout. Therefore, even if the other surrounding bottom-level circuit layouts have not yet been designed, the circuit structure associated with the current bottom-level circuit layout to be subjected to post-simulation test cannot be guaranteed to be completely consistent with the corresponding circuit structure in the top-level circuit layout, and the post-simulation result of the current bottom-level circuit layout will also be more likely to be closer to the post-simulation result of the top-level circuit layout than the post-simulation result of only setting unreal virtual metal.

[0063] In an illustrative embodiment, taking into account the different design states that other underlying circuit layouts may be in, step 303 may specifically include: when other underlying circuit layouts contain devices and connecting lines between devices, connecting the current underlying circuit layout with the other underlying circuit layouts through a planned metal interconnection structure; when other underlying circuit layouts only contain devices, or when other underlying circuit layouts do not contain devices, connecting the current underlying circuit layout with the other underlying circuit layouts through a pre-planned metal interconnection structure.

[0064] In an exemplary embodiment, the device may include transistors, capacitors, resistors, and other basic electronic components in the underlying circuit layout.

[0065] In the exemplary embodiment, the situation that other bottom-level circuit layouts contain devices and connecting lines between devices indicates that the design of other bottom-level circuit layouts may have been basically completed. At this time, the planned metal interconnection structure indicates that with the completion of the design of other bottom-level circuit layouts, the metal interconnection structure between modules of other bottom-level circuit layouts and the current bottom-level circuit layout is also basically determined. Although appropriate modifications may be made, the degree of modification will not be too large and will not lead to excessive adjustments to the entire integrated circuit layout. In the case that other bottom-level circuit layouts contain devices and connecting lines between devices, after connecting the current bottom-level circuit layout with other bottom-level circuit layouts through the planned metal interconnection structure, for the current bottom-level circuit layout, the other bottom-level circuit layouts and the planned metal interconnection structure are closer to the structural features of the top-level circuit layout, and the structural layout of the unreal virtual metal filled will also be closer to the virtual metal filled in the top-level circuit layout. Therefore, after connecting the current bottom-level circuit layout with other bottom-level circuit layouts and filling virtual metal (unreal) in this way, the post-simulation test results of the current bottom-level circuit layout will be closer to the post-simulation test results of the top-level circuit layout.

[0066] In the exemplary embodiment, the case where other bottom-level circuit layouts only include devices indicates that the other bottom-level circuit layouts have not been completed in the design process. At this time, the pre-planned metal interconnection structure indicates that the metal interconnection structure between the modules of the other bottom-level circuit layouts and the current bottom-level circuit layout cannot be determined, and may be modified according to the addition of the connection lines between the devices of the other bottom-level circuit layouts. In the case where other bottom-level circuit layouts only include devices, after the current bottom-level circuit layout is connected to the other bottom-level circuit layouts through the pre-planned metal interconnection structure, although the other bottom-level circuit layouts have not been completed, they are closer to the structural features of the top-level circuit layout than the method of only filling unreal virtual metal around the current bottom-level circuit layout. Therefore, compared with the post-simulation test results of only filling unreal virtual metal around the current bottom-level circuit layout, the post-simulation test results of the current bottom-level circuit layout in this way will also be closer to the post-simulation test results of the top-level circuit layout.

[0067] In the exemplary embodiment, the situation that other bottom-level circuit layouts do not contain devices indicates that the design of other bottom-level circuit layouts may not have started yet, but only the area where the modules of other bottom-level circuit layouts are located has been planned. At this time, the metal interconnection structure cannot be determined, but it can be pre-planned according to the area where the modules of other bottom-level circuit layouts are located. In the case that other bottom-level circuit layouts do not contain devices, after the current bottom-level circuit layout is connected to other bottom-level circuit layouts through the pre-planned metal interconnection structure, although the design of other bottom-level circuit layouts has not started yet, due to the existence of the pre-planned metal interconnection structure, compared with the method of only filling unreal virtual metal around the current bottom-level circuit layout, it will be closer to the structural features of the top-level circuit layout. Therefore, compared with the post-simulation test results of only filling unreal virtual metal around the current bottom-level circuit layout, the post-simulation test results of the current bottom-level circuit layout in this way will also be closer to the post-simulation test results of the top-level circuit layout.

[0068] In an exemplary embodiment, virtual metal is filled in the space of the metal interconnect structure not occupied by the circuit structure, and is removed after the post-simulation test of the current bottom circuit layout is completed. In step 303, after the current bottom circuit layout is combined with the circuit structure, the virtual metal can no longer be filled in the space occupied by the circuit structure. The space of the metal interconnect structure not occupied by the circuit structure usually corresponds to the area with low metal density in the metal layer. The virtual metal is filled in these spaces, and in the subsequent semiconductor device manufacturing process, it will play a supporting role for the metal layer during the chemical mechanical polishing process. At this time (step 303), the virtual metal (not real, which will be removed after the current bottom circuit layout simulation is completed) filled in the space of the metal interconnect structure not occupied by the circuit structure plays a role in the post-simulation of the current bottom circuit layout. It can be considered that it is close to the role of the virtual metal in the top circuit layout (real, which will be retained after the top circuit layout is post-simulated and will be generated with the manufacture of the integrated circuit). The RC parameters brought by the unreal virtual metal are close to the RC parameters brought by the real virtual metal added to the corresponding position area during the post-simulation test of the top circuit layout. Therefore, from the perspective of the current bottom-level circuit layout, the circuit structure and the unreal virtual metal filled in the space not occupied by the circuit structure simulate the structure of the corresponding position area in the top-level circuit layout. Therefore, the post-simulation results of the current bottom-level circuit layout will be closer to the post-simulation results of the top-level circuit layout.

[0069] In some cases, the current bottom-layer circuit layout may have been designed and pre-simulated, but other bottom-layer circuit layouts associated with the current bottom-layer circuit layout have not been designed. In this case, there is no associated circuit structure to add. If a circuit structure not associated with the current bottom-layer circuit layout is added, the added circuit structure will lose its reference value because it is very different from the structure of the top-layer circuit layout after the design is completed later. In an illustrative embodiment, in this case, the test method of the bottom-layer circuit layout of the embodiment of the present disclosure also includes: in the absence of the circuit structure, directly filling virtual metal around the current bottom-layer circuit layout to form a post-simulation test structure. This situation is a solution that returns to the relevant technology. When individual bottom-layer circuit layouts among the multiple bottom-layer circuit layouts that constitute the top-layer circuit layout adopt this solution, and when the majority of other bottom-layer circuit layouts adopt the test method of the bottom-layer circuit layout of the embodiment of the present disclosure, it still helps to improve the consistency between the post-simulation test results of most bottom-layer circuit layouts and the post-simulation test results of the top-layer circuit layout.

[0070] In the related art, before executing the post-simulation test of the bottom-level circuit layout, there is no virtual metal filled in the bottom-level circuit layout. When the metal density of the bottom-level circuit layout does not meet the DRC requirements, the related software program will fill a large number of blank spaces in the bottom-level circuit layout with virtual metal with higher density, and perform RC parameter extraction on this basis. The parasitic capacitance of the virtual metal will be evenly applied to the parasitic capacitance of each metal trace, but the blank spaces in the actual top-level circuit layout will run through several top-level (top layer) traces. Even without these traces, the density of the virtual metal actually filled in the top-level circuit layout will be relatively low.

[0071] Since the environment of the top-level circuit layout is more realistic, based on the disclosed embodiment, when designing the current bottom-level circuit layout, other bottom-level circuit layouts existing around the current bottom-level circuit layout are placed in the current bottom-level circuit layout as dummy parts, and dummy metal is filled in the remaining positions of the current bottom-level circuit layout. In this way, the post-simulation test results of the current bottom-level circuit layout can be closer to the post-simulation test results of the real top-level circuit layout.

[0072] Figure 4 is a flow chart of an application scenario of a method for testing a bottom-layer circuit layout according to an exemplary embodiment, such as Figure 4As shown, in order to facilitate the post-simulation test of the bottom circuit layout and the call when it is used to form the top circuit layout, in this application scenario, the current bottom circuit layout adopts a dual layout design method, one of which is used for post-simulation testing, which can be called the post-simulation test layout, and the other is used for calling when forming the top circuit layout, which can be called the call layout. The post-simulation test layout and the call layout are two versions of the current bottom circuit layout used to perform different tasks, and these two versions are completely consistent, but have different uses. When one version is modified, the other version is also modified accordingly, or one version can be modified and the other version can be obtained by copying. Figure 4 As shown, in this application scenario, no other circuits are set around the calling layout, and the top-level circuit layout can directly use the calling layout; the surrounding of the post-simulation test layout can add related circuit structures around it for the post-simulation test of the current bottom-level circuit layout. Figure 4 As shown, in this application scenario: first, the content of other bottom-level circuit layouts (including other bottom-level circuits and related circuits in other bottom-level circuit layouts) is added around the post-simulation test layout, and the content of other bottom-level circuit layouts surrounds the current bottom-level circuit in the post-simulation test layout in the middle, so that the surrounding environment of the functional module of the post-simulation test layout is closer to the environment of the top-level circuit layout; second, the top-level routing (the top-level routing may be the routing connected to the current bottom-level circuit and other bottom-level circuits) is added to the post-simulation test layout, and the top-level routing refers to the routing existing in the top-level circuit layout, so that the post-simulation test of the post-simulation test layout can include the parasitic effects brought by the top-level routing, and the content of other bottom-level circuit layouts and the top-level routing constitute the circuit structure associated with the current bottom-level circuit layout; third, virtual metal is added to the post-simulation test layout, so that the post-simulation test of the post-simulation test layout can include the parasitic effects brought by the virtual metal.

[0073] Figure 5The present invention is a schematic diagram of a post-simulation test layout including associated circuit structures according to an illustrative embodiment, wherein the current bottom-layer circuit layout in the middle part is the bottom-layer circuit layout that needs to be subjected to post-simulation test, and four other bottom-layer circuit layouts are added around it, including a first bottom-layer circuit layout, a second bottom-layer circuit layout, a third bottom-layer circuit layout and a fourth bottom-layer circuit layout, and the vicinity of the current bottom-layer circuit layout also includes a top-layer routing connecting the first bottom-layer circuit layout and the fourth bottom-layer circuit layout, a top-layer routing connecting the second bottom-layer circuit layout and the fourth bottom-layer circuit layout, a top-layer routing connecting the first bottom-layer circuit layout and the third bottom-layer circuit layout, and a top-layer routing connecting the first bottom-layer circuit layout and the current bottom-layer circuit layout, and virtual metal is filled in the space of the current bottom-layer circuit layout that is not occupied by each top-layer routing and each other bottom-layer circuit layout. Among them, any number of the first bottom-level circuit layout, the second bottom-level circuit layout, the third bottom-level circuit layout and the fourth bottom-level circuit layout can be bottom-level circuit layouts that have been designed or circuit layouts in the design process. According to the design status of different bottom-level circuit layouts, the corresponding top-level routing can be planned or pre-planned. For example, if the first bottom-level circuit layout has been designed, the top-level routing connecting the first bottom-level circuit layout and the current bottom-level circuit layout can be a planned top-level routing. If the second bottom-level circuit layout and / or the fourth bottom-level circuit layout are circuit layouts in the design process, the top-level routing connecting the second bottom-level circuit layout and the fourth bottom-level circuit layout can be a pre-planned top-level routing. Figure 5 It can be seen that the surrounding environment of the current bottom circuit layout in the layout after adding other bottom circuit layouts, top routing and virtual metal will be closer to the surrounding environment of the current bottom circuit layout in the final top circuit layout. Therefore, the result of post-simulation test on the post-simulation test layout based on the layout after adding other bottom circuit layouts, top routing and virtual metal can be closer to the post-simulation test result of the top circuit layout. Figure 5 As shown, the first bottom-level circuit layout, the second bottom-level circuit layout, the third bottom-level circuit layout, the fourth bottom-level circuit layout, each top-level routing and virtual metal are represented by dotted lines to indicate that these objects are only used for post-simulation testing of the current bottom-level circuit layout.

[0074] like Figure 4As shown, after adding other bottom circuit layouts, top routing and virtual metal layouts to the post-simulation test layout, perform DRC and LVS of the post-simulation test layout, extract RC parameters of the layout, and post-simulation test of the layout, and the post-simulation test can be modified according to the results of the post-simulation test. When modifying the post-simulation test layout, the calling layout can be modified synchronously to ensure the consistency of the calling layout and the post-simulation test layout. After the post-simulation test of the post-simulation test layout passes, the calling layout can be used to form the top-level circuit layout. This process may include DRC and LVS of the calling layout, assembling the top-level circuit layout, DRC and LVS of the top-level circuit layout, extracting RC parameters of the top-level circuit layout, and post-simulation test of the top-level circuit layout.

[0075] Take the circuit layout (top circuit layout) of the process detector as an example. The circuit layout of the process detector consists of several group layouts, and one group layout consists of several ring oscillators. The parasitic condition of the circuit layout is determined by post-simulation of the frequency of the ring oscillator. The slower the frequency, the larger the parasitic capacitance. See Table 1 for the comparison of post-simulation frequencies.

[0076] Table 1 Comparison of post-simulation frequencies

[0077]

[0078] As shown in Table 1, ring oscillator level: when the circuit has only one ring oscillator, that is, only the bottom circuit is included, because the blank space in the bottom circuit layout containing only one ring oscillator is large, before extracting the RC parameters, the relevant program fills the bottom circuit layout with high-density virtual metal that does not exist in the real situation to meet the DRC requirements. Because the environment of the ring oscillator during the frequency post-simulation test of the bottom circuit layout containing only one ring oscillator is very different from the environment of the ring oscillator in the process detector, the absolute value of the error -A% is the largest among all levels.

[0079] Group layout level: Based on the ring oscillator level, the circuits around the ring oscillator are added to form a group layout. At this time, the frequency post-simulation test is performed on the bottom circuit layout of the ring oscillator. The post-simulation results show that the speed of the ring oscillator will become faster and the frequency will increase. Compared with the frequency post-simulation test results of the top circuit layout of the process detector, it is B% slower, that is, the error is -B%, where the absolute value of the error -B% is smaller than the absolute value of the error -A%.

[0080] Group layout plus top routing level: Add top routing based on the group layout level. At this time, the frequency post-simulation test results of the bottom circuit layout of the ring oscillator show that the speed of the ring oscillator will become faster and the frequency will be further improved. Compared with the frequency post-simulation test results of the top circuit layout of the process detector, the error is C% slower, that is, the error is -C%, where the absolute value of the error -C% is smaller than the absolute value of the error -B%.

[0081] Group layout plus top routing and virtual metal level: Virtual metal is added on the basis of the group layout plus the top routing level. At this time, the frequency post-simulation test results of the bottom circuit layout of the ring oscillator show that the speed of the ring oscillator will become faster and the frequency will be further improved. Compared with the frequency post-simulation test results of the top circuit layout of the process detector, the error is -D%, where the absolute value of the error -D% is smaller than the absolute value of the error -C%.

[0082] Process detector level: This level performs frequency post-simulation testing on the top-level circuit layout of the process detector.

[0083] The comparison result of the error values ​​between the various levels shown in Table 1 is A>B>C>D, among which the post-simulation test result of the group layout plus the top-level routing and virtual metal level is closest to the post-simulation test result of the process detector level. This shows that the test method of the bottom-level circuit layout of the disclosed embodiment can make the post-simulation test result of the bottom-level circuit layout closer to the post-simulation test result of the top-level circuit layout, thereby helping to improve the consistency between the post-simulation test result of the bottom-level circuit layout and the post-simulation test result of the top-level circuit layout, helping to prevent the problem that the bottom-level circuit layout meets the design requirements while the top-level circuit layout cannot meet the design requirements, and helping to improve the development efficiency of the integrated circuit design stage.

[0084] The present disclosure also provides a circuit layout testing method. Figure 6 is a flow chart of a circuit layout testing method according to an exemplary embodiment. Figure 6 As shown, the circuit layout testing method mainly includes the following steps 601 to 603.

[0085] Step 601, executing a test method for a bottom-level circuit layout for at least one of all the bottom-level circuit layouts constituting the top-level circuit layout;

[0086] Step 602: connect all bottom-layer circuit layouts that have passed the post-simulation test through the planned metal interconnection structure and fill them with dummy metal to form a top-layer circuit layout that has been pre-tested for the post-simulation test;

[0087] Step 603: Perform a post-simulation test on the top-level circuit layout to obtain a post-simulation test result of the top-level circuit layout.

[0088] Wherein, what is executed in step 601 is the bottom layer circuit layout testing method of the above-mentioned embodiments.

[0089] Figure 7 is a schematic diagram of a structure of a testing device for a bottom-layer circuit layout according to an exemplary embodiment, such as Figure 7 As shown, the test device of the bottom layer circuit layout mainly includes a layout acquisition module 701, a circuit structure acquisition module 702, a test structure assembly module 703 and a bottom layer layout post-simulation test module 704. Among them, the layout acquisition module 701 is configured to execute the acquisition of the current bottom layer circuit layout for post-simulation test. The circuit structure acquisition module 702 is configured to execute the acquisition of the circuit structure associated with the current bottom layer circuit layout. The test structure assembly module 703 is configured to execute the combination of the current bottom layer circuit layout and the circuit structure and fill the virtual metal to form a post-simulation test structure associated with the current bottom layer circuit layout. The bottom layer layout post-simulation test module 704 is configured to execute the post-simulation test result of the current bottom layer circuit layout by performing the post-simulation test on the current bottom layer circuit layout based on the post-simulation test structure.

[0090] In an exemplary embodiment, the circuit structure includes at least one of other underlying circuit layouts associated with the current underlying circuit layout and metal interconnect structures between the current underlying circuit layout and the other underlying circuit layouts.

[0091] In an illustrative embodiment, the test structure assembly module 703 can be further configured to perform: when other underlying circuit layouts include devices and connecting lines between devices, connecting the current underlying circuit layout with the other underlying circuit layouts through a planned metal interconnection structure; when other underlying circuit layouts only include devices, or when other underlying circuit layouts do not include devices, connecting the current underlying circuit layout with the other underlying circuit layouts through a pre-planned metal interconnection structure.

[0092] In an exemplary embodiment, the dummy metal is filled in the space of the metal interconnect structure not occupied by the circuit structure, and is removed after the post-simulation test of the current bottom layer circuit layout is completed.

[0093] In an exemplary embodiment, the test structure assembly module 703 may be further configured to perform: when the circuit structure does not exist, directly fill virtual metal around the current bottom layer circuit layout to form a post-simulation test structure.

[0094] Regarding the testing device for the underlying circuit layout in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the testing method for the underlying circuit layout, and will not be elaborated here.

[0095] Figure 8 is a schematic diagram of a circuit layout test device according to an exemplary embodiment. Figure 8 As shown, the circuit layout test device mainly includes a bottom-layer circuit layout test device 801, a top-layer circuit layout assembly module 802 and a top-layer layout post-simulation test module 803. Among them, the bottom-layer circuit layout test device 801 is the bottom-layer circuit layout test device of the above embodiment, which is used to perform a post-simulation test of the bottom-layer circuit layout for at least one of all the bottom-layer circuit layouts constituting the top-layer circuit layout. The top-layer circuit layout assembly module 802 is configured to connect all the bottom-layer circuit layouts that have passed the post-simulation test through the planned metal interconnect structure and fill the virtual metal to form a top-layer circuit layout that has been pre-post-simulation tested. The top-layer layout post-simulation test module 803 is configured to perform a post-simulation test on the top-layer circuit layout to obtain a post-simulation test result of the top-layer circuit layout.

[0096] It should be noted that: the above embodiment only illustrates the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0097] Fig. 9 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 900 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 901 and one or more memories 902, wherein the memory 902 stores at least one program code, and the at least one program code is loaded and executed by the processor 901 to implement the test method of the underlying circuit layout and / or the test method of the circuit layout provided by the above-mentioned various embodiments. Of course, the electronic device 900 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 900 may also include other components for implementing device functions, which will not be repeated here.

[0098] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the underlying circuit layout testing method and / or the circuit layout testing method in the above-mentioned embodiment.

[0099] Optionally, the above-mentioned computer-readable storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0100] In an exemplary embodiment, a computer program product is also provided, including a computer program, which, when executed by a processor, implements the underlying circuit layout testing method and / or the circuit layout testing method provided in the above-mentioned embodiments.

[0101] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A method for testing a bottom layer circuit layout, comprising: Obtain the current bottom-layer circuit layout for pre-simulation testing; Acquire a circuit structure associated with the current bottom layer circuit layout, wherein the circuit structure includes at least one of other bottom layer circuit layouts associated with the current bottom layer circuit layout and a metal interconnection structure between the current bottom layer circuit layout and the other bottom layer circuit layouts; The current bottom-layer circuit layout is combined with the circuit structure and filled with virtual metal to form a post-simulation test structure associated with the current bottom-layer circuit layout, wherein the current bottom-layer circuit layout is combined with the circuit structure, including: in the case where the other bottom-layer circuit layouts contain devices and connecting traces between devices, the current bottom-layer circuit layout is connected with the other bottom-layer circuit layouts through a planned metal interconnection structure, wherein the virtual metal is filled in the space of the metal interconnection structure not occupied by the circuit structure; Based on the post-simulation test structure, a post-simulation test result of the current bottom-layer circuit layout is obtained by performing a post-simulation test on the current bottom-layer circuit layout.

2. The method for testing the bottom layer circuit layout according to claim 1, characterized in that: The combining the current bottom layer circuit layout with the circuit structure further includes: When the other bottom-level circuit layout only includes devices, or when the other bottom-level circuit layout does not include devices, the current bottom-level circuit layout is connected to the other bottom-level circuit layout through a pre-planned metal interconnection structure.

3. The method for testing the bottom layer circuit layout according to claim 1, characterized in that: The dummy metal is removed after the post-simulation test of the current bottom layer circuit layout is completed.

4. The method for testing the bottom layer circuit layout according to claim 1, characterized in that: Also includes: In the case that the circuit structure does not exist, the virtual metal is directly filled around the current bottom layer circuit layout to form the post-simulation test structure.

5. A method for testing a circuit layout, comprising: Performing the bottom layer circuit layout testing method as claimed in any one of claims 1 to 4 on at least one of all the bottom layer circuit layouts constituting the top layer circuit layout; Connecting all the bottom-layer circuit layouts that have passed the post-simulation test through the planned metal interconnection structure and filling virtual metal to form the top-layer circuit layout that has been pre-tested; By performing a post-simulation test on the top-level circuit layout, a post-simulation test result of the top-level circuit layout is obtained.

6. A test device for bottom-layer circuit layout, characterized in that: include: A layout acquisition module is configured to execute acquisition of the current bottom layer circuit layout for pre-simulation test; A circuit structure acquisition module is configured to execute acquisition of a circuit structure associated with the current bottom layer circuit layout, wherein the circuit structure includes at least one of other bottom layer circuit layouts associated with the current bottom layer circuit layout and a metal interconnection structure between the current bottom layer circuit layout and the other bottom layer circuit layouts; A test structure assembly module is configured to perform combining the current bottom layer circuit layout with the circuit structure and filling virtual metal to form a post-simulation test structure associated with the current bottom layer circuit layout, wherein the combining the current bottom layer circuit layout with the circuit structure includes: in the case where the other bottom layer circuit layouts contain devices and connecting traces between devices, connecting the current bottom layer circuit layout with the other bottom layer circuit layouts through a planned metal interconnect structure, wherein the virtual metal is filled in the space of the metal interconnect structure not occupied by the circuit structure; The bottom layer layout post-simulation test module is configured to execute a post-simulation test on the current bottom layer circuit layout based on the post-simulation test structure to obtain a post-simulation test result of the current bottom layer circuit layout.

7. A circuit layout testing device, characterized in that: include: The testing device for the bottom layer circuit layout as claimed in claim 6, which is used to perform a post-simulation test of the bottom layer circuit layout for at least one of all the bottom layer circuit layouts constituting the top layer circuit layout; A top-level circuit layout assembly module is configured to connect all the bottom-level circuit layouts that have passed the post-simulation test through the planned metal interconnection structure and fill the virtual metal to form the top-level circuit layout that has been pre-tested for the post-simulation test; The top-level layout post-simulation test module is configured to perform a post-simulation test on the top-level circuit layout to obtain a post-simulation test result of the top-level circuit layout.

8. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the bottom layer circuit layout testing method according to any one of claims 1 to 4 and / or the circuit layout testing method according to claim 5.

9. A computer-readable storage medium, characterized in that: When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the testing method of the underlying circuit layout as described in any one of claims 1 to 4 and / or the testing method of the circuit layout as described in claim 5.

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