A clock circuit suitable for DDRPHY

Abstract

The purpose of the present invention is to provide a clock circuit suitable for DDRPHY, the circuit comprising: a duty cycle detection module and an analog duty cycle calibration module; the duty cycle detection module is located in the analog IO module, and is used to detect the duty cycle of the high-speed signal; the analog duty cycle calibration module is located outside the analog IO module and is connected to the duty cycle detection module, and is used to calibrate the positive and negative ends of the analog comparator. The present invention can make the clock bifurcate at the last level, and send even data and odd data to the analog IO. At the same time, through the duty cycle detection module, in combination with digital control logic, the circuit workload of the clock is guaranteed, and the timing margin of the data is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a clock circuit suitable for DDRPHY. Background Art

[0002] With the requirements for storage bandwidth speed, the rate of DDR continues to rise, and the internal clock frequency of the memory signal interface is also increased synchronously. At present, the information transmission rate of LPDDR5X particles is generally 8533Mbps, and the maximum can reach 9600Mbps. There are generally two ways for the internal high-speed clock of DDRPHY in the industry, namely full mode and half mode. If the full mode structure is adopted, the internal high-speed clock cycle of the memory signal interface is equal to 1UI, then the internal high-speed clock frequency of the memory signal interface is 8.5G. The speed is too high. On the one hand, digital timing convergence is very difficult, and on the other hand, the internal power consumption will increase a lot, and the clock quality is not easy to guarantee. Therefore, for DDRPHY, at such a high rate, the halfmode structure is adopted to make the high-speed clock frequency inside the chip of the external signal interface equal to half of the information transmission rate, that is, the internal high-speed clock of the chip of the lpddr5x external signal interface is 4.2G. Compared with full mode, reducing the clock frequency can also improve indicators such as PPA.

[0003] For half mode, the internal clock needs to have two clocks that respectively generate rising and falling edges, and after parallel-to-serial conversion, synthesize an 8533Mbps information transmission rate to match the dynamic random access memory particles. Currently, there is a phase-locked loop that is calibrated by the probe time deviation, which allows the phase-locked loop to generate two 4.2G clocks, one as the clock that generates the rising edge, and the other as the clock that generates the falling edge. In this way, the clock bifurcation is relatively early, and the clock path offset requirements are relatively strict. The clock deviation will have a relatively large impact on the circuit workload of the rising and falling edges sent from the digital to the analog later, resulting in insufficient data timing margin on the transmission path. There is also a digital clock architecture, and finally the rising and falling edges are converted from parallel to serial in the digital part and sent to the IO for output. In this way, it is difficult for the digital to grasp the duty cycle of the data sent to the IO after the rising and falling edges are merged at the last level, resulting in a deviation in the timing margin of the final IO output, and even failing to meet the specifications of the dynamic random access memory. The early clock bifurcation will result in a relatively large open circuit voltage, and the delay of different clocks will affect the timing margin sent to the IO later. If the bifurcation is at the last level, the digital part converts the rising and falling edges into serial signals and sends them to the IO. After passing through the selector inverter, it will affect the duty cycle of the high-speed signal, and even the data signal sent out may not meet the specifications of the dynamic random access memory. Summary of the invention

[0004] The purpose of the present invention is to provide a clock circuit suitable for DDRPHY, which can make the clock bifurcate at the last level, output even data and odd data to analog IO, and at the same time, through a duty cycle detection module and digital control logic, ensure the circuit workload of the clock and make the timing margin of the data reach the best.

[0005] A clock circuit suitable for DDRPHY, comprising: a duty cycle detection module and an analog duty cycle calibration module;

[0006] The duty cycle detection module is located in the analog IO module and is used to detect the duty cycle of the high-speed signal;

[0007] The analog duty cycle calibration module is located outside the analog IO module and connected to the duty cycle detection module, and is used to calibrate the positive and negative terminals of the analog comparator.

[0008] Preferably, it also includes: a digital logic control module;

[0009] The input end of the digital logic control module is connected to the output end of the duty cycle detection module;

[0010] The output end of the digital logic control module is connected to the input end of the analog duty cycle calibration module;

[0011] The digital logic control module is used to generate an adjustment code according to the output of the duty cycle detection module, and send the adjustment code to the duty cycle calibration module.

[0012] Preferably, it further comprises: a phase-locked loop, a first trigger, a second trigger, a first NOT gate and an analog IO module;

[0013] The output end of the phase-locked loop is connected to the input end of the analog duty cycle calibration module;

[0014] The Q terminal of the first trigger is connected to the analog IO module;

[0015] The Q terminal of the second trigger is connected to the analog IO module;

[0016] The CK terminal of the first trigger is connected to the input terminal of the first NOT gate;

[0017] The output terminal of the first NOT gate is connected to the CK terminal of the second flip-flop;

[0018] An input end of the duty cycle detection module is connected to a CK end of the first trigger and an input end of the first NOT gate.

[0019] Preferably, the duty cycle detection module comprises: a filtering module and a detection module;

[0020] The filtering module is connected to the detection module, and includes: a first capacitor, a first inductor, a first resistor, and a second capacitor;

[0021] The upper plate of the first capacitor and the first end of the first inductor are both connected to the surge protection module, and the second end of the first capacitor is grounded;

[0022] The second end of the first inductor is grounded via a third capacitor, and the second end of the first inductor is connected to a substrate gating module;

[0023] The upper plate of the second capacitor is connected to the first inductor, and the lower plate is grounded;

[0024] A first end of the first resistor is connected to an upper plate of the second capacitor, and a second end of the first resistor is connected to the first inductor.

[0025] Preferably, the detection module comprises: a first detection branch and a second detection branch;

[0026] The first detection branch is controlled by the low level of the clock signal passing through the filtering module and is used to detect the high level of the clock signal;

[0027] The second detection branch is controlled by the inverted signal of the clock signal passing through the filtering module, and is used to detect the low level of the clock signal.

[0028] Preferably, the analog duty cycle calibration module comprises: a second resistor, a third resistor, a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, a second NOT gate, a third NOT gate and a first comparator;

[0029] The second resistor is connected in parallel with the third capacitor and connected to the third resistor;

[0030] The third resistor is connected in parallel with the second NOT gate;

[0031] A first end of the third capacitor is connected to CKP, and a second end is connected to an input end of the second NOT gate;

[0032] A first end of the fourth capacitor is connected to CKN, and a second end is connected to an input end of the third NOT gate;

[0033] The fourth resistor is connected in parallel with the fourth capacitor and connected to the fifth resistor;

[0034] The fifth resistor is connected to the third NOT gate;

[0035] The output terminal of the second NOT gate is connected to the positive input terminal of the first comparator;

[0036] The output terminal of the third NOT gate is connected to the negative input terminal of the first comparator.

[0037] A clock circuit control method applicable to DDRPHY, comprising:

[0038] Start the phase-locked loop to half the information transmission rate;

[0039] The digital logic control module generates an adjustment code according to the output of the duty cycle detection module;

[0040] The duty cycle calibration module performs duty cycle calibration according to the adjustment code.

[0041] Preferably, after the phase-locked loop is started to oscillate to half of the information transmission rate, the method further comprises:

[0042] The duty cycle detection module performs self-calibration to calibrate the positive and negative terminals of the comparator;

[0043] The digital logic control module determines whether the output of the duty cycle detection module reaches a calibration target according to the output of the duty cycle detection module.

[0044] An electronic device comprises: a chip, a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a clock circuit control method applicable to DDRPHY.

[0045] The beneficial effects of the present invention are: 1. The present invention samples half mode, so that the internal clock frequency of the memory signal interface is reduced to half of the signal transmission rate, which solves the technical problem of the difficulty in converging the internal high-speed clock frequency of the memory signal interface, and can also reduce internal power consumption; 2. The present invention makes the clock bifurcate at the last level, the OCV effect is small, and the deviation of the rising edge and the falling edge is guaranteed to be small; 3. The present invention adds a duty cycle detection module and a duty cycle calibration module, so that the timing margin of the data signal sent out on the rising edge and the falling edge is sufficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0048] Figure 1 A clock circuit structure diagram applicable to DDRPHY of the present invention;

[0049] Figure 2 It is a schematic diagram of the circuit structure of the filter module of the present invention;

[0050] Figure 3 It is a schematic diagram of the circuit structure of the detection module of the present invention;

[0051] Figure 4 It is a schematic diagram of the circuit structure of the analog duty cycle calibration module of the present invention;

[0052] Figure 5 A schematic flow chart of a clock circuit control method applicable to DDRPHY of the present invention;

[0053] Figure 6 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] For half mode, the internal clock needs to have two clocks that respectively generate rising and falling edges, and after parallel-to-serial conversion, synthesize an 8533Mbps information transmission rate to match the dynamic random access memory particles. Currently, there is a phase-locked loop that is calibrated by the probe time deviation, which allows the phase-locked loop to generate two 4.2G clocks, one as the clock that generates the rising edge, and the other as the clock that generates the falling edge. In this way, the clock bifurcation is relatively early, and the clock path offset requirements are relatively strict. The clock deviation will have a relatively large impact on the circuit workload of the rising and falling edges sent from the digital to the analog later, resulting in insufficient data timing margin on the transmission path. There is also a digital clock architecture, and finally the rising and falling edges are converted from parallel to serial in the digital part and sent to the IO for output. In this way, it is difficult for the digital to grasp the duty cycle of the data sent to the IO after the rising and falling edges are merged at the last level, resulting in a deviation in the timing margin of the final IO output, and even failing to meet the specifications of the dynamic random access memory. The early clock bifurcation will result in a relatively large open circuit voltage, and the delay of different clocks will affect the timing margin sent to the IO later. If the bifurcation is at the last level, the digital part converts the rising and falling edges into serial signals and sends them to the IO. After passing through the selector inverter, it will affect the duty cycle of the high-speed signal, and even the data signal sent out may not meet the specifications of the dynamic random access memory.

[0058] The present invention samples half mode, so that the internal clock frequency of the memory signal interface is reduced to half of the signal transmission rate, thereby solving the technical problem of the difficulty in converging the internal high-speed clock frequency of the memory signal interface and reducing the internal power consumption; the present invention makes the clock bifurcate at the last level, the OCV effect is small, and the deviation of the rising edge and the falling edge is guaranteed to be small; the present invention adds a duty cycle detection module and a duty cycle calibration module, so that the timing margin of the data signal sent out at the rising edge and the falling edge is sufficient.

[0059] Example 1

[0060] A clock circuit suitable for DDRPHY, reference Figure 1 , including: a duty cycle detection module and an analog duty cycle calibration module;

[0061] The duty cycle detection module is located in the analog IO module and is used to detect the duty cycle of the high-speed signal;

[0062] The analog duty cycle calibration module is located outside the analog IO module and is connected to the duty cycle detection module, and is used to calibrate the positive and negative terminals of the analog comparator.

[0063] The present invention adopts a half mode structure. If the highest frequency of the chip of the external signal interface is 8533Mbps, the clock frequency of the internal phase-locked loop is 4266Mbps. The clock bifurcation is at the last digital level to ensure that the OCV has little impact. Since the even and odd data will be sent out using the rising and falling edges of the main core clock, in order to solve the timing margin problem of the dataeven and dataodd data signals at the transmitting end, a duty cycle detection module and an external analog duty cycle calibration module are added to the analog IO. At the same time, digital control logic is added to generate a corresponding adjustment code code according to the output of the duty cycle detection module and send it to the duty cycle calibration module. In this way, the half mode structure is adopted to reduce the internal clock of the chip of the external signal interface to half of the data transmission rate, solve the problem of early clock bifurcation, and ensure the timing margin of the data sent out on the rising and falling edges.

[0064] Preferably, it also includes: a digital logic control module;

[0065] The input end of the digital logic control module is connected to the output end of the duty cycle detection module;

[0066] The output end of the digital logic control module is connected to the input end of the analog duty cycle calibration module;

[0067] The digital logic control module is used for generating an adjustment code according to the output of the duty cycle detection module and sending the adjustment code to the duty cycle calibration module.

[0068] The digital logic control module is an electronic module that coordinates and controls the data flow and signal transmission between various components in the system to achieve coordinated and safe system operation. The logic control module is usually implemented in a digital way, and various logic operation rules can be preset so that the system can automatically analyze and judge different operating states, thereby adopting corresponding control strategies.

[0069] The functions of the digital logic control module mainly include data processing, signal conversion, integrated control, etc. In terms of data processing, the logic control module can process, classify, and filter system data to ensure the correctness and reliability of the data; in terms of signal conversion, the digital logic control module can convert the signals between different components into signals that the system can recognize and perform corresponding control; in terms of integrated control, the digital logic control module can coordinate the operating status of various system components to ensure smooth system operation.

[0070] In this embodiment, the digital logic control module is mainly responsible for generating an adjustment code based on the duty cycle detection result output by the duty cycle detection module and sending it to the duty cycle calibration module. If the duty cycle detection result of the duty cycle detection module does not meet the preset standard, for example, the duty cycle is too large or too small, then the digital logic control module will send the corresponding adjustment code to the duty cycle calibration module to help the duty cycle calibration module to adjust the duty cycle more accurately. If the duty cycle detection result output by the duty cycle detection module meets the preset standard, then there is no need to send the adjustment code, which can save energy more effectively.

[0071] Preferably, it further comprises: a phase-locked loop, a first trigger, a second trigger, a first NOT gate and an analog IO module;

[0072] The output end of the phase-locked loop is connected to the input end of the analog duty cycle calibration module;

[0073] A phase-locked loop is a negative feedback control system that can use the voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency. It is mainly composed of components such as a phase detector, a loop filter, and a voltage-controlled oscillator. The frequency and phase of the oscillation signal inside the loop are controlled by an external reference signal to achieve automatic tracking of the output signal frequency to the input signal frequency. Phase-locked loops are generally used in closed-loop tracking circuits and are a method of making the frequency more stable in radio transmission. Its main components include: Phase detector: responsible for comparing the phase difference between the output signal and the input signal, and outputting a signal representing the difference between the two to a low-pass filter. Loop filter: has a low-pass characteristic, which is used to maintain loop stability, suppress in-band and out-of-band spurious signals, and phase-locked loop lock time. Its main parameters include loop bandwidth and phase margin, and the selection of these parameters will affect the performance of the phase-locked loop. Voltage-controlled oscillator (VCO): outputs a periodic signal whose frequency is controlled by the input voltage. After the output of the VCO is collected and divided, it is simultaneously input into the phase detector for comparison with the reference signal, and phase synchronization is achieved in this way.

[0074] The working principle of the phase-locked loop is based on phase comparison and negative feedback mechanism. It detects the phase difference between the input signal and the output signal, and converts the detected phase difference signal into a voltage signal for output. This voltage signal is filtered by the loop filter to form the control voltage of the voltage-controlled oscillator, and the frequency of the oscillator output signal is controlled to achieve the purpose of phase locking. The phase-locked loop can realize the automatic tracking of the output signal frequency to the input signal frequency, and is widely used in frequency synthesis, clock distribution, phase demodulation, clock recovery and other fields.

[0075] The Q terminal of the first trigger is connected to the analog IO module;

[0076] The Q terminal of the second trigger is connected to the analog IO module;

[0077] The CK terminal of the first trigger is connected to the input terminal of the first NOT gate;

[0078] A flip-flop is a memory device that stores a bit and can change its state under given conditions. A flip-flop consists mainly of several logic gates, any of which can be driven by the input signal of the flip-flop. The output of the logic gate is connected to other logic gates and / or storage capacitors. The input signal causes the state of the logic gate output to change, which in turn causes the voltage value of the storage capacitor to change. When a clock signal arrives, the voltage value of the capacitor (and the digital state it represents) is copied to the output and maintained.

[0079] The output terminal of the first NOT gate is connected to the CK terminal of the second flip-flop;

[0080] The logical function of the NOT gate is equivalent to the NOT operation in logic algebra, and the circuit function is equivalent to inversion. When the input of the NOT gate is high (logic 1), the output is low (logic 0); when the input is low, the output is high, that is, the level states of the input and output are always inverted.

[0081] The input end of the duty cycle detection module is connected to the CK end of the first trigger and the input end of the first NOT gate.

[0082] Preferably, reference Figure 2 ,The duty cycle detection module includes: a filtering module and a detection module;

[0083] The filter module is connected to the detection module, and includes: a first capacitor, a first inductor, a first resistor, and a second capacitor;

[0084] The upper plate of the first capacitor and the first end of the first inductor are both connected to the surge protection module, and the second end of the first capacitor is grounded;

[0085] The second end of the first inductor is grounded through the third capacitor, and the second end of the first inductor is connected to the substrate gating module;

[0086] The upper plate of the second capacitor is connected to the first inductor, and the lower plate is grounded;

[0087] The first end of the first resistor is connected to the upper plate of the second capacitor, and the second end of the first resistor is connected to the first inductor.

[0088] As an important linear system in communication systems, filters are not limited to the field of signal processing, but also play a key role in many aspects. First of all, filters can effectively shape the waveform and spectrum of the input signal, and the waveform and spectrum of the output signal are also shaped. This characteristic makes filters play a vital role in communication systems, especially in changing the time domain and frequency domain characteristics of signals. One of the core functions of filters is to remove noise and extract signals of interest from a large number of signals. This is achieved through two main types of filters: analog filters and digital filters. Analog filters use the characteristics of components such as capacitors and inductors to suppress unwanted frequency components by passing high frequencies to block low frequencies or reflecting high-frequency interference currents. Digital filters process digital signals through algorithms to achieve the purpose of filtering out noise and extracting signals. In addition, the application of filters also includes improving the anti-interference and signal-to-noise ratio of signals, filtering out frequency components of no interest to improve analysis accuracy, and separating single frequency components from complex frequency components. These functions make filtering modules widely used in many fields such as communication, audio processing, and image processing.

[0089] In the process of charging and discharging the capacitor in the embodiment of the present invention, when the rectified voltage is higher than the capacitor voltage, the capacitor is charged; when the rectified voltage is lower than the capacitor voltage, the capacitor is discharged. Through this charging and discharging process, the capacitor can smooth the output voltage, thereby providing a stable DC voltage. The advantage of capacitor filtering is that it has stable working performance and can provide a stable DC voltage output, which is conducive to the normal operation of electronic equipment.

[0090] Preferably, reference Figure 3 , the detection module includes: a first detection branch and a second detection branch;

[0091] The first detection branch is controlled by the low level of the clock signal passing through the filtering module and is used to detect the high level of the clock signal;

[0092] The second detection branch is controlled by the inverted signal of the clock signal passing through the filtering module, and is used to detect the low level of the clock signal.

[0093] Duty cycle refers to the proportion of time that a signal is in an effective state (such as high or low) in a complete cycle. This proportion is usually expressed as a percentage. For example, if the signal is in a high state for half of the time in a cycle, the duty cycle is 50%. Duty cycle is widely used in the design of various electronic devices and systems, such as power control, PWM signal modulation, etc. In PWM technology, the duty cycle is changed by adjusting the pulse width to control the output of the circuit. This technology allows electronic devices to control loads with higher precision, such as the brightness of a lamp, the speed of a motor, etc. By adjusting the pulse width (that is, the length of time the switch is turned on), the duty cycle can be changed to accurately control the output power of the load. The larger the duty cycle, the higher the average output voltage or current, which in turn controls the brightness of the lamp, the speed of the motor, etc. In some applications, such as power management chips, frequency modulation (FM) and width modulation (PWM) techniques are used simultaneously. When the frequency remains fixed, the duty cycle is changed by adjusting the pulse width to achieve precise voltage and current control. The duty cycle changes the proportion of the effective time of the signal in a cycle by adjusting the pulse width, thereby achieving precise control and regulation functions. Its duty cycle detection module is responsible for detecting the duty cycle error, and the duty cycle calibration module is responsible for adjusting the duty cycle of the clock.

[0094] Preferably, reference Figure 4 , the analog duty cycle calibration module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, a second NOT gate, a third NOT gate and a first comparator;

[0095] The second resistor is connected in parallel with the third capacitor and connected to the third resistor;

[0096] The third resistor is connected in parallel with the second NOT gate;

[0097] A first end of the third capacitor is connected to CKP, and a second end is connected to an input end of the second NOT gate;

[0098] A first end of the fourth capacitor is connected to CKN, and a second end is connected to an input end of the third NOT gate;

[0099] The fourth resistor is connected in parallel with the fourth capacitor and connected to the fifth resistor;

[0100] The fifth resistor is connected to the third NOT gate;

[0101] An output terminal of the second NOT gate is connected to a positive input terminal of the first comparator;

[0102] The output terminal of the third NOT gate is connected to the negative input terminal of the first comparator.

[0103] With the continuous upgrading of integrated circuit technology, the operating speed and throughput of chips are constantly improving, and the quality requirements for clocks will also be higher. Among them, the clock duty cycle is an important indicator of high-speed clocks. The high-speed clock output from the phase-locked loop will cause the clock duty cycle to deteriorate due to process mismatch, long-distance transmission and circuit design mismatch. Therefore, the design of the clock duty cycle calibration circuit is a key technology for the chip. The existing clock calibration methods mainly include digital clock calibration and analog clock calibration. Among them, digital clock calibration is usually unable to achieve high-speed and high-precision clock calibration due to the constraints of the delay unit. In an embodiment of the present invention, the analog duty cycle calibration module is used to adjust or calibrate the accuracy of the duty cycle detection circuit. It includes a reference voltage source, a comparator and an adjustment element. By comparing the duty cycle output by the detection circuit with the preset reference value, precise adjustment is performed to ensure the accuracy and stability of the duty cycle detection. The duty cycle calibration circuit compares the duty cycle output by the detection circuit with the preset reference value, and then adjusts the circuit parameters so that the output duty cycle can accurately match the reference value. In this way, the accuracy and stability of the circuit can be ensured when measuring and controlling periodic signals.

[0104] Example 2

[0105] A clock circuit control method suitable for DDRPHY, reference Figure 5 ,include:

[0106] S100, start the phase-locked loop to half the information transmission rate;

[0107] Start the phase-locked loop to half of the information transfer rate. If the LPDDR5X target is 8533Mbps, then start the phase-locked loop to 4.2G.

[0108] S200, the digital logic control module generates an adjustment code according to the output of the duty cycle detection module;

[0109] The digital control logic sends out the duty cycle adjustment code to calibrate the duty cycle, and then continuously determines whether the duty cycle reaches 50 percent based on the high and low levels of the output signal of the duty cycle detection module.

[0110] S300: The duty cycle calibration module performs duty cycle calibration according to the adjustment code.

[0111] If the duty cycle calibration module receives the adjustment code, it means that the duty cycle has not reached 50% or exceeds 50%. The duty cycle calibration module needs to calibrate the duty cycle according to the adjustment code output by the digital control logic module, and then send the calibrated duty cycle to the duty cycle detection module for detection again until the output of the duty cycle detection module jumps, indicating that the duty cycle has been adjusted to around 50%.

[0112] Preferably, after S100, starting the phase-locked loop to half the information transmission rate, the method further includes:

[0113] S110, the duty cycle detection module performs self-calibration to calibrate the positive and negative terminals of the comparator;

[0114] Self-calibration of a duty cycle detection circuit refers to the ability of the circuit to automatically adjust or calibrate its duty cycle detection function during operation to ensure long-term stability and accuracy. This is usually achieved through an internal feedback mechanism, that is, the circuit automatically monitors the duty cycle of its output and compares and adjusts it based on a preset reference value. This self-calibration can improve the circuit's adaptability to changing environmental conditions and ensure that it can still provide accurate duty cycle measurements under different operating conditions. The self-calibration of the duty cycle detection circuit usually relies on internal feedback mechanisms and specific circuit designs. The self-calibration module includes: Internal feedback mechanism: A feedback path is set inside the circuit to monitor the actual output duty cycle. Reference value comparison: The circuit compares the actual output duty cycle with a preset reference value. Adjust circuit parameters: If the output duty cycle is detected to not match the preset reference value, the circuit automatically adjusts internal parameters or calibration components to make the output duty cycle close to the expected reference value. Stability and accuracy: This automatic calibration ensures that the circuit maintains stability and measurement accuracy over long periods of operation, even if it is affected by factors such as temperature changes, power supply fluctuations, or device aging. The specific implementation will vary depending on the complexity of the circuit and the design requirements, but the core goal is to automatically adjust the duty cycle detection circuit so that it can provide reliable performance under various operating conditions.

[0115] The steps for calibrating the positive and negative terminals of a comparator include: Using a known stable voltage source or signal generator, ensure that the non-inverting terminal (positive terminal) and the inverting terminal (negative terminal) of the comparator receive the correct reference voltage. Adjust the bias voltage of the comparator: The comparator may have a potentiometer or calibration circuit to adjust the bias voltage of the non-inverting terminal or the inverting terminal. By adjusting these circuits, ensure that the comparator responds correctly when the input signal reaches or exceeds the threshold. Adjust the threshold of the comparator: The threshold of the comparator determines the voltage level at which its output state changes. Depending on the needs of the specific application, adjust the threshold to ensure that the comparator triggers at the correct voltage point. After completing the calibration, you can also perform stability testing to verify the performance and stability of the comparator under different conditions such as temperature and power supply changes.

[0116] S120, the digital logic control module determines whether the output of the duty cycle detection module reaches a calibration target according to the output of the duty cycle detection module.

[0117] The digital logic control module determines whether the self-calibration of the duty cycle detection module reaches the calibration target by checking the output of the duty cycle detection module, thereby avoiding the detection error caused by the self-calibration error of the duty cycle detection module and being able to adjust the duty cycle more accurately.

[0118] Example 3

[0119] An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program codes, the computer program codes include computer instructions, and when the chip executes the computer instructions, the electronic device executes a clock circuit control method suitable for DDRPHY.

[0120] refer to Figure 6 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0121] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0122] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0123] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0124] The present invention samples half mode, so that the internal clock frequency of the memory signal interface is reduced to half of the signal transmission rate, thereby solving the technical problem of the difficulty in converging the internal high-speed clock frequency of the memory signal interface and reducing the internal power consumption; the present invention makes the clock bifurcate at the last level, the OCV effect is small, and the deviation of the rising edge and the falling edge is guaranteed to be small; the present invention adds a duty cycle detection module and a duty cycle calibration module, so that the timing margin of the data signal sent out at the rising edge and the falling edge is sufficient.

[0125] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A clock circuit suitable for DDRPHY, characterized in that: include: A duty cycle detection module, a digital control logic module and an analog duty cycle calibration module; The duty cycle detection module is located in the analog IO module, the input end of the duty cycle detection module is connected to the output end of the analog duty cycle calibration module, and the output end is connected to the digital control logic module, and is used to detect the duty cycle of the high-speed signal; The analog duty cycle calibration module is located outside the analog IO module, and the input end of the analog duty cycle calibration module is connected to the phase-locked loop output signal, and is used to calibrate the positive and negative ends of the first comparator in the analog duty cycle calibration module; The duty cycle detection module includes: a filtering module and a detection module; The filtering module is connected to the analog duty cycle calibration module; The detection module is connected with the filter module and the digital control logic module; The analog duty cycle calibration module includes: a second resistor, a third resistor, a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, a second NOT gate, a third NOT gate and a first comparator; The second resistor is connected in parallel with the third capacitor and connected to the third resistor; The third resistor is connected in parallel with the second NOT gate; A first end of the third capacitor is connected to CKP, and a second end is connected to an input end of the second NOT gate; A first end of the fourth capacitor is connected to CKN, and a second end is connected to an input end of the third NOT gate; The fourth resistor is connected in parallel with the fourth capacitor and connected to the fifth resistor; The fifth resistor is connected to the third NOT gate; The output terminal of the second NOT gate is connected to the positive input terminal of the first comparator; The output terminal of the third NOT gate is connected to the negative input terminal of the first comparator; The output end of the first comparator is connected to the duty cycle detection module; The input end of the digital control logic module is connected to the output end of the duty cycle detection module; The output end of the digital control logic module is connected to the input end of the analog duty cycle calibration module; The digital control logic module is used to generate an adjustment code according to the output of the duty cycle detection module, and send the adjustment code to the analog duty cycle calibration module.

2. A clock circuit suitable for DDRPHY according to claim 1, characterized in that: Also includes: A phase-locked loop, a first trigger, a second trigger, a first NOT gate and an analog IO module; The output end of the phase-locked loop is connected to the input end of the analog duty cycle calibration module; The Q terminal of the first trigger is connected to the analog IO module; The Q terminal of the second trigger is connected to the analog IO module; The CK terminal of the first trigger is connected to the input terminal of the first NOT gate; The output terminal of the first NOT gate is connected to the CK terminal of the second flip-flop; An input end of the duty cycle detection module is connected to a CK end of the first trigger and an input end of the first NOT gate.

3. A clock circuit suitable for DDRPHY according to claim 1, characterized in that: The duty cycle detection module includes: a filtering module and a detection module; The filtering module is connected to the detection module, and includes: a first capacitor, a first inductor, a first resistor, and a second capacitor; The upper plate of the first capacitor and the first end of the first inductor are both connected to the surge protection module, and the second end of the first capacitor is grounded; The second end of the first inductor is grounded via a third capacitor, and the second end of the first inductor is connected to a substrate gating module; The upper plate of the second capacitor is connected to the first inductor, and the lower plate is grounded; A first end of the first resistor is connected to an upper plate of the second capacitor, and a second end of the first resistor is connected to the first inductor.

4. A clock circuit suitable for DDRPHY according to claim 1, characterized in that: The detection module comprises: a first detection branch and a second detection branch; The first detection branch is controlled by the low level of the clock signal passing through the filtering module and is used to detect the high level of the clock signal; The second detection branch is controlled by the inverted signal of the clock signal passing through the filtering module, and is used to detect the low level of the clock signal.

5. A clock circuit control method applicable to DDRPHY, applied to a clock circuit applicable to DDRPHY as claimed in any one of claims 1 to 4, characterized in that: include: Start the phase-locked loop to half the information transmission rate; The digital control logic module generates an adjustment code according to the output of the duty cycle detection module; The analog duty cycle calibration module performs duty cycle calibration according to the adjustment code.

6. A clock circuit control method applicable to DDRPHY according to claim 5, characterized in that: After the phase-locked loop is started to oscillate to half the information transmission rate, it also includes: The duty cycle detection module performs self-calibration to calibrate the positive and negative terminals of the first comparator; The digital control logic module determines whether the output of the duty cycle detection module reaches a calibration target according to the output of the duty cycle detection module.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions. When the chip executes the computer instructions, the electronic device executes a clock circuit control method applicable to DDRPHY as described in any one of claims 5 to 6.

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