Data mapping device and method for fine-grained optical transport network based on FPGA

Abstract

The present application discloses a data mapping device for a fine-grained optical transport network based on FPGA. The clock generation module generates an ODUk clock enable signal corresponding to each ODUk channel number. The frame structure generation module generates a corresponding ODUk frame structure based on the ODUk clock enable signal. The time slot search module determines the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and the overhead byte corresponding to each fgTSOH. The signal mapping module maps the fgODUflex data frames of each fgODUflex channel number to each fgTS of OPUk in the ODUk frame structure, and maps the overhead byte corresponding to each fgTSOH to OPUk, thereby obtaining ODUk data frames of multiple ODUk channel numbers, thereby saving FPGA system resources.

Description

Technical Field

[0001] The present application relates to the technical field of fine-grained optical transport networks, and in particular to a data mapping device and method for a fine-grained optical transport network based on FPGA. Background Art

[0002] Fine Grain Optical Transport Network (fgOTN) is the technological evolution of SDH (ITU-TG.707) and OTN (ITU-G.709). It perfectly inherits the high reliability and deterministic latency characteristics of SDH and OTN (Optical Transport Network), supports a variety of VBR (variable bit rate) and CBR (constant bit rate) services such as Ethernet, E1, SDH, etc., and can provide a secure hard isolation solution based on rigid hard pipes for quality connections. It can be widely used in operators' government and enterprise dedicated lines, as well as private networks in industries such as electricity and transportation.

[0003] The fine-grained optical transport network adopts a fixed time slot allocation design with 10Mb / s bandwidth as the unit to meet the needs of small-grained services to achieve high reliability and deterministic time-delay transmission of small-grained services with the least resources. In order to realize multiple ODUk (Optical Data Unit-k, optical channel data unit k) to support mapping of up to n*952 fgODUflex (FineGrain Optical Data Unit Flex, fine-grained flexible optical data unit) channels, if the traditional general mapping procedure circuit is used, the circuit needs to be copied 952 times, resulting in huge FPGA resource usage and complex implementation solutions. Summary of the invention

[0004] The purpose of the present application is to provide a data mapping device for a fine-grained optical transport network based on FPGA, which uses time division multiplexing to map multi-channel fgODUflex data frames into multiple ODUk containers on a data bus, saving FPGA system resources.

[0005] In a first aspect, the present application provides a data mapping device for a fine-grained optical transport network based on FPGA, the device comprising:

[0006] A cache module, used for caching fgODUflex data frames of multiple fgODUflex channels;

[0007] The clock generation module includes at least one clock enable unit, which is used to process the system clock and the external clock according to the configured ODUk rate level k for each clock enable unit to obtain the ODUk clock enable signal under the system clock, and then obtain the ODUk clock enable signal corresponding to each ODUk channel number under the system clock, and use each ODUk clock enable signal to occupy the same data bus in a time division multiplexing form, where k=0, 1, 2, or flex;

[0008] The frame structure generation module is used to perform the following processing for each clock cycle of the system clock: determine the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, perform byte counting in response to the ODUk clock enable signal, and then generate an ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained based on the byte counting of each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number;

[0009] The time slot search module is used to perform the following processing for each clock cycle of the system clock: based on the ODUk channel number corresponding to the current clock cycle and the ODUk clock enable signal, determine the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and determine the overhead byte corresponding to each fgTSOH in the ODUk frame structure;

[0010] The signal mapping module is used to read the corresponding fgODUflex data frame from the cache module for each ODUk channel number according to the fgODUflex channel numbers corresponding to the fgTS in the ODUk frame structure of the ODUk channel number, and map it to the fgTS in the ODUk frame structure, and map the overhead byte to the fgTSOH in the ODUk frame structure to obtain the ODUk data frame of the ODUk channel number.

[0011] In a second aspect, the present application provides a data mapping method for a fine-grained optical transport network based on FPGA, the method comprising:

[0012] Buffer fgODUflex data frames of multiple fgODUflex channels;

[0013] According to the configured ODUk rate level k, the system clock and the external clock are processed to obtain the ODUk clock enable signal under the system clock, and then the ODUk clock enable signal corresponding to each ODUk channel number under the system clock is obtained, and each ODUk clock enable signal occupies the same data bus in the form of time division multiplexing, where k=0, 1, 2, or flexn, flexn=3~7;

[0014] For each clock cycle of the system clock, the following processing is performed: determining the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, performing byte counting in response to the ODUk clock enable signal, and then generating an ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained based on performing byte counting on each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number;

[0015] For each clock cycle of the system clock, the following processing is performed: based on the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number is determined, and the overhead byte corresponding to each fgTSOH in the ODUk frame structure is determined;

[0016] For each ODUk channel number, according to the fgODUflex channel numbers corresponding to the fgTS in the ODUk frame structure of the ODUk channel number, the corresponding fgODUflex data frame is read from the cache module and mapped to the corresponding fgTS in the ODUk frame structure, and the overhead byte is mapped to the corresponding fgTSOH in the ODUk frame structure to obtain the ODUk data frame of the ODUk channel number.

[0017] In a third aspect, the present application provides a communication device, including the data mapping device of the fine-grained optical transport network based on FPGA as described above.

[0018] In the present application, each ODUk clock enable signal occupies the same data bus in a time-division multiplexing form. Based on the data bus, an ODUk frame structure of each ODUk channel number is generated by time-division multiplexing, and the fgODUflex channel number corresponding to each fgTS of OPUk in the ODUk frame structure is determined, and the overhead byte corresponding to each fgTSOH of OPUk is determined, and the fgODUflex data frame of each fgODUflex channel number is mapped to each fgTS of OPUk in the ODUk frame structure, and the overhead byte corresponding to each fgTSOH is mapped to OPUk, thereby obtaining ODUk data frames of multiple ODUk channel numbers, and the signal can be mapped to ODUk containers of any multiple channels. The design scheme is flexible and can save FPGA system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A system block diagram of a data mapping device for a fine-grained optical transport network based on FPGA provided in an embodiment of the present application;

[0020] Figure 2 A system block diagram of a clock generation module provided in the first embodiment of the present application;

[0021] Figure 3 A schematic diagram of the ODU2 / ODU1 / ODU0 clock enable signal provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of time division multiplexing of each ODUk clock enable signal provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the ODUK frame structure provided in an embodiment of the present application;

[0024] Figure 6 A system block diagram of a frame structure generation module provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of generating an ODUK frame structure provided in an embodiment of the present application;

[0026] Figure 8 A system block diagram of a time slot search module provided in an embodiment of the present application;

[0027] Fig. 9 A schematic diagram of a first storage unit provided in an embodiment of the present application;

[0028] Fig.10 A signal diagram of a fifth counter and a sixth counter provided in an embodiment of the present application;

[0029] Fig.11The overhead byte configuration provided in the embodiment of the present application is schematic;

[0030] Fig.12 A signal diagram of a seventh counter and an eighth counter provided in an embodiment of the present application;

[0031] Fig.13 A system block diagram of a signal mapping module provided in an embodiment of the present application;

[0032] Fig.14 A schematic diagram of a valid data area of ​​an OPUk frame provided in an embodiment of the present application;

[0033] Fig.15 A flow chart of a data mapping method for a fine-grained optical transport network based on FPGA provided in an embodiment of the present application;

[0034] Fig.16 A system block diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application will be described in detail below in conjunction with the specific implementation modes shown in the accompanying drawings, but these implementation modes do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in the field based on these implementation modes are included in the protection scope of the present application.

[0036] like Figure 1As shown, a data mapping device for a fine-grained optical transport network based on FPGA is provided in an embodiment of the present application, and the device includes a cache module 11, a clock generation module 12, a frame structure generation module 13, a time slot search module 14 and a signal mapping module 15. The cache module 11 caches fgODUflex data frames of multiple fgODUflex channels. The clock generation module 12 includes at least one clock enable unit 121. For each clock enable unit 121, according to the configured ODUk rate level k, the system clock and the external clock are processed to obtain the ODUk clock enable signal under the system clock, and then the ODUk clock enable signal corresponding to each ODUk channel number under the system clock is obtained, and each ODUk clock enable signal occupies the same data bus in a time division multiplexing form, where k=0, 1, 2, or flex. The frame structure generation module 13 performs the following processing for each clock cycle of the system clock: determining the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle of the system clock, performing byte counting in response to the ODUk clock enable signal, and generating the ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained by performing byte counting based on each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number. The time slot search module 14 performs the following processing for each clock cycle of the system clock: determining the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle of the system clock, determining the fgODUflex channel number corresponding to each fgTS (fine granular time slot) in the ODUk frame structure of the ODUk channel number, and determining the overhead byte corresponding to each fgTSOH (fine granular time slot overhead) in the ODUk frame structure. The signal mapping module 15 reads the corresponding fgODUflex data frame from the cache module 11 for each ODUk channel number according to each fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and maps the corresponding fgODUflex data frame to each fgTS in the ODUk frame structure, and maps the overhead byte to each fgTSOH in the ODUk frame structure, so as to obtain the ODUk data frame of the ODUk channel number. In this embodiment, the ODUk clock enable signal is obtained by processing the system clock and the external clock through the clock enable unit 121. According to the requirements and system settings, multiple clock enable units 121 can be selected, and the ODUk clock enable signal of each ODUk channel is generated based on each clock enable unit 121. It can be understood that the k value in each ODUk clock enable signal can be the same or different, and can be set according to actual requirements. The same clock enable unit 121 can only generate a clock enable signal of one ODUk level rate.Each ODUk clock enable signal occupies the same data bus in a time-division multiplexing form. Based on the data bus, an ODUk frame structure of each ODUk channel number is generated by time-division multiplexing, and the fgODUflex channel number corresponding to each fgTS of OPUk in the ODUk frame structure is determined by time-division multiplexing, and the overhead byte corresponding to each fgTSOH of OPUk is determined, and the fgODUflex data frame of each fgODUflex channel number is mapped to each fgTS of OPUk in the ODUk frame structure, and the overhead byte corresponding to each fgTSOH is mapped to OPUk, so as to obtain ODUk data frames of multiple ODUk channel numbers, and the signal can be mapped to ODUk containers of any multiple channels. The solution is flexible in application and can save FPGA system resources.

[0037] As an optional implementation, Figure 2 As shown, the clock generation module 12 includes an asynchronous FIFO 122 , a first counter 123 and a second counter 124 .

[0038] The asynchronous FIFO122 uses the system clock as the read clock domain of the asynchronous FIFO122 and the external clock as the write clock domain of the asynchronous FIFO122, and outputs the ODU2 clock enable signal under the system clock, wherein the external clock frequency is consistent with the ODU2 rate, and the ODU2 clock enable signal has the first data bit width. The rates of ODU0 / ODU1 / ODU2 / ODUflex are all multiples of 1244160kbit, i.e., ODU1=239 / 238*2*ODU0, ODUflex=N*ODU0, N=3~7, ODU2 =239 / 237*8*ODU0. In this embodiment, the ODU2 rate is used as the write clock domain of the asynchronous FIFO122, i.e., the external clock is 156.832M, which can be generated by a clock chip. Exemplarily, the system clock is 200Mhz. The read clock of the asynchronous FIFO 122 is 200Mhz, and the write clock is 156.832M. When the asynchronous FIFO 122 has data, it outputs a read data and a read enable. The read enable is the ODU2 clock enable signal of the ODU2 at the 200M clock. The ODU2 clock enable signal has a data bit width of 64 bits.

[0039] In each counting cycle of the first counter 123, the ODU2 clock enable signal is counted, and when the count reaches 238, it is cleared, and the first 237 ODU2 clock enable signals are taken as the ODU1 clock enable signal under the system clock, wherein the ODU1 clock enable signal has the second data bit width. Exemplarily, the data bit width of the ODU1 clock enable signal is 16 bits, the ODU1 clock frequency = (239 / 238*2488320) / 16, the ODU2 clock frequency = 239 / 237*9953280) / 64, so ODU1 / ODU2 = ((239 / 238*2488320) / 16) / (239 / 237*9953280) / 64) = 237 / 238, so the ODU2 clock enable signal is counted by the first counter 123 to obtain the ODU1 clock enable signal, when the count reaches 238, the first counter 123 is cleared, and each of the first 237 ODU2 clock enable signals is taken as the ODU1 clock enable signal under the 200M system clock.

[0040] In each counting cycle of the second counter 124, the ODU1 clock enable signal is counted, and when the count reaches 239, it is cleared, and the first 238 ODU1 clock enable signals are taken as the ODU0 clock enable signal under the system clock, wherein the ODU0 clock enable signal has a third data bit width. Exemplarily, the rate of ODU0 is defined in the protocol as half of the rate of OPU1, and the data bit width of the ODU0 clock enable signal is 8 bits, so the clock frequency of OPU1 is the same as the clock frequency of ODU0. The OPU1 rate is 2488320 kbit, so the ratio of the clock frequency of ODU0 to that of ODU1 is 238:239. Therefore, the ODU1 clock enable signal is counted by the second counter 124, and when the count reaches 239, the count is cleared, and each of the first 238 ODU1 clock enable signals is taken as the ODU0 clock enable signal under the system clock 200M. As Figure 3 The schematic diagram of ODU2 / ODU1 / ODU0 clock enable signal is shown in the figure. In the figure, the green signal is the 200M system clock signal, the gray signal is the ODU2 clock 156.832M, the red signal is the ODU2 clock enable signal (64bit data bit width), the yellow signal is the ODU1 clock enable signal (16bit data bit width), and the blue signal is the ODU0 clock enable signal (8bit data bit width).

[0041] As an optional implementation, Figure 2As shown, the clock generation module 12 includes a plurality of clock enable units 121, a clock buffer unit 125 and a clock scheduling unit 126. The selected clock enable unit 121 is determined according to the total bandwidth of the fgODUflex data frame and the sum of the bandwidths of the clock enable units 121. For any selected clock enable unit 121, one of the ODU0 clock enable signal, the ODU1 clock enable signal and the ODU2 clock enable signal is selected as the clock enable signal of the clock enable unit 121 according to the configured ODUk rate level k. The selected clock enable signal is counted under the triggering of the system clock, and the count value is increased by L each time. When the count value is greater than or equal to 16, the ODUk clock enable signal under the system clock is output, and the count value is reduced by 16 to obtain each ODUk clock enable signal under the system clock, wherein L is determined according to the ODUk rate level k and the selected clock enable signal, and the ODUk clock enable signal has a fourth data bit width. The clock buffer unit 125 includes a plurality of buffers 1251, and buffers each ODUk clock enable signal one by one into each buffer 1251, and uses the number of each buffer 1251 as the corresponding ODUk channel number. The clock scheduling unit 126 uses a round-robin scheduling algorithm to take out each ODUk clock enable signal from the clock buffer unit 125, and uses each ODUk clock enable signal to occupy the same data bus in a time division multiplexing form, wherein the ODUk clock enable signal carries the corresponding ODUk channel number.

[0042] In this embodiment, in order to ensure the flexibility of software configuration, each clock enable unit 121 supports the generation of clock enable signals of ODU0 / ODU1 / ODU2 / ODUflex, and one clock enable unit 121 can only generate a clock enable signal of one ODUk rate level, so the required clock enable unit 121 can be selected from multiple clock enable units 121 according to the bandwidth of the data frame to be mapped and the sum of the bandwidths of the clock enable units 121. Exemplarily, the sum of the bandwidths of the multiple clock enable units 121 is 20G, and the minimum particle of the fgODUflex data frame mapped to ODUk is ODU0, so a maximum of 16 clock enable units 121 are supported. If the clock enable unit 121 is configured to output the ODU0 clock enable signal, the clock enable unit 121 occupies 1.25G bandwidth; if the clock enable unit 121 is configured to output the ODU1 clock enable signal, the clock enable unit 121 occupies 2.5G bandwidth; if the clock enable unit 121 is configured to output the ODU2 clock enable signal, the clock enable unit 121 occupies 10G bandwidth; if the clock enable unit 121 is configured to output the ODUflex clock enable signal, the clock enable unit 121 occupies N*1.25G bandwidth. The total bandwidth of the multiple clock enable units 121 to be configured cannot exceed 20G, but each clock enable unit 121 can be configured in any combination. For example, one ODU2 clock generation unit and eight ODU0 clock generation units are selected according to the requirements, and these nine clock generation units are selected from the 16 clock enable units 121 based on actual requirements.

[0043] In this embodiment, each clock enable unit 121 inputs the ODU0 clock enable signal, the ODU1 clock enable signal, and the ODU1 clock enable signal. Since the rate level of the ODUk clock enable signal output by the clock enable unit 121 is different, for example, it can be ODU0 or ODUflex. Based on the relationship between the ODUk rates of different rate levels, one of the three clock enable signals inputted above is selected as the clock enable signal used by the clock enable unit 121. For example, the rate of ODUflex is N times that of ODU0, so the clock generation unit outputting the ODUflex clock enable signal selects the ODU0 clock enable signal. Since the data bit widths of the ODU0 clock enable signal, the ODU1 clock enable signal, and the ODU1 clock enable signal are inconsistent, the output ODUk clock enable signal needs to be converted to the same data bit width through a counter, that is, under the triggering of the system clock, the selected clock enable signal is counted and the count value is increased by L each time. When the count value is greater than or equal to 16, the ODUk clock enable signal under the system clock is output. Exemplarily, the data bit width of the output ODUk clock enable signal is set to 128 bits, the ODU0 clock enable signal is 8 bits, the ODU1 clock enable signal is 16 bits, and the ODU2 clock enable signal is 64 bits. If the clock enable unit 121 selects the ODU0 clock enable signal and outputs a 128-bit ODU0 clock enable signal, L is 1; if the clock enable unit 121 selects the ODU1 clock enable signal and outputs a 128-bit ODU0 clock enable signal, L is 2; if the clock enable unit 121 selects the ODU2 clock enable signal and outputs a 128-bit ODU2 clock enable signal, L is 8; if the clock enable unit 121 selects the ODU0 clock enable signal and outputs a 128-bit ODUflex clock enable signal, L is N, and N is 3 to 7.

[0044] In this embodiment, the ODUk clock enable signals generated by the above-obtained clock enable units 121 are cached, one buffer 1251 caches one ODUk clock enable signal, and the number of each buffer 1251 is defined as the corresponding ODUk channel number. Exemplarily, taking the above embodiment as an example, the total bandwidth of the clock enable unit 121 is 20G, and a maximum of 16 clock enable units 121 are supported, so there can be 16 buffers 1251, and the buffers 1251 can be numbered 0 to 15 in sequence.

[0045] In this embodiment, the clock scheduling unit 126 uses a round-robin scheduling algorithm to take out the corresponding ODUk clock enable signal from each buffer 1251, and the taken out ODUk clock enable signal occupies the same data bus in a time division multiplexing form. The round-robin scheduling algorithm is a commonly used scheduling algorithm. The ODUk clock enable signal of a buffer 1251 is currently read, and the ODUk clock enable signal of another buffer 1251 is read next time, so as to maintain uniform scheduling and reduce clock jitter. Exemplarily, the ODUk clock enable signal read from the 0th buffer 1251 carries an ODUk channel number of 0, and the ODUk clock enable signal read from the 15th buffer 1251 carries an ODUk channel number of 15. The read ODUk clock enable signals occupy the same data bus in the form of time division multiplexing. In the subsequent ODUk frame structure generation, time slot search, and payload and overhead insertion, the ODUk channel number corresponding to each clock cycle of each system clock is processed in a time division multiplexing method based on the data bus, that is, in the current clock cycle of the system clock, the corresponding ODUk channel number is performed with related operations, and the status information after the current operation is cached, so that when the next clock cycle corresponding to the ODUk channel number comes, the subsequent processing is continued based on the cached status information. If the next clock cycle corresponds to another ODUk channel number, the related operations are also performed, and the last cached status information is read out, and the subsequent related operations are continued, so as to realize the time division multiplexing processing of each ODUk channel number on the data bus. Figure 4 FIG. 1 is a schematic diagram of time division multiplexing of various ODUk clock enable signals.

[0046] like Figure 5 The schematic diagram of the ODUK frame structure shown is composed of 4 rows of block structures, each row contains 3824 bytes (i.e., contains 3824 columns), a total of 15296 bytes, the 1st to 16th columns of each row are overhead areas, and the 17th to 3824th columns of each row are the payload area of ​​the optical channel payload unit k (OPUk), wherein the overhead area mainly includes: frame alignment bytes located in the 1st to 6th columns of the 1st row, OTUk overhead bytes located in the 7th to 14th columns of the 1st row, ODUk overhead bytes located in the 1st to 14th bytes of the 2nd to 4th rows, and OPUk overhead bytes located in the 15th to 16th bytes of the 1st to 4th rows. Based on the ODUK frame structure, the counter of the frame structure generation module 13 performs row and column counting to generate the ODUk frame structure of each ODUk channel number.

[0047] As an optional implementation, Figure 6As shown, the frame structure generation module 13 includes a third counter 131 and a fourth counter 132. The third counter 131 and the fourth counter 132 perform column counting and row counting on the ODUk frame structure of each ODUk channel number using a time division multiplexing method to generate a corresponding ODUk frame structure. The time division multiplexing method includes: for each ODUk channel number, the third counter 131 determines the ODUk channel number and the ODUk clock enable signal in the current clock cycle of the system clock, and in response to the ODUk clock enable signal, performs byte counting based on a preset number of unit bytes to obtain a column count value, caches the obtained column count value, and in the next clock cycle corresponding to the ODUk channel number, the third counter 131 accumulates counts on the last cached column count value, and so on, in response to the third counter When the column count value of the third counter 131 reaches the maximum value, the count value of the fourth counter 132 is increased by one to obtain the row count value, the third counter 131 is cleared, and the row count value is cached. The cached row count value is used for the fourth counter 132 to add one to the cached row count value when the third counter 131 reaches the maximum value of the column count next time, and in the next clock cycle corresponding to the ODUk channel number, the third counter 131 starts counting from 0, and so on, until the row count value is 3 and the column count value reaches the maximum value of the column count, the third counter 131 and the fourth counter 132 are reset to generate an ODUk frame structure corresponding to the ODUk channel number, wherein the maximum value of the column count is determined according to the total number of bytes and the number of unit bytes of the ODUk frame structure. For example, the number of unit bytes is set to 16 bytes. From the above ODUk frame structure, it can be seen that each count increases by 16 bytes, the maximum value of the column count is 3824 / 16=239, the row count is counted from 0 to 3, when the column count value is counted from 0 to 238, the row count is counted from 0 to 1, the column count is counted from 0 to 238, the row count is counted from 1 to 2, and so on, to obtain an ODUk frame structure with 4 rows and 239 columns. Figure 7 The schematic diagram of ODUk frame structure generation is shown. It can be seen from the figure that the first clock cycle and the second clock cycle of the system clock correspond to the ODUk clock enable signal of ODUk channel No. 1. The first clock cycle and the second clock cycle perform frame structure counting on ODUk channel No. 1. The third clock cycle of the system clock corresponds to the ODUk clock enable signal of ODUk channel No. 2. The frame structure counting is performed on ODUk channel No. 2. The fourth clock cycle corresponds to the ODUk clock enable signal of ODUk channel No. 1. Therefore, according to the count value cached last time, the frame structure counting continues to be performed on ODUk channel No. 1. And so on, the ODUk frame structure of ODUk channel No. 1 and the ODUk frame structure of ODUk channel No. 2 are generated, thereby realizing the technical solution of time division multiplexing without duplicating the frame structure counting circuit of each channel number, saving the system resources of FPGA.

[0048] In the protocol, OPU0 is divided into 119 10M fine-grained time slots fgTS, OPU1 is divided into 2*119 10M fine-grained time slots fgTS, OPU2 is divided into 8*119 10M fine-grained time slots fgTS, and OPUflex is divided into N*119 10M fine-grained time slots fgTS, where n is 3~7. The 10M fine-grained time slot fgTS uses a 16-byte time slot interleaving granularity in the OPU payload area. A 10M fine-grained time slot fgTS includes a part of the OPU overhead area and a part of the payload area. For example, the fgTSOH multiframe of OPU0 consists of 32 OPU0 frames, which are divided into 119 10M fine-grained time slots numbered from 1 to 119. The 119 10M fine-grained time slots fgTS are arranged in 16-byte interleaving in the payload area of ​​OPU0. Each 10M fine-grained time slot in OPU0 consists of 256 16-byte blocks and a 12-bit time slot overhead (fgTSOH). In the 1st to 29th OPU0 frames, each OPU0 frame overhead area carries 4 fgTSOH overheads, a total of fgTSOH #1, fgTSOH #2, fgTSOH #3, ..., fgTSOH #116, corresponding to fgTS #1, fgTS #2, fgTS #3, ..., fgTS #116, respectively. The 30th OPU0 frame overhead area carries the remaining 3 fgTSOH overheads, namely fgTSOH #117, fgTSOH #118, fgTSOH #119, corresponding to fgTS #117, fgTS #118, fgTS #119, respectively. The fgTSOH of each 10M fine-grained time slot is available once in each fgTSOH multiframe (32 OPU0 frames). For other OPUk frame structures, OPU2 is divided into 119*8 fgTS, OPU1 is divided into 119*2 fgTS, and OPUflex is divided into 119*N fgTS, where N=3~7. For the specific frame structure description, please refer to the protocol and will not be repeated here.

[0049] Based on the fine-grained time slot fgTS distribution of OPUk, the fgODUflex channel number corresponding to each fgTS is determined to map the corresponding fgODUflex data frame to the corresponding fgTS. Figure 8 As shown, the time slot search module 14 includes a fifth counter 141 , a sixth counter 142 , a first storage unit 143 , a second storage unit 144 and a payload time slot search unit 145 .

[0050] In this embodiment, 119 fgTS are grouped as one fgTS search page. OPU2 has 119*8 fgTS, so there are 8 fgTS search pages in total. OPU1 has 119*2 fgTS, so there are 2 fgTS search pages in total. OPU0 has 119*1 fgTS, so there are 1 fgTS search page in total. OPUflex has 119*N fgTS, so there are N fgTS search pages in total, where N is 3 to 7. The fifth counter 141 and the sixth counter 142 use a time division multiplexing method to count the fgTS in the OPUk frame of each ODUk channel number, and count the fgTS search page. The time division multiplexing method includes: for each ODUk channel number, the fifth counter 141 determines the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle of the system clock, and determines the corresponding OPUk payload enable signal based on the byte position of OPUk in the ODUk frame structure. In response to the OPUk payload enable signal, the fifth counter 141 performs counting, caches the obtained fgTS count value, and in the next clock cycle corresponding to the ODUk channel number, the fifth counter 141 accumulates the count on the fgTS count value cached last time, and so on, in response to the count value of the fifth counter 141 reaching 1 At 18:00, the counting of 119 fgTSs is completed, triggering the sixth counter 142 to count plus one, indicating that an fgTS search page is obtained, and the obtained fgTS search page count value is cached, and the fifth counter 141 is cleared. The cached fgTS search page count value is used for the fifth counter 141 to add one to the cached fgTS search page count value when the next fgTS count value reaches 118. In the next clock cycle corresponding to the ODUk channel number, the fifth counter 141 starts counting from 0, and so on, until the count value of the sixth counter 142 reaches P, the fifth counter 141 and the sixth counter 142 are cleared, wherein P indicates that there are P*119 fgTSs in OPUk, the fgTS count value is used to indicate the number of fgTSs among the 119 fgTSs, and the fgTS search page count value is used to indicate the number of fgTS search pages. In the embodiment of the present application, the fgTS counting and fgTS search page counting operations are performed on the ODUk channel number corresponding to the current clock cycle, and the counting result is cached. If the next clock cycle corresponds to another ODUK channel number, the fgTS counting and fgTS search page counting operations of the ODUk channel number are performed, and the counting result is also cached, so that the processing operation of each ODUk channel number of a data line can be implemented based on the time division multiplexing method.

[0051] In this embodiment, the first storage unit 143 uses the ODUk channel number and the fgTS search page count value as the storage address, and stores the preset fgTS time slot page configuration value into the storage space corresponding to each storage address, wherein the fgTS search page count value is each count value generated by the sixth counter 142 in any counting cycle. The fgTS time slot page configuration value is configured in advance according to actual needs. The count value of the sixth counter 142 is used to indicate the number of the fgTS search page. For example, as can be seen from the above, OPU2 has a total of 8 fgTS search pages, and the count value of the sixth counter 142 corresponds to 0-7, OPU1 has a total of 2 fgTS search pages, and the count value of the sixth counter 142 corresponds to 0-2, OPU0 has a total of 1 fgTS search page, and the count value of the sixth counter 142 is 0-1, OPUflexn has a total of N fgTS time slot pages, and the count value of the sixth counter 142 corresponds to 0~N-1, and N is 3~7. For example, Fig. 9 Schematic diagram of the first storage unit 143 shown in the figure, the low bit addr[2:0] of the storage address is the count value of the sixth counter 142, the high bit addr[6:3] of the storage address is the ODUk channel number, and each storage address stores a pre-configured fgTS time slot page configuration value. For example, the address corresponding to the ODUk channel number 0 and the count value 0 of the sixth counter 142 is 0000000, which stores the fgTS time slot page configuration value corresponding to the 0th fgTS search page in the ODUk frame of the ODUk channel No. 0, and the address corresponding to the ODUk channel number 0 and the count value 1 of the sixth counter 142 is 0000001, which stores the fgTS time slot page configuration value corresponding to the 1st fgTS search page in the ODUk frame of the ODUk channel No. 0.

[0052] The second storage unit 144 is divided into a plurality of storage areas, each storage area includes 119 storage spaces, and the fgTS time slot page configuration value and the fgTS count value are used as the storage address of each storage space, and the preset fgODUflex channel number and the indication of whether the fgTS corresponding to the fgODUflex channel number is the first time slot and the indication of whether it is the last time slot are stored in each storage space, wherein one storage area corresponds to one fgTS time slot page configuration value, and the fgTS count value is each count value generated by the fifth counter 141 in any counting cycle. Exemplarily, it can be seen from the above that when the total bandwidth is 20G, a maximum of 16 fgTS search pages of 119fgTS are supported. The second storage unit is divided into 144 sixteen storage areas 0~15. For storage area 0, the corresponding fgTS time slot page configuration value is 0, and for storage area 3, the corresponding fgTS time slot page configuration value is 3. Each storage area corresponds to storage space 0-118, 0~118 corresponds to fgTS 0~118, and each storage space stores the fgODUflex channel number, that is, the fgODUflex channel number corresponding to fgTS 0~118 can be obtained. 1 ODU2 can be divided into 8 fgTS search pages, 1 ODU0 can be divided into 1 fgTS search page, 1 ODU1 can be divided into 2 fgTS search pages, and 1 ODUflex can be divided into N fgTS search pages. In principle, the total number of enabled fgTS search pages cannot exceed 20. Through the mapping relationship between fgTS and fgTS search pages in the first storage unit 143 and the second storage unit 144, the fgTS of ODUk can be configured more flexibly. For example, the 8 fgTS search pages of ODU2 can select any 8 of the above-mentioned 16 fgTS search pages, which can be achieved by setting the fgTS search page configuration value.

[0053] The payload timeslot search unit 145 uses the ODUk channel number and the current fgTS search page count value of the sixth counter 142 as the read address of the first storage unit 143 in the current clock cycle, reads the corresponding fgTS timeslot page configuration value, and uses the read fgTS timeslot page configuration value and the current fgTS count value of the fifth counter 141 as the read address of the second storage unit 144 to read the fgODUflex channel number corresponding to the current fgTS count value, that is, obtains the fgODUflex channel number corresponding to the current fgTS, and so on, based on each clock cycle corresponding to the ODUk channel number, obtains the fgODUflex channel number corresponding to each fgTS of OPUk in the ODUk frame structure of the ODUk channel number. Similarly, the payload time slot search unit 145 is also based on the time division multiplexing mode during processing, that is, the above operation is performed for the ODUk channel number corresponding to the current clock cycle, and the execution result is cached. If the next clock cycle corresponds to another ODUk channel number, the above operation is performed and the corresponding execution result is cached, so as to realize the operation processing of each ODUk channel number on a data bus, such as Fig.10 Schematic diagram of the fifth counter 141 and the sixth counter 142. Exemplarily, if the current fgTS search page count value of the sixth counter 142 is 0, if the current fgTS count value of the fifth counter 141 is 112, the corresponding fgTS time slot page configuration value is 3 in the first storage unit 143, the corresponding storage area in the second storage unit 144 is 3, and the corresponding fgODUflex channel number is read in the 112th address space in the storage area 3.

[0054] As an optional implementation, Figure 8 As shown, the time slot search module 14 further includes a seventh counter 146, an eighth counter 147, a third storage unit 148, a fourth storage unit 149 and an overhead time slot search unit 14A.

[0055] It can be seen from the OPU0 frame structure that the fgTSOH multiframe of OPU0 is composed of 32 OPU0 frames, and each OPU0 frame overhead area carries 4 fgTSOH overheads. For OPU1, every 2*32 OPU1 frames constitute a fgTSOH multiframe. For OPU2, every 8*32 OPU2 frames constitute a fgTSOH multiframe. For OPUflex, every N*32 OPUflex frames constitute a fgTSOH multiframe. In the embodiment of the present application, 119 fgTSOH overhead time slots are used as an fgTSOH search page, so OPU2 has a total of 8 fgTSOH search pages, OPU1 has a total of 2 fgTSOH search pages, OPU0 has a total of 1 fgTSOH search page, and OPUflex has a total of N fgTSOH search pages, where N is 3~7.

[0056] In this embodiment, the seventh counter 146 and the eighth counter 147 use a time division multiplexing method to count the number of OPUk frames and the fgTSOH search page of each ODUk channel number. The time division multiplexing method includes: for each ODUk channel number, the seventh counter 146 determines the OPUk overhead enable signal based on the ODUk channel number and the ODU clock enable signal in the current clock cycle of the system clock, and in response to the OPUk overhead enable signal, the seventh counter 146 performs counting, caches the obtained OPUk frame count value, and in the next clock cycle corresponding to the ODUk channel number, the seventh counter 146 accumulates the count value of the last cached OPUk frame number, and so on. In response to the count value of the seventh counter 146 reaching 31, the count value of the eighth counter 147 is triggered to increase. First, the obtained fgTSOH search page count value is cached, and the seventh counter 146 is cleared. The cached fgTSOH search page count value is used when the seventh counter 146 reaches 31 in the next OPUk frame count value. The eighth counter 147 adds one to the cached fgTSOH search page count value. In the next clock cycle corresponding to the ODUk channel number, the seventh counter 146 starts counting from 0, and so on. When the count value of the eighth counter 147 reaches Q, the seventh counter 146 and the eighth counter 147 are cleared, where Q indicates that there are Q*119 fgTSOH overhead time slots in OPUk, the count value of the number of OPUk frames is used to indicate the number of 32 OPUk frames, and the fgTSOH search page count value is used to indicate the number of fgTSOH search pages. Exemplarily, it can be seen from the above OPU1 frame structure that the fgTSOH multiframe of OPU1 consists of 2*32 OPU1 frames. Therefore, the seventh counter 146 is used for counting. When the column value of the third counter 131 is 0 and the row count value of the fourth counter 132 is 0, the OPUk overhead enable signal is obtained, indicating the first OPU1 frame. When the column value and row count value are 0 next time, it indicates the second OPU1 frame. By analogy, when the count reaches 31, it indicates the 32nd OPU1 frame. The eighth counter 147 counts from 0 to 1, indicating the first 32 OPU1 frames. The seventh counter 146 counts according to the above method. When the count reaches 31, the eighth counter 147 counts from 1 to 2, indicating the second 32 OPU1 frames. In the embodiment of the present application, the counting operation of the ODUk channel number OPUk frame number and the overhead time slot page corresponding to the current clock cycle is also processed in a time division multiplexing manner. The processing scheme is similar to the above method and will not be repeated here.

[0057] In this embodiment, the third storage unit 148 uses the ODUk channel number and the fgTSOH search page count value as the storage address, and stores the preset fgTSOH time slot page configuration value to the storage space corresponding to each storage address, wherein the fgTSOH search page count value is each count value generated by the eighth counter 147 in any counting cycle. The fgTSOH time slot page configuration value is configured in advance according to actual needs. The count value of the eighth counter 147 is used to indicate the number of fgTSOH search pages. For example, it can be seen from the above that OPU2 has a total of 8 fgTSOH search pages, and the count value of the eighth counter 147 corresponds to 0-7. Similarly, OPU1 has a total of 2 fgTSOH search pages, and the count value of the eighth counter 147 corresponds to 0-1. OPU0 has a total of 1 fgTSOH search page, and the maximum count value of the eighth counter 147 is 1. OPUflex has a total of N fgTSOH search pages, and the count value of the eighth counter 147 corresponds to 0~N-1, where N is 3~7. Exemplarily, the low bits addr[2:0] of the storage address of the third storage unit 148 are the count value of the eighth counter 147, and the high bits addr[6:3] of the storage address are the ODUk channel number. Each storage address stores a pre-configured fgTSOH time slot page configuration value. For example, the address corresponding to the ODUk channel number 0 and the count value 0 of the eighth counter 147 is 0000000, which stores the fgTSOH time slot page configuration value corresponding to the 0th fgTSOH search page in the OPUk frame of the ODUk channel No. 0. The address corresponding to the ODUk channel number 0 and the count value 1 of the eighth counter 147 is 0000001, which stores the fgTSOH time slot page configuration value corresponding to the 1st fgTSOH search page in the OPUk frame of the ODUk channel No. 0.

[0058] In this embodiment, the fourth storage unit 149 stores a plurality of overhead byte configuration tables, each of which includes three rows of table entries, wherein the fgTSOH time slot page configuration value is used as the index number of the overhead byte configuration table, the OPUk frame count value is used as the index number of each row of table entries, a group of fgTSOH is obtained by sequentially dividing four fgTSOHs into a group according to 0-118 fgTSOH, the OPUk frame count value is each count value generated by the seventh counter 146 in any counting cycle, and the overhead byte includes the second parameter C of the previous multiframe cycle m T and overhead byte check code. For example, Fig.11The overhead byte configuration shown is schematic. From the above, it can be seen that when the total bandwidth is 20G, a maximum of 16 fgTSOH search pages are supported, so the overhead byte configuration table is set to 16, and its index number is set to 0~15 accordingly, and the fgTSOH time slot page configuration value is also set to 0~15. It can be seen from the figure that in each overhead byte configuration table, fgTSOH0~fgTSOH1 corresponds to table item 0, and the corresponding OPUk frame count value is 0, that is, it corresponds to fgTSOH0-fgTSOH3 of the 0th OPUk frame, and the corresponding overhead bytes of fgTSOH0~fgTSOH1 are configured in the table item; fgTSOH4~fgTSOH7 corresponds to a table item 1, and the corresponding OPUk frame count value is 1, that is, it corresponds to fgTSOH4~fgTSOH7 of the 1st OPUk frame, and the corresponding overhead bytes of fgTSOH4~fgTSOH7 are configured in the table item. By analogy, the overhead bytes of fgTSOH0~fgTSOH118 are configured in the overhead byte configuration table.

[0059] In this embodiment, the overhead time slot search unit 14A uses the ODUk channel number and the current fgTSOH search page count value of the eighth counter 147 as the read address of the third storage unit 148 in the current clock cycle, reads the corresponding fgTSOH time slot page configuration value, and uses the read fgTSOH time slot page configuration value as the index number to find the corresponding overhead byte configuration table in the fourth storage unit 149, uses the current OPUk frame count value of the seventh counter 146 as the index number to find the corresponding table entry in the overhead byte configuration table, and obtains the four fgTSOH overhead bytes in the table entry. Similarly, based on each clock cycle corresponding to the ODUk channel number, each fgTSOH overhead byte of OPUk in the ODUk frame structure of the ODUk channel number is obtained. Similarly, the overhead time slot search unit 14A is also based on time division multiplexing when processing. Fig.12 Schematic diagram of the seventh counter 146 and the eighth counter 147. Exemplarily, if the current fgTSOH lookup page count value of the eighth counter 147 is 1, if the current OPUk frame count value of the seventh counter 146 is 1, the corresponding fgTSOH time slot page configuration value is 0, and the corresponding 0th overhead byte configuration table in the fourth storage unit 149 is obtained, and the overhead bytes of fgTSOH4~fgTSOH7 are obtained in the first table entry of the 0th overhead byte configuration table.

[0060] The fgODUflex frame is mapped to the fgODTU.M payload area in units of 16-byte blocks. The fgODTU.M consists of the fgODTU.M payload area and the fgODTU.M overhead area. The fgODTU.M payload area is a 128-row 2*M 16-byte column structure, including 256*M 16-byte payload blocks. The 256×M 16-byte payload blocks in the fgODTU.M payload area are numbered from 1 to 256M. The fgODTU.M overhead area includes 12 bits for carrying the fgGMP mapping overhead. The fgODTU.M is carried in the M 10M fine-grained time slots of OPUk. When the fgODTU.M is multiplexed into the M 10M time slots of the OPU, the 256*M 16-byte blocks in the fgODTU.M payload area are mapped one by one to the 256*M 16-byte blocks in the M 10M fine-grained time slots of the n*32-frame OPU multiframe. The fgODTU.M overhead is mapped into the OPU fgTSOH corresponding to the last timeslot allocated to the fgODTU.M.

[0061] As an optional implementation, Fig.13 As shown, the signal mapping module 15 includes a fifth storage unit 151 and an overhead updating unit 152 .

[0062] In this embodiment, the fifth storage unit 151 stores a fgGMP mapping configuration table, in which a corresponding relationship between the fgODUflex channel number and the preset fgGMP mapping parameters is established. The fgGMP mapping parameters include parameters C 128 B. Parameter C 128,nor Parameter C 128 T, min Parameter C 128 T, max and parameter Pserver. These parameters are configured according to actual needs. According to the protocol, C 128 B indicates that different rates of fgODUflex correspond to different C 128 B value. C 128,min Indicates that when fgODUflex is mapped to fgODTU.M, C 128 Minimum value of T. C 128,max Indicates that when fgODUflex is mapped to fgODTU.M, C 128 The maximum value of T. Pserver indicates the size of the fgODTU.M payload, in units of 16-byte blocks. For example, if the fgODTU.M payload area is a 128-row, 2M 16-byte column structure, including 256M 16-byte blocks, then Pserver = 256M.

[0063] The overhead updating unit 152 updates the parameter C corresponding to the fgODUflex channel number for each fgODUflex channel number according to the rate at which the fgODUflex data frame corresponding to the fgODUflex channel number is written into the cache module 11 and the rate at which the fgODUflex data frame is read from the cache module 11. 128,min and parameter C 128,max Choose one of the two as the first parameter C ur C m , and the second parameter C of the current multiframe period m T is updated to the corresponding fgTSOH in the fourth storage unit 149, where the parameter C 128,min is parameter C 128 T, min and parameter C 128 The sum of B, parameter C 128,max is parameter C 128 T, min and parameter C 128 B and the second parameter C m T is the first parameter C ur C m With C 128 It can be understood that, from the above, each fgTS in OPUk corresponding to each fgODUflex channel number can be used to obtain the corresponding fgTSOH based on each fgTS, and then the second parameter C of the current multiframe period can be obtained. m T is updated to the corresponding fgTSOH. The fgODTU.M payload area is a 128-row 2*M 16-byte column structure. Each time a fgODTU.M payload area is sent, the fgGMP algorithm can map C 128,min ~C 128,max bytes. If the C 128,min , the fgODUflex rate is greater than the fgGMP filling data rate, and it is too late to send; if it continues to fill C 128,max , it is sent too fast, which will cause fgODUflex frame loss. Therefore, it is necessary to dynamically determine the C filled in each fgODTU.M sending cycle. 128 Therefore, an upper waterline and a lower waterline are set at the cache FIFO of each fgODUflex signal channel. When the upper waterline is reached, it indicates that the rate at which fgODUflex data is written into the cache module 11 is greater than the rate at which fgODUflex data is read from the cache module 11. C 128,max The fgGMP mapping algorithm is performed to gradually reduce the amount of temporary data in the cache module 11 to the waterline. At this time, the fgODUflex reading rate is less than the fgODTU.M frame sending rate. 128,minThe fgGMP mapping algorithm is performed to slowly increase the amount of temporary data in the cache module 11 to the upper waterline. In such a dynamic alternation process, the overall fgODUflex reading rate is equal to the gODTU.M frame sending rate, thereby completing the rate adaptation. For example, the rate of an fgODflex channel is 10.409203Mbps, and the rate of an allocated fgODTU.M is 10.411380Mbps. 128,nor =10.409203 / 10.411380 * 256 = 255.947, but the C128 used in each sending cycle is an integer, so it can only be 255 or 256, so C is used in 947 cycles in 1000 cycles. 128 =256,53 cycles to send C 128 =255, thus achieving rate adaptation.

[0064] like Fig.13 As shown, the signal mapping module 15 includes an overhead inserting unit 153 and a payload mapping unit 154 .

[0065] The overhead insertion unit 153 writes the overhead bytes of each fgTSOH of OPUk in the ODUk frame structure of the ODUk channel number into each fgTSOH of the corresponding OPUk for each ODUk channel number, and the overhead bytes include the second parameter C of the current multiframe period. m T and the overhead byte check code are used to implement the insertion of the overhead bytes in the frame signal mapping. Exemplarily, the overhead byte configuration table corresponding to the ODUk channel number in the fourth storage unit 149 is determined, and the corresponding overhead bytes are read from each table item of the overhead byte configuration table in sequence, and four fgTSOH overhead bytes are read each time, and the four fgTSOH overhead bytes are written into the fgTSOH corresponding to OPUk in sequence to complete the overhead byte insertion function. The overhead bytes include the second parameter C of the current multiframe period m T and overhead byte check code. The OPUk frame structure also includes an OPUk multi-frame indicator (OMFI) of 4 bits, located at bits 5-8 of the 4th row and 16th column of the OPU frame. The multi-frame increments every 256 frames. Different OPUs have different OMFI value ranges. For OPU0, the OMFI value range is 0, for OPU1, the OMFI value range is [0,1], for OPU2, the OMFI value range is [0,7], and for OPUflexn, the OMFI value range is [0,n-1]. When the overhead byte is inserted, the OPUk multi-frame indicator is also inserted to the corresponding position.

[0066] The payload mapping unit 154 performs payload signal mapping processing on each fgTS in the OPUk for each ODUk channel number. The payload signal mapping processing includes: obtaining a first parameter C of the fgTSOH corresponding to the fgTS ur C m , based on the first parameter C ur C m The fgGMP mapping is performed on the fgTS and the fgGMP mapping parameters to obtain each valid data area in the fgODTU.M frame structure, and the data area enable signal of each valid data area is determined. Based on each data area enable signal, the fgODUflex data frame corresponding to the fgTS and the fgODUflex channel number is read from the cache module 11, and mapped to each valid data area in the fgODTU.M frame structure to obtain the fgODTU.M frame corresponding to the fgTS, and then obtain the fgODTU.M frames corresponding to each fgTS, multiplex the fgODTU.M frame signal into the M fgTS of OPUk, and based on the OPUk with the overhead bytes inserted, obtain the ODUk data frame corresponding to the ODUk channel number.

[0067] For example, fgGMP mapping is used to map fgODUflex to fgODTU.M, where M is the number of fine-grained time slots allocated to fgODUflex. fgGMP mapping is a general mapping algorithm that uses the Sigma-Delta algorithm for filling, with a granularity of 16 bytes per block, to uniformly increase the fgODUflex signal rate to match the fgODTU.M rate in ODUk. fgGMP mapping is a simplified mapping processing method of GMP, which only transmits C m T, no need to transmit CnD information, where CmB+CmT is the Cm value, CmB is the agreed fixed value, and different rates of fgODUflex correspond to different CmB values. Each fgODTU.M multiframe generates a CmT. Fig.14The schematic diagram of the valid data area of ​​the OPUk frame shown in the figure, the 17th to 3824th bytes in the ODUk frame are the OPUk payload area. As shown in the figure, each blue data area is allocated to the first fgODTU.M, each orange data area is allocated to the second fgODTU.M, and each green data area is allocated to the third fgODTU.M. The first fgODUflex signal is mapped to each blue data area through fgGMP. Through the mapping algorithm, the first blue data area is a valid data area, which can be filled with 16 bytes of fgODUflex data, the second blue data area is filled, which can be filled with 0, the third blue data area is a valid data area, which can be filled with 16 bytes of fgODUflex data, and the fourth blue block is filled, thereby realizing the ODUk data frame mapped with multiple fgODUflex signals. Based on the byte position of each valid data area in the frame structure, the data area enable signal of each valid data area can be determined, and based on the data area enable signal, the fgODUflex data is read from the cache module 11.

[0068] Exemplarily, the cache module 11 stores the received fgODUflex data based on the fgODUflex channel number. Based on the cache space corresponding to each fgODUflex channel number, the corresponding fgODUflex data is cached. Exemplarily, the cache module 11 may be a RAM.

[0069] Based on the same inventive concept, an embodiment of the present application also provides a data mapping method for a fine-grained optical transport network based on FPGA. The implementation solution for solving the problem provided by the method is similar to the implementation solution recorded in the above-mentioned device. Therefore, the specific limitations in one or more embodiments of the data mapping method for a fine-grained optical transport network based on FPGA provided below can be found in the above limitations on the data mapping device for a fine-grained optical transport network based on FPGA, and will not be repeated here.

[0070] Please refer to Fig.15 The present application provides a data mapping method for a fine-grained optical transport network based on FPGA, the method comprising the steps of:

[0071] S1501, buffering fgODUflex data frames of multiple fgODUflex channels;

[0072] S1502: According to the configured ODUk rate level, the system clock and the external clock are processed to obtain an ODUk clock enable signal under the system clock, and then the ODUk clock enable signal corresponding to each ODUk channel number under the system clock is obtained, and each ODUk clock enable signal occupies the same data bus in a time division multiplexing form, where k=0, 1, 2, or flex;

[0073] S1503, for each clock cycle of the system clock, perform the following processing: determine the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, perform byte counting in response to the ODUk clock enable signal, and then generate an ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained based on the byte counting of each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number;

[0074] S1504, for each clock cycle of the system clock, perform the following processing: based on the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, determine the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and determine the overhead byte corresponding to each fgTSOH in the ODUk frame structure;

[0075] S1505: For each ODUk channel number, according to the fgODUflex channel numbers corresponding to the fgTS in the ODUk frame structure of the ODUk channel number, the corresponding fgODUflex data frame is read from the cache module 11, and mapped to the corresponding fgTS in the ODUk frame structure, and the overhead byte is mapped to the corresponding fgTSOH in the ODUk frame structure to obtain the ODUk data frame of the ODUk channel number.

[0076] In this embodiment, each ODUk clock enable signal occupies the same data bus in a time division multiplexing form, and an ODUk frame structure of each ODUk channel number is generated by time division multiplexing. The fgODUflex channel number corresponding to each fgTS of OPUk in the ODUk frame structure is determined by time division multiplexing, and the overhead byte corresponding to each fgTSOH of OPUk is determined. The fgODUflex data frame of each fgODUflex channel number is mapped to each fgTS of OPUk in the ODUk frame structure, and the overhead byte corresponding to each fgTSOH is mapped to OPUk, thereby obtaining ODUk data frames of multiple ODUk channel numbers, and the signal can be mapped to ODUk containers of any multiple channels. This solution is flexible in application and can save FPGA system resources.

[0077] As an example, see Fig.16, which shows a schematic diagram of the structure of a communication device provided by an embodiment of the present application. The network device includes a fine-grained flexible optical data unit generating device 1601 based on FPGA, a communication interface 1602, a processor 1603, a memory 1604 and a bus 1605. The processor 1603, the memory 1604, the communication interface 1602 and the data mapping device 1601 of the fine-grained optical transport network based on FPGA are connected to each other through a bus 1805. The memory 1604 can be used to store computer programs, and the computer programs may include instructions and data. In an embodiment of the present application, the memory 1604 may be various types of storage media, such as random access memory, static random access memory, non-volatile RAM, DDR, etc. The memory 1604 may include a hard disk and / or a memory. The processor 1603 may be a general-purpose processor, which may be a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (such as memory 1604), and the general-purpose processor is used to process the data output by the data mapping device 1601 of the fine-grained optical transport network based on FPGA. A general-purpose processor may be, for example, but not limited to, a central processing unit. In addition, the processor 1603 may also be a special-purpose processor, which may be a processor specially designed to perform specific steps and / or operations, and may be, for example, but not limited to, an ASIC and an FPGA. In addition, the processor 1603 may also be a combination of multiple processors, such as a multi-core processor. The communication interface 1602 may include an input / output interface, a physical interface, a logical interface, and other interfaces for interconnecting devices within a network device, as well as an interface for interconnecting a network device with other devices (such as a network device). The physical interface may be a Gigabit Ethernet interface, which may be used to interconnect a network device with other devices, and the logical interface is an interface within a network device, which may be used to interconnect devices within a network device. The bus 1605 may be any type of communication bus, such as a system bus, for interconnecting the processor 1603, the memory 1604, the communication interface 1602, and the data mapping device 1601 of a fine-grained optical transport network based on an FPGA. The structure of the data mapping device 1601 of a fine-grained optical transport network based on an FPGA may refer to Figure 1 The interconnection between any one of the processor 1603, the memory 1604 and the communication interface 1602 and the data mapping device 1601 of the fine-grained optical transport network based on FPGA may specifically refer to the interconnection between any one of the devices and the device in the data mapping device 1601 of the fine-grained optical transport network based on FPGA.

[0078] The embodiments disclosed in the present application also provide a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is executed on a computer, the computer executes the data mapping method for a fine-grained optical transport network based on FPGA as described in any of the above embodiments.

[0079] Although the preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application as disclosed in the accompanying claims.

Claims

1. A data mapping device for a fine-grained optical transport network based on FPGA, characterized in that: The device comprises: A cache module, used for caching fgODUflex data frames of multiple fgODUflex channels; The clock generation module includes at least one clock enable unit, which is used to process the system clock and the external clock according to the configured ODUk rate level k for each clock enable unit to obtain the ODUk clock enable signal under the system clock, and then obtain the ODUk clock enable signal corresponding to each ODUk channel number under the system clock, and use each ODUk clock enable signal to occupy the same data bus in a time division multiplexing form, where k=0, 1, 2, or flex; a frame structure generating module, configured to perform the following processing for each clock cycle of the system clock: determining an ODUk channel number and an ODUk clock enable signal corresponding to a current clock cycle, performing byte counting in response to the ODUk clock enable signal, and then generating an ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained by performing byte counting on each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number; The time slot search module is used to perform the following processing for each clock cycle of the system clock: based on the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, determine the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and determine the overhead byte corresponding to each fgTSOH in the ODUk frame structure; The signal mapping module is used to read the corresponding fgODUflex data frame from the cache module according to each fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number for each ODUk channel number, and map it to each fgTS in the ODUk frame structure, and map the overhead byte to each fgTSOH in the ODUk frame structure to obtain the ODUk data frame of the ODUk channel number.

2. The device according to claim 1, characterized in that The clock generation module comprises: an asynchronous FIFO, configured to use the system clock as a read clock domain of the asynchronous FIFO, use the external clock as a write clock domain of the asynchronous FIFO, and output an ODU2 clock enable signal under the system clock, wherein the external clock frequency is consistent with the ODU2 rate, and the ODU2 clock enable signal has a first data bit width; a first counter, configured to count the ODU2 clock enable signal in each counting cycle of the first counter, and to clear the counted ODU2 clock enable signal when the count reaches 238, and to take each of the first 237 ODU2 clock enable signals as the ODU1 clock enable signal under the system clock, wherein the ODU1 clock enable signal has a second data bit width; The second counter is used to count the ODU1 clock enable signal in each counting cycle of the second counter, and clear it when the count reaches 239, and take each of the first 238 ODU1 clock enable signals as the ODU0 clock enable signal under the system clock, wherein the ODU0 clock enable signal has a third data bit width.

3. The device according to claim 2, characterized in that The clock generation module comprises: a plurality of clock enable units, configured to determine a selected clock enable unit according to a total bandwidth of the fgODUflex data frame and a sum of bandwidths of the plurality of clock enable units, and for any selected clock enable unit, select one of the ODU0 clock enable signal, the ODU1 clock enable signal, and the ODU2 clock enable signal as a clock enable signal of the clock enable unit according to the rate level k of the ODUk, count the selected clock enable signal under the triggering of the system clock, add L to the count value each time, and when the count value is greater than or equal to 16, subtract 16 from the count value, and output the ODUk clock enable signal under the system clock, so as to obtain each ODUk clock enable signal under the system clock, wherein the L is determined according to the rate level k of the ODUk and the selected clock enable signal, and the ODUk clock enable signal has a fourth data bit width; A clock buffer unit, comprising a plurality of buffers, for buffering each of the ODUk clock enable signals into each buffer one by one, and taking the number of each buffer as the corresponding ODUk channel number; The clock scheduling unit is used to take out each ODUk clock enable signal from the clock buffer unit by using a round-robin scheduling algorithm, and use each ODUk clock enable signal to occupy the same data bus in a time division multiplexing form, wherein the ODUk clock enable signal carries a corresponding ODUk channel number.

4. The device according to claim 1, characterized in that The frame structure generation module includes a third counter and a fourth counter: For each ODUk channel number, the third counter and the fourth counter generate a corresponding ODUk frame structure using a time division multiplexing method, and the time division multiplexing method includes: The third counter determines the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle of the system clock, and in response to the ODUk clock enable signal, counts based on a preset number of unit bytes to obtain a column count value, caches the column count value, and in the next clock cycle corresponding to the ODUk channel number, the third counter accumulates the count on the last cached column count value, and so on, in response to the third counter reaching the maximum column count value, the count value of the fourth counter is increased by one to obtain a row count value, the third counter is cleared, and the row count value is cached, and the cached row count value is used for the fourth counter to add one to the cached row count value when the third counter reaches the maximum column count value next time, and so on, until the row count value is 3 and the column count value reaches the maximum row count value, the third counter and the fourth counter are reset to generate the ODUk frame structure corresponding to the ODUk channel number, wherein the maximum column count value is determined according to the total number of bytes and the number of unit bytes of the ODUk frame structure.

5. The device according to claim 1, characterized in that The time slot search module includes a fifth counter, a sixth counter, a first storage unit, a second storage unit and a payload time slot search unit: For each ODUk channel number, based on the ODUk channel number corresponding to the current clock cycle of the system clock and the ODUk clock enable signal, an OPUk payload enable signal is determined, and in response to the OPUk payload enable signal, the fifth counter performs counting, caches the obtained fgTS count value, and in the next clock cycle corresponding to the ODUk channel number, the fifth counter accumulates the count on the fgTS count value cached last time, and so on, in response to the count value of the fifth counter reaching 118, the count value of the sixth counter is increased by one, and the obtained fgTS search page count value is cache, the fifth counter is cleared, the fgTS search page count value of the cache is used to add one to the fgTS search page count value of the cache when the fgTS count value of the fifth counter reaches 118 next time, and so on, until the fgTS search page count value reaches P, the fifth counter and the sixth counter are cleared, wherein P indicates that there are P*119 fgTSs in OPUk, the fgTS count value is used to indicate the number of fgTSs among 119 fgTSs, and the fgTS search page count value is used to indicate the number of fgTS search pages; The first storage unit is used to store the preset fgTS time slot page configuration value into the storage space corresponding to each storage address by using the ODUk channel number and the fgTS search page count value as the storage address, wherein the fgTS search page count value is each count value generated by the sixth counter in any counting cycle, and the value range of the fgTS time slot page configuration value is 0 to the maximum value of the ODUk channel number - 1; The second storage unit is used to divide the second storage unit into a plurality of storage areas, each storage area includes 119 storage spaces, and the fgTS time slot page configuration value and the fgTS count value are used as the storage address of each storage space, and the preset fgODUflex channel number and the indication of whether the fgTS corresponding to the fgODUflex channel number is the first time slot and the indication of whether it is the last time slot are stored in each storage space, wherein one storage area corresponds to one fgTS time slot page configuration value, and the fgTS count value is each count value generated by the fifth counter in any counting cycle; The payload timeslot search unit is configured to use the ODUk channel number and the current fgTS search page count value of the sixth counter as the read address of the first storage unit in the current clock cycle, read the corresponding fgTS timeslot page configuration value, and use the read fgTS timeslot page configuration value and the current fgTS count value of the fifth counter as the read address of the second storage unit to obtain the fgODUflex channel number corresponding to the current fgTS, and so on, based on each clock cycle corresponding to the ODUk channel number, obtain the fgODUflex channel number corresponding to each fgTS of OPUk in the ODUk frame structure of the ODUk channel number.

6. The device according to claim 5, characterized in that The time slot search module includes a seventh counter, an eighth counter, a third storage unit, a fourth storage unit and an overhead time slot search unit, wherein: For each ODUk channel number, based on the ODUk channel number corresponding to the current clock cycle of the system clock and the ODU clock enable signal, an OPUk overhead enable signal is determined, and in response to the OPUk overhead enable signal, the seventh counter performs counting, caches the obtained OPUk frame count value, and in the next clock cycle corresponding to the ODUk channel number, the seventh counter accumulates the count on the last cached OPUk frame count value, and so on, in response to the seventh counter reaching 31, the count value of the eighth counter is increased by one, the obtained fgTSOH search page count value is cached, and the seventh counter performs counting, caches the obtained fgTSOH search page count value, and caches the obtained fgTSOH search page count value. The seventh counter is cleared, and the cached fgTSOH search page count value is used to add one to the cached fgTSOH search page count value when the seventh counter reaches 31 at the next OPUk frame count value, and so on, until the fgTSOH search page count value reaches Q, the fifth counter and the sixth counter are cleared, wherein Q indicates that there are Q*119 fgTSOHs in OPUk, the OPUk frame count value is used to indicate the number of 32 OPUk frames, and the fgTSOH search page count value is used to indicate the number of fgTSOH search pages; The third storage unit is used to store the preset fgTSOH time slot page configuration value into the storage space corresponding to each storage address by using the ODUk channel number and the fgTSOH search page count value as the storage address, wherein the fgTSOH search page count value is each count value generated by the eighth counter in any counting cycle, and the value range of the fgTSOH time slot page configuration value is 0 to the maximum value of the ODUk channel number -1; The fourth storage unit is used to store multiple overhead byte configuration tables, each of which includes 3 rows of table entries, each of which is used to store a group of fgTSOH overhead bytes, wherein the fgTSOH time slot page configuration value is used as the index number of the overhead byte configuration table, and the OPUk frame count value is used as the index number of each row of table entries, and the group of fgTSOH is obtained by sequentially dividing four fgTSOHs into a group according to 0-118 fgTSOH, and the OPUk frame count value is each count value generated by the seventh counter in any counting cycle, and the overhead bytes include the second parameter C of the previous multiframe cycle m T and overhead byte check code; The overhead time slot search unit is configured to use the ODUk channel number and the current fgTSOH search page count value of the eighth counter as the read address of the third storage unit in the current clock cycle, read the corresponding fgTSOH time slot page configuration value, and use the read fgTSOH time slot page configuration value as the index number to find the corresponding overhead byte configuration table in the fourth storage unit, use the current OPUk frame count value of the seventh counter as the index number to find the corresponding table entry in the overhead byte configuration table, obtain the four fgTSOH overhead bytes in the table entry, and so on, based on each clock cycle corresponding to the ODUk channel number, obtain each fgTSOH overhead byte of OPUk in the ODUk frame structure of the ODUk channel number.

7. The device according to claim 6, characterized in that The signal mapping module comprises: The fifth storage unit is used to store a fgGMP mapping configuration table, in which a corresponding relationship between the fgODUflex channel number and the preset fgGMP mapping parameters is established, and the fgGMP mapping parameters include parameters C 128 B. Parameter C 128,nor Parameter C 128 T, min Parameter C 128 T, max and parameter Pserver; The overhead updating unit is configured to update, for each fgODUflex channel number, a parameter C corresponding to the fgODUflex channel number according to a rate at which the fgODUflex data frame corresponding to the fgODUflex channel number is written into the cache module and a rate at which the fgODUflex data frame is read from the cache module. 128,min and parameter C 128,max Choose one of the two as the first parameter C ur C m , and the second parameter C of the current multiframe period m T is updated to the corresponding fgTSOH in the fourth storage unit, where the parameter C 128,min is parameter C 128 T, min and parameter C 128 B and, the parameter C 128,max is parameter C 128 T, min and parameter C 128 B and the second parameter C m T is the first parameter C ur C m With C 128 The difference of B.

8. The device according to claim 7, characterized in that The signal mapping module comprises: The overhead insertion unit is used to write the overhead bytes of each fgTSOH of OPUk in the ODUk frame structure of the ODUk channel number into each fgTSOH of the corresponding OPUk for each ODUk channel number, wherein the overhead bytes include the second parameter C of the current multiframe period. m T and overhead byte check code; The payload mapping unit is used to perform payload signal mapping processing on each fgTS in OPUk for each ODUk channel number, and the payload signal mapping processing includes: obtaining a first parameter C of fgTSOH corresponding to the fgTS ur C m , based on the first parameter C ur C m Perform fgGMP mapping on the fgTS and fgGMP mapping parameters to obtain each valid data area in the fgODTU.M frame structure, determine the data area enable signal of each valid data area, read the fgODUflex data frame of the fgTS corresponding to the fgODUflex channel number from the cache module based on each data area enable signal, and map it to each valid data area in the fgODTU.M frame structure to obtain the fgODTU.M frame corresponding to the fgTS, and then obtain the fgODTU.M frames corresponding to each fgTS, multiplex the fgODTU.M frame signal into M fgTS of OPUk, and based on the OPUk with the overhead bytes inserted, obtain the ODUk data frame corresponding to the ODUk channel number.

9. A data mapping method for a fine-grained optical transport network based on FPGA, characterized in that: The method comprises: Buffer fgODUflex data frames of multiple fgODUflex channels; According to the configured ODUk rate level k, the system clock and the external clock are processed to obtain the ODUk clock enable signal under the system clock, and then the ODUk clock enable signal corresponding to each ODUk channel number under the system clock is obtained, and each ODUk clock enable signal occupies the same data bus in a time division multiplexing form, where k=0, 1, 2, or flexn, flexn=3~7; For each clock cycle of the system clock, the following processing is performed: determining an ODUk channel number and an ODUk clock enable signal corresponding to a current clock cycle, performing byte counting in response to the ODUk clock enable signal, and then generating an ODUk frame structure corresponding to the ODUk channel number, wherein the ODUk frame structure is obtained by performing byte counting on each ODUk clock enable signal, and each ODUk clock enable signal is a clock enable signal in each clock cycle corresponding to the ODUk channel number; For each clock cycle of the system clock, performing the following processing: determining, based on the ODUk channel number and the ODUk clock enable signal corresponding to the current clock cycle, the fgODUflex channel number corresponding to each fgTS in the ODUk frame structure of the ODUk channel number, and determining the overhead byte corresponding to each fgTSOH in the ODUk frame structure; For each ODUk channel number, according to the fgODUflex channel numbers corresponding to the fgTS in the ODUk frame structure of the ODUk channel number, the corresponding fgODUflex data frame is read from the cache module and mapped to the corresponding fgTS in the ODUk frame structure, and the overhead byte is mapped to the corresponding fgTSOH in the ODUk frame structure to obtain the ODUk data frame of the ODUk channel number.

10. A communication device, characterized in that: It comprises a data mapping device for a fine-grained optical transport network based on FPGA as described in any one of claims 1-8.

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